Texas Instruments SN74LV8153N Handleiding

Texas Instruments Niet gecategoriseerd SN74LV8153N

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SCLS555 − JUNE 2004

DESCRIPTION

The SN74LV8153 is a serial-to-parallel data converter. It

accepts serial input data and outputs 8-bit parallel data.

The automatic data-rate detection feature of the

SN74LV8153 eliminates the need for an external oscillator

and helps with cost and board real-estate savings.

The OUTSEL pin is used to choose between open

collector and push-pull outputs. The open-collector option

is suitable when this device is used in applications such as

LED interface, where high drive current is required. SOUT

is the output that acknowledges reception of the serial

data.

To ensure the high-impedance state during power up or

power down, OE should be tied to VCC1 through a pullup

resistor; the minimum value of the resistor is determined

by the current-sinking capability of the driver.

N OR PW PACKAGE

(TOP VIEW)

VCC1

OUTSEL

RESET

SOUT

GND

VCC2

GND

FEATURES

DSingle-Wire Serial Data Input

DCompatible With UART Serial-Data Format

DUp to Eight Devices (64-Bit Parallel) Can

Share the Same Bus by Using Dierent

Combinations of A0, A1, A2

DUp to 40 mA Current Drive in Open-Collector

Mode for Driving LEDs

DOutputs Can be Congured as

Open-Collector or Push-Pull

DInternal Oscillator and Counter for

Automatic Data-Rate Detection

DOutput Levels Are Referenced to V CC2 and

Can Be Congured From 3 V to 12 V

DLatch-Up Performance Exceeds 250 mA Per

JESD 17

DESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 1000-V Charged-Device Model (C101)

SUMMARY OF RECOMMENDED

OPERATING CONDITIONS

PARAMETER

VCC1 3 V to 5.5 V

VCC2 3 V to 13.2 V

IOL 40 mA @ VCC2 = 4.5 V

(open-collector mode)

IOH −24 mA @ VCC2 = 12 V

(push-pull mode)

Maximum Data Rate 24 Kbps

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OUTSEL RESET OE Dn

OUTPUT

STRUCTURE

L H L H L

L H L L H

Open collector

L X H X H

Open collector

L L X X H

H H L H H

H H L L L

Push pull

H X H X Z

Push-pull

H L L X L

In the open-collector mode (OUTSEL = L), the outputs are inverted,

e.g., Y1 = l, when D1 = H

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

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SCLS555 − JUNE 2004

www.ti.com

ORDERING INFORMATION

TAPACKAGE(1) ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74LV8153N SN74LV8153N

−40° °C to 85 C

TSSOP PW

Tube SN74LV8153PW

LV8153

TSSOP − PW

Tape and reel SN74LV8153PWR

LV8153

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

PIN DESCRIPTION

PIN # PIN NAME I/O PIN FUNCTION

1 VCC1 Power-supply pin (all inputs and outputs except for Y0-Y7)

2-4 InA0, A1, A2 The address pins are used to program the address of the device and allow up to eight

devices to share the same bus.

5 D In Serial data input

6 OUTSEL In Choose between open-collector and push-pull type outputs (Y0-Y7).

7 RESET In Initialize register status

8 OE In Force Y0-Y7 to Hi-Z

9 SOUT Out Outputs a pulse when latch data is changed. Supplied by V

CC1

12-19 Y0-Y7 Out Push-pull or open collector parallel data outputs. Supplied by V

CC2.

20 VCC2 Power-supply pin for outputs (Y0-Y7). V

CC2 can range from 3 V to 13.2 V.

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SCLS555 − JUNE 2004

www.ti.com

data transmission protocol

− The serial data should be sent as 2START-3ADDRESS-4DATA-1STOP. Two consecutive serial-data

frames transmit 8 bits of data. The rst frame includes the lower four bits of data (D0-D3), and the

second frame includes the upper four bits (D4-D7).

− The three address bits (in the consecutive frame) must be the same as those in the rst frame;

otherwise, the data will be dropped.

− The order of the two start bits must be 0, then 1 in any frame; otherwise, the data rate will not be

detected correctly. The period between the falling edge of the rst start bit (ST0) and the rising edge of

the second start bit (ST1) is measured to generate an internal-clock synchronized data stream.

1st Frame 2nd Frame

DATA

Internal Clock

Y0−Y7

SOUT

Timing Chart

Example of Serial-Data Format

ST0

ST1 A0 A1 A2 D0 D1 D2 D3 SP

ST0

ST1 A0 A1 A2 D4 D5 D7 SP

ST0

ST1 A0 A1 A2 D0 D1 D2 D3 SP

ST0

ST1 A0 A1 A2 D4 D5 D7 SP

(1)Internal clock cannot be observed.

(2)D0 is LSB and D7 is MSB. The data stream should be LSB first.

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74LV8153N
Breedte:	26.92 mm
Diepte:	6.6 mm
Hoogte:	4.57 mm
Breedte verpakking:	13.97 mm
Diepte verpakking:	506 mm
Hoogte verpakking:	11.23 mm
Type verpakking:	PDIP
Aantal per verpakking:	20 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	-40 - 85 °C
Aantal pinnen:	20
Breedte (met pennen):	26.92 mm
Diepte (met pennen):	10.92 mm
Hoogte (met pennen):	8.26 mm