Texas Instruments SN74LV166ADR Handleiding

Texas Instruments Niet gecategoriseerd SN74LV166ADR

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SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D2-V to 5.5-V VCC Operation

DMax tpd of 10.5 ns at 5 V

DTypical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

DTypical VOHV (Output VOH Undershoot)

>2.3 V at VCC = 3.3 V, TA = 25°C

DIoff Supports Partial-Power-Down-Mode

Operation

DSynchronous Load

DDirect Overriding Clear

DParallel-to-Serial Conversion

DLatch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

SN54LV166A . . . J OR W PACKAGE

SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

SN54LV166A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SER

CLK INH

CLK

GND

VCC

SH/LD

CLR

3 2 1 20 19

9 10 11 12 13

CLK INH

SER

CLR

SH/LD

CLK

GND

description/ordering information

The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC D

Tube of 40 SN74LV166AD

LV166A

SOIC − D Reel of 2500 SN74LV166ADR LV166A

SOP − NS Reel of 2000 SN74LV166ANSR 74LV166A

40° °C to 85 C

SSOP − DB Reel of 2000 SN74LV166ADBR LV166A

−40° °C to 85 C Tube of 90 SN74LV166APW

TSSOP − PW Reel of 2000 SN74LV166APWR LV166A

TSSOP PW

Reel of 250 SN74LV166APWT

LV166A

TVSOP − DGV Reel of 2000 SN74LV166ADGVR LV166A

CDIP − J Tube of 25 SNJ54LV166AJ SNJ54LV166AJ

−55° °C to 125 C CFP − W Tube of 150 SNJ54LV166AW SNJ54LV166AW

LCCC − FK Tube of 55 SNJ54LV166AFK SNJ54LV166AFK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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   

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an

overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input.

When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each

clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs

on the next clock pulse. During parallel loading, serial data ow is inhibited. Clocking is accomplished on the

low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a

clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low

enables the other clock input. This allows the system clock to be free running, and the register can be stopped

on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

These devices are fully specied for partial-power-down applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLE

INPUTS

OUTPUTS

INPUTS

INTERNAL

CLR SH/LD CLK INH CLK SER PARALLEL

A . . . H Q

AQB

L X X X X X L L L

H X L L X X QA0 QB0 QH0

H L L ↑X a . . . h a b h

H H L ↑H X H Q

An QGn

H H L ↑L X L Q

An QGn

H X H X X Q↑A0 QB0 QH0

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   

SCLS456C − FEBRUARY 2001 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

SH/LD

CLR

CLK

CLK INH

2 3 4 5 10 11 12 14

SER

A B C D E F G H

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

typical clear, shift, load, inhibit, and shift sequence

Clear Load

Inhibit

H H H H H

LLL

CLK

CLK INH

SER

SH/LD

CLR

Parallel

Inputs

Serial Shift Serial Shift

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74LV166ADR
Breedte:	10 mm
Diepte:	4 mm
Hoogte:	1.5 mm
Breedte verpakking:	336.1 mm
Diepte verpakking:	340.5 mm
Hoogte verpakking:	32 mm
Soort:	Logic IC
Type verpakking:	SOIC
Aantal per verpakking:	2500 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	-40 - 85 °C
Aantal pinnen:	16
Breedte (met pennen):	10 mm
Diepte (met pennen):	6.2 mm
Hoogte (met pennen):	1.75 mm