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SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O − DECEMBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Inputs Are TTL-Voltage Compatible

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

1OE

2OE

GND

VCC

4OE

3OE

SN54AHCT125 . . . J OR W PACKAGE

SN74AHCT125 . . . D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

3OE

2OE

1OE

4OE

GND

SN54AHCT125 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74AHCT125 . . . RGY PACKAGE

(TOP VIEW)

1 14

7 8

4OE

3OE

2OE

1OE

3Y V

GND

description/ordering information

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.

Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective

gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74AHCT125RGYR HB125

PDIP − N Tube SN74AHCT125N SN74AHCT125N

SOIC D

Tube SN74AHCT125D

AHCT125

SOIC − D Tape and reel SN74AHCT125DR AHCT125

−40° °C to 85 C SOP − NS Tape and reel SN74AHCT125NSR AHCT125

SSOP − DB Tape and reel SN74AHCT125DBR HB125

TSSOP PW

Tube SN74AHCT125PW

HB125

TSSOP − PW Tape and reel SN74AHCT125PWR HB125

TVSOP − DGV Tape and reel SN74AHCT125DGVR HB125

CDIP − J Tube SNJ54AHCT125J SNJ54AHCT125J

−55° °C to 125 C CFP − W Tube SNJ54AHCT125W SNJ54AHCT125W

55 C

125 C

LCCC − FK Tube SNJ54AHCT125FK SNJ54AHCT125FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O − DECEMBER 1995 − REVISED JULY 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each buffer)

INPUTS OUTPUT

OE A

OUTPUT

L H H

L L L

H X Z

logic diagram (positive logic)

2A 2Y

2OE

1A 1Y

1OE

3A 3Y

3OE

4A 4Y

4OE

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.

SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCLS264O − DECEMBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC ) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC ) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65° °C to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

3. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 4)

SN54AHCT125 SN74AHCT125

UNIT

MIN MAX MIN MAX UNIT

VCC Supply voltage 4.5 5.5 4.5 5.5 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VI Input voltage 0 5.5 0 5.5 V

VO Output voltage 0 VCC 0 VCC V

IOH High-level output current −8 −8 mA

IOL Low-level output current 8 8 mA

Δ Δt/ v 20 20 ns/VInput transition rise or fall rate

TA Operating free-air temperature −55 125 −40 85 C°

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

Product specificaties

Merk:	Texas Instruments
Categorie:	Niet gecategoriseerd
Model:	SN74AHCT125PWR
Breedte:	5.1 mm
Diepte:	4.5 mm
Hoogte:	1.05 mm
Breedte verpakking:	364 mm
Diepte verpakking:	364 mm
Hoogte verpakking:	27 mm
Soort:	Logic IC
Type verpakking:	TSSOP
Aantal per verpakking:	2000 stuk(s)
Temperatuur bij opslag:	-65 - 150 °C
Bedrijfstemperatuur (T-T):	-40 - 125 °C
Aantal pinnen:	14
Breedte (met pennen):	5.1 mm
Diepte (met pennen):	6.6 mm
Hoogte (met pennen):	1.2 mm