Microchip SY89846U Handleiding

Microchip Niet gecategoriseerd SY89846U

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SY89846U
1.5G Precision, LVPECL 1:5 Fanout with 2:1 Hz
MUX and Fail Safe Input with Internal
Termination
Precision Edge®
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • http://www.micrel.com- -
Oct. 1, 2013
M9999-072211B
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY89846U is a 2.5/3.3V, 1:5 LVPECL fanout
buer with a 2:1 dierential input multiplexer (MUX).
A unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (voltage between
the pins of the dierential input drops signicantly
below 100mV).
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any dierential signal (AC- or DC-coupled) as small
as 100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
outputs are 800mV, LVPECL with fast rise/fall times
guaranteed to be less than 250ps.
The SY89846U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of 40°C to +85°C. The –
SY89846U is part of Micrel’s high-speed, Precision
Edge® product line.
All support documentation can be found on Micrel’s
web site at: . www.micrel.com
Functional Block Diagram
Precision Edge®
Features
ď‚·Selects between two inputs, and provides 5 precision
LVPECL copies
ď‚·Fail-Safe Input
–Prevents outputs from oscillating when input is
invalid
ď‚·Guaranteed AC performance over temperature and
supply voltage:
–DC-to >1.5GHz throughput
–< 900ps Propagation Delay (IN- -to Q)
–< 250ps Rise/Fall times
ď‚·Ultra-low jitter design:
–150fs RMS phase jitter (Typ)
–0.7psRMS MUX crosstalk induced jitter
ď‚·Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
ď‚·Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
ď‚·Wide input voltage range. VCC to GND
2.5V ±5% or 3.3 ±10% supply voltage
-40°C to +85°C industrial temperature range
ď‚·Available in 32-pin (5mm x 5mm) QFN package
Applications
ď‚·Fail-safe clock protection
ď‚·SONET clock distribution
ď‚·Backplane distribution
Markets
ď‚·LAN/WAN
ď‚·Enterprise servers
ď‚·ATE
ď‚·Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
Micrel, Inc. SY89846U
Oct. 1, 2013 M99 -072211B 99
hbwhelp@micrel.com or (408) 955-1690
2
Ordering Information (1)
Part Number
Package
Type
Package Marking
Lead Finish
SY89846UMG
QFN- 32
SY89846U with
Pb-Free bar-line Indicator
NiPdAu
Pb-Free
SY89846UMGTR(2)
QFN- 32
SY89846U with
Pb-Free bar-line Indicator
NiPdAu
Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
32 32)-Pin QFN (QFN-
Micrel, Inc. SY89846U
Oct. 1, 2013 M99 -072211B 99
hbwhelp@micrel.com or (408) 955-1690
3
Pin Description
Pin Number
Pin Name
Pin Function
1,8
VT0, VT1
Input Termination Center-Tap: Each side of a dierential input pair terminates to
the VT pin. The VT pin provides a center-tap for each input (IN, /IN) to a
termination network for maximum interface flexibility. See “Input Interface
Applications” subsection.
2, 3
6, 7
IN0, /IN0
IN1, /IN1
Dierential Inputs: These input pairs are the dierential signal inputs to the device.
These inputs accept AC- or DC-coupled signals as small as 100mV. The input
pairs internally terminate to a VT pin through 50Ω. Each input has level shifting
resistors of 3.72k to VCC. This allows a wide input voltage range from VCC to Ω
GND. See Figure 3a, Simplied Dierential Input Stage for details. Note that
these inputs will default to a valid (either HIGH or LOW) state if left open. See
“Input Interface Applications” subsection.
10, 11, 30, 31
GND,
Exposed Pad
Ground. Exposed pad must be connected to a ground plane that is the same
potential as the ground pins.
4
OE
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q4
outputs. It is internally connected to a 25k pull-up resistor and will default to a Ω
logic HIGH state if left open. When disabled, goes LOW and /Q goes HIGH. OE Q
being synchronous, outputs will be enabled/disabled following a rising and a falling
edge of the input clock. V
TH = VCC/2.
5
SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the
inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-
up resistor and will default to logic HIGH state if left open. V
TH = VCC/2.
9, 32
VREF-AC1
VREF-AC0
Reference Voltage: These outputs bias to V
CC–1.2V. They are used for AC-
coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin.
Bypass with 0.01µF low ESR capacitor to VCC. Due to limited drive capability, the
VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source
current is ±0.5mA. See subsection. “Input Interface Applications”
12, 13, 16, 19,
22, 25, 28, 29
VCC
Positive Power Supply: Bypass with 0.1µF 0.01µF low ESR capacitors as close to ||
the VCC pins as possible.
27, 26
24, 23
21, 20
18, 17
15, 14
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
LVPECL Dierential Output Pairs ierential buered output copies of the : D
selected input signal. The output swing is typically 800mV. Unused output pairs
may be left floating with no impact on jitter. See “LVPECL Output Termination”
subsection. Normally terminated with 50Ω to VCC-2V. These dierential LVPECL
outputs are a logic function of the IN0, IN1, and SEL inputs. See “Truth Table”
below.
Truth Table
Inputs
Outputs
IN0
/IN0
IN1
/IN1
SEL
Q
/Q
0
1
X
X
0
0
1
1
0
X
X
0
1
0
X
X
0
1
1
0
1
X
X
1
0
1
1
0

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: SY89846U

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