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Controller Area

Network (CAN)

Section 34. Controller Area Network (CAN)

HIGHLIGHT

This section of the manual contains the following topics:

34.1 Introduction..............................................................................................................34-2

34.2 CAN Message Formats ...........................................................................................34-4

34.3 CAN Registers.........................................................................................................34-9

34.4 Enabling and Disabling the CAN Module ..............................................................34-47

34.5 CAN Module Operating Modes.............................................................................. 34-47

34.6 CAN Message Handling ....................................................................................... 34-49

34.7 Transmitting a CAN Message................................................................................ 34-56

34.8 CAN Message Filtering.......................................................................................... 34-68

34.9 Receiving a CAN Message....................................................................................34-75

34.10 Bit Timing...............................................................................................................34-83

34.11 CAN Error Management ........................................................................................ 34-87

34.12 CAN Interrupts.......................................................................................................34-90

34.13 CAN Received Message Time Stamping............................................................... 34-94

34.14 Power-Saving Modes ............................................................................................34-95

34.15 Related Application Notes .....................................................................................34-96

34.16 Revision History..................................................................................................... 34-97

PIC32 Family Reference Manual

34.1 INTRODUCTION

The PIC32 Controller Area Network (CAN) module implements the CAN Specification 2.0B,

which is used primarily in industrial and automotive applications. This asynchronous serial data

communication protocol provides reliable communication in an electrically noisy environment.

The PIC32 device family integrates up to two CAN modules. Figure 34-1 illustrates a typical CAN

bus topology.

Figure 34-1: Typical CAN Bus Network

The CAN module supports the following key features:

• Standards Compliance:

- Full CAN Specification 2.0B compliance

- Programmable bit rate up to 1 Mbps

• Message Reception and Transmission:

- 32 message FIFOs

- Each FIFO can have up to 32 messages for a total of 1024 messages

- FIFO can be a transmit message FIFO or a receive message FIFO

- User-defined priority levels for message FIFOs used for transmission

- 32 acceptance filters for message filtering

- Four acceptance filter mask registers for message filtering

- Automatic response to Remote Transmit Request (RTR)

- DeviceNet™ addressing support

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Controller Area Network (CAN)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

CAN

bus

CAN1

PIC®

with Integrated

ECAN

CAN

Transceiver

dsPIC33F

with Integrated

ECAN™

dsPIC30F

with Integrated

CAN

Transceiver

CAN Transceiver

CAN

Transceiver

CAN

CAN2

CAN

Transceiver

PIC32

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

• Additional Features:

- Loopback, Listen All Messages and Listen-Only modes for self-test, system diagnostics

and bus monitoring

- Low-power operating modes

- CAN module is a bus master on the PIC32 system bus

- Does not require Direct Memory Access (DMA) channels for operation

- Dedicated time stamp timer

- Data-only Message Reception mode

Figure 34-2 illustrates the general structure of the CAN module.

Figure 34-2: PIC32 CAN Module Block Diagram

The CAN module consists of a protocol engine, message acceptance filters and Message

Assembly Buffers (MABs). The protocol engine transmits and receives messages to and from the

CAN bus (as per CAN Specification 2.0B). Received messages are assembled in the receive

message assembly buffer. The received message is then filtered by the message acceptance

filters. The transmit message assembly buffer holds the message to be transmitted as it is

processed by the protocol engine.

The CAN message buffers reside in device RAM. There are no CAN message buffers in the CAN

module. Therefore, all messages are stored in device RAM. The CAN module is a bus master on

the PIC32 system bus, and will read and write data to device RAM as required. The CAN module

does not use DMA for its operation and fetches messages from the device RAM without DMA or

CPU intervention.

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

FIFO0 FIFO1 FIFO31

Device RAM

Up to 32 Message Buffers

CAN Message FIFO (up to 32 FIFOs)

Message

Buffer Size

2 or 4 Words

System Bus

CPU

CAN Module

32 Filters

4 Masks

CxTX

CxRX

PIC32 Family Reference Manual

34.2 CAN MESSAGE FORMATS

The CAN bus protocol uses asynchronous communication. Information is passed from the

transmitters to receivers in data frames, which are composed of byte fields that define the

contents of the data frame as illustrated in Figure 34-3.

Each frame begins with a Start of Frame (SOF) bit field and terminates with an End of Frame

(EOF) bit field. The SOF is followed by the Arbitration and Control fields, which identify the

message type, format, length and priority. This information allows each node on the CAN bus to

respond appropriately to the message. The Data field conveys the message content and is of

variable length, ranging from 0 bytes to 8 bytes. Error protection is provided by the Cyclic

Redundancy Check (CRC) and Acknowledgement (ACK) fields.

Figure 34-3: CAN Bus Message Frame

The CAN bus protocol supports four frame types:

•Data Frame – carries data from transmitter to the receivers

•Remote Frame – transmitted by a node on the bus, to request transmission of a data

frame with the same identifier from another node

•Error Frame – transmitted by any node when it detects an error

•Overload Frame – provides an extra delay between successive Data or remote frames

•Interframe Space – provides a separation between successive frames

The CAN Specification 2.0B defines two additional data formats:

•Standard Data Frame – intended for standard messages that use 11 identifier bits

•Extended Data Frame – intended for extended messages that use 29 identifier bits

There are three CAN Specification versions:

•2.0A – considers 29-bit identifier as error

• 2.0B Passive – ignores 29-bit identifier messages

•2.0B Active – handles both 11-bit and 29-bit identifiers

The PIC32 CAN module is compliant with the CAN Specification 2.0B, while providing enhanced

message filtering capabilities.

Note: For detailed information on the CAN protocol, refer to the Bosch CAN Bus

Specification 2.0B, which is available for download at:

http://www.semiconductors.bosch.de

ARBITRATION CONTROL DATA ACKCRC

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.2.1 Standard Data Frame

The standard data frame message begins with an SOF bit followed by a 12-bit Arbitration field

as illustrated in Figure 34-4. The Arbitration field contains an 11-bit identifier and RTR bit. The

identifier defines the type of information contained in the message, and is used by each receiving

node to determine if the message is of interest to it. The RTR bit distinguishes a data frame from

a remote frame. For a standard data frame, the RTR bit is clear.

Following the Arbitration field is a 6-bit Control field, which provides more information about the

contents of the message. The first bit in the Control field is an Identifier Extension (IDE) bit, which

distinguishes the message as either a standard or extended data frame. A standard data frame

is indicated by a dominant state (logic level ‘0’) during transmission of the IDE bit. The second

bit in the Control field is a reserved (RB0) bit, which is in the dominant state (logic level ‘0’). The

last four bits in the Control field represent the Data Length Code (DLC), which specifies the

number of data bytes present in the message.

The Data field follows the Control field. This field carries the message data – the actual payload

of the data frame. This field is of variable length, ranging from 0 bytes to eight bytes. The number

of bytes is user-selectable.

The Data field is followed by the CRC field, which is a 15-bit CRC sequence with one delimiter bit.

The Acknowledgement (ACK) field is sent as a recessive bit (logic level ‘1’), and is overwritten

as a dominant bit by any receiver that has received the data correctly. The message is

acknowledged by the receiver regardless of the result of the acceptance filter comparison.

The last field is the EOF field, which consists of seven recessive bits that indicate the end of

message.

Figure 34-4: Format of the Standard Data Frame

SID10 SID1

IDENTIFIER

11 Bits

RB0 DLC

4 Bits

DATA

8 Bytes

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID0

9/19/2006 - 9/26/2006

11-bit Identifier

Interframe Space

9/19/2006 - 9/26/2006 9/19/2006 - 9/26/2006

Data

9/19/2006 - 9/26/2006

9 - 9/26/2006

Frame Interframe Space

9/19/2006 - 9/26/2006

IDE is Dominant (Logical ‘0’)

RTR is Dominant (Logical ‘0’)

RB0 is Dominant (Logical ‘0’)

/19/

Arbitration

Field

Control

Field

CRC

Field

ACK

Field

End-of-

PIC32 Family Reference Manual

34.2.2 Extended Data Frame

The extended data frame begins with an SOF bit followed by a 31-bit Arbitration field as

illustrated in Figure 34-5. The Arbitration field for the extended data frame contains 29 identifier

bits in two fields separated by a Substitute Remote Request (SRR) bit and an IDE bit. The SRR

bit determines if the message is a remote frame. SRR = 1 for extended data frames. The IDE bit

indicates the data frame type. For the extended data frame, IDE = 1.

The extended data frame Control field consists of seven bits. The first bit is the RTR. For the

extended data frame, RTR = 0. The next two bits, RB1 and RB0, are reserved bits that are in the

dominant state (logic level ‘0’). The last four bits in the Control field are the DLC, which specifies

the number of data bytes present in the message.

The remaining fields in an extended data frame are identical to a standard data frame.

Figure 34-5: Format of the Extended Data Frame

SID10 SID1

IDENTIFIER

11 Bits

DLC

4 BITS

CRC

16 BITS

ACK

2 BITS

EOF

7 BITS

IFS

3 BITS

SID0

Field

29-bit Identifier

9/19/2006 - 9/26/2006

Control

9/19/2006 - 9/26/2006

CRC

9/19/2006 - 9/26/2006

IDENTIFIER

18 BITS

EID17 EID1 EID0

IDE is Recessive (Logical ‘1’)

SRR is Recessive (Logical ‘1’)

RTR is Dominant (Logical ‘0’)

RB0 is Dominant (Logical ‘0’)

RB1 is Dominant (Logical ‘0’)

9/19/2006 - 9/26/2006

ACK End of

Frame

9/19/2006 - 9/26/20069/19/2006 - 9/26/2006

Data

DATA

8 Bytes

Arbitration

Field Field Field Field

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.2.3 Remote Frame

A node expecting to receive data from another node can initiate transmission of the respective

data by the source node, by sending a remote frame. A remote frame can be in standard format

(Figure Figure 34-6) or the extended format ( 34-7).

A Remote frame is similar to a data frame, with the following exceptions:

• The RTR bit is recessive (RTR = 1)

• There is no Data field (DLC = 0)

Figure 34-6: Format of the Standard Remote Frame

Figure 34-7: Format of the Extended Remote Frame

SID10 SID1

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID0

11-bit Identifier

RB0

IDE is Dominant (Logical ‘0’)

RTR is Recessive (Logical ‘1’)

RB0 is Dominant (Logical ‘0’)

Arbitration Field Control Field CRC Field ACK Field End of Frame

SID10 SID0

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID1

Arbitration Field

29-bit Identifier

Control Field CRC Field

IDENTIFIER

18 Bits

EID17 EID1 EID0

IDE is Recessive (Logical ‘1’)

SRR is Recessive (Logical ‘1’)

RTR is Recessive (Logical ‘1’)

RB0 is Dominant (Logical ‘0’)

RB1 is Dominant (Logical ‘0’)

ACK Field

End of

Frame

PIC32 Family Reference Manual

34.2.4 Error Frame

An error frame is generated by any node that detects a bus error. An error frame consists of an

Error Flag field followed by an Error Delimiter field. The Error Delimiter consists of eight recessive

bits and allows the bus nodes to restart communication cleanly after an error has occurred. There

are two types of error flag fields, depending on the error status of the node that detects the error:

•Error Active Flag – contains six consecutive dominant bits, which forces all other nodes

on the network to generate Error Echo Fags, thereby resulting in a series of 6 to 12

dominant bits on the bus

•Error Passive Flag – contains six consecutive recessive bits, with the result that unless

the bus error is detected by the transmitting node, the transmission of an Error Passive

Flag will not affect the communication of any other node on the network

34.2.5 Overload Frame

An Overload Frame can be generated by a node either when a dominant bit is detected during

Interframe Space or when a node is not ready to receive the next message (for example, if it is

still reading the previous received message). An Overload Frame has the same format as an

Error Frame with an Active Error Flag, but can only be generated during Interframe Space. It

consists of an Overload Fag field with six dominant bits followed by an Overload Delimiter field

with eight recessive bits. A node can generate a maximum of two sequential overload frames to

delay the start of the next message.

34.2.6 Interframe Space

Interframe Space separates successive frames being transmitted on the CAN bus. It consists of

at least three recessive bits, referred to as intermission. The Interframe Space allows nodes time

to internally process the previously received message before the start of the next frame. If the

transmitting node is in the Error Passive state, an additional eight recessive bits will be inserted

in the Interframe Space before any other message is transmitted by the node. This period is

called a Suspend Transmit field and allows time for other transmitting nodes to take control of the

bus.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.3 CAN REGISTERS

The CAN module registers can be classified by their function into the following groups:

• Module and CAN bit rate Configuration registers

• Interrupt and Status registers

• Mask and Filter Configuration registers

• FIFO Control registers

34.3.1 Module and CAN Bit Rate Configuration Registers

•CiCON: CAN Module Control Register

This register is used to set up the CAN module operational mode and DeviceNet

addressing.

•CiCFG: CAN Baud Rate Configuration Register

This register contains control bits to set the period of each time quantum, using the baud rate

prescaler, and specifies Synchronization Jump Width (SJW) in terms of time quanta. It is

also used to program the number of time quanta in each CAN bit segment, including the

propagation and phase segments 1 and 2.

34.3.2 Interrupt and Status Registers

•CiINT: CAN Interrupt Register

This register allows various CAN module interrupt sources to be enabled and disabled. It

also contains interrupt status flags.

•CiVEC: CAN Interrupt Code Register

This register provides status bits which provide information on CAN module interrupt source

and message filter hits. These values can be used to implement a jump table for handling

different cases.

•CiTREC: CAN Transmit/Receive Error Count Register

This register provides information on Transmit and Receive Error Counter values. It also has

bits which indicate various warning states.

•CiFSTAT: CAN FIFO Status Register

This register contains interrupt status flag for all the FIFOs.

•CiRXOVF: CAN Receive FIFO Overflow Status Register

This register contains overflow interrupt status flag for all the FIFOs.

•CiTMR: CAN TImer Register

This register contains CAN Message Timestamp timer and a Prescaler.

34.3.3 Mask and Filter Configuration Registers

•CiRXMn: CAN Acceptance Filter Mask n Register (n = 0, 1, 2 or 3)

These registers allow the configuration of the filter masks. A total of four masks are

available.

•CiFLTCON0: CAN Filter Control Register 0 through CiFLTCON7: CAN Filter Control

These registers allow the association of FIFO and Masks with a filter. A Filter can be

associated with any one mask. It also contains a filter enable/disable bit.

•CiRXFn: CAN Acceptance Filter n Register 7 (n = 0 through 31)

These registers specify the filter to be applied to the received message. A total of 32 filters

are available.

Note: The ‘i’ shown in the register identifier denotes CAN1 or CAN2.

PIC32 Family Reference Manual

34.3.4 CAN Module Control Registers

•CiFIFOBA: CAN Message Buffer Base Address Register

This register holds the base (start) address of the CAN message buffer area. This is a

physical address.

•CiFIFOCONn: CAN FIFO Control Register (n = 0 through 31)

These registers allow the control and configuration of CAN Message FIFOs.

•CiFIFOINTn: CAN FIFO Interrupt Register (n = 0 through 31)

These registers allow the individual FIFO interrupt sources to be enabled or disabled. They

also contain interrupt status bits.

•CiFIFOUAn: CAN FIFO User Address Register (n = 0 through 31)

These registers provide the addr the CAN message FIFO from ess of the memory location in

where the next message can be read or where the next message should be written to.

•CiFIFOCIn: CAN Module Message Index Register (n = 0 through 31)

These registers provide the message buffer index (in the message FIFO) of the next

message that the CAN module will transmit or where the next received message will be

saved.

Table 34-1 provides a summary of all CAN-related registers. Corresponding registers appear

after the summary, followed by a detailed description of each register. All unimplemented

registers and/or bits within a register read as zeros.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

Table 34-1: CAN Controller Register Summary

Name Bit

Range

Bit

31/2315/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

CiCON(1) 31:24 — — — — ABAT REQOP<2:0>

23:16 OPMOD<2:0> CANCAP — — — —

15:8 ON — — — — —SIDLE CANBUSY

7:0 — — — DNCNT<4:0>

CiCFG (1) 31:24 — — — — — — — —

23:16 — — — —WAKFIL SEG2PH<2:0>

15:8 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>

7:0 SJW<1:0> BRP<5:0>

CiINT (1) 31:24 IVRIE WAKIE CERRIE SERRIE RBOVIE — — —

23:16 — — — — MODIE CTMRIE RBIE TBIE

15:8 IVRIF WAKIF CERRIF SERRIF RBOVIF — — —

7:0 — — — — MODIF CTMRIF RBIF TBIF

CiVEC(1) 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — FILHIT<4:0>

7:0 — ICODE<6:0>

CiTREC(1) 31:24 — — — — — — — —

23:16 — — TXBO TXBP RXBP TXWARN RXWARN EWARN

15:8 TERRCNT<7:0>

7:0 RERRCNT<7:0>

CiFSTAT(1) 31:24 FIFOIP31 FIFOIP29 FIFOIP28 FIFOIP26 FIFOIP25FIFOIP30 FIFOIP27 FIFOIP24

23:16 FIFOIP23 FIFOIP21 FIFOIP20 FIFOIP18 FIFOIP17FIFOIP22 FIFOIP19 FIFOIP16

15:8 FIFOIP15 FIFOIP13 FIFOIP12FIFOIP14 FIFOIP11 FIFOIP8FIFOIP10 FIFOIP9

7:0 FIFOIP7 FIFOIP4 FIFOIP1FIFOIP6 FIFOIP5 FIFOIP3 FIFOIP2 FIFOIP0

CiRXOVF(1) 31:24 RXOVF31 RXOVF24RXOVF30 RXOVF29 RXOVF28 RXOVF25RXOVF27 RXOVF26

23:16 RXOVF23 RXOVF16RXOVF22 RXOVF21 RXOVF20 RXOVF17RXOVF19 RXOVF18

15:8 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF8RXOVF10 RXOVF9

7:0 RXOVF7 RXOVF4 RXOVF1RXOVF6 RXOVF5 RXOVF3 RXOVF2 RXOVF0

CiTMR(1) 31:24 CANTS<15:8>

23:16 CANTS<7:0>

15:8 CANTSPRE<15:8>

7:0 CANTSPRE<7:0>

CiRXM0(1) 31:24 SID<10:3>

23:16 SID<2:0> MIDE-— — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiRXM1(1) 31:24 SID<10:3>

23:16 SID<2:0> MIDE-— — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiRXM2(1) 31:24 SID<10:3>

23:16 SID<2:0> MIDE-— — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

Legend: ‘—’ = unimplemented; read as ‘0’.

Note 1: This register has an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, or 0xC bytes, respectively. These registers have

the same name with CLR, SET, or INV appended to the end of the register name (For example, CiCONCLR). Writing a ‘1’ to any bit

position in these registers will clear, set, or invert valid bits in the associated register. Reads from these registers should be ignored.

PIC32 Family Reference Manual

CiRXM3(1) 31:24 SID<10:3>

23:16 SID<2:0> MIDE-— — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiFLTCON0(1) 31:24 FLTEN3 MSEL3<1:0> FSEL3<4:0>

23:16 FLTEN2 MSEL2<1:0> FSEL2<4:0>

15:8 FLTEN1 MSEL1<1:0> FSEL1<4:0>

7:0 FLTEN0 MSEL0<1:0> FSEL0<4:0>

CiFLTCON1(1) 31:24 FLTEN7 MSEL7<1:0> FSEL7<4:0>

23:16 FLTEN6 MSEL6<1:0> FSEL6<4:0>

15:8 FLTEN5 MSEL5<1:0> FSEL5<4:0>

7:0 FLTEN4 MSEL4<1:0> FSEL4<4:0>

CiFLTCON2(1) 31:24 FLTEN11 MSEL11<1:0> FSEL11<4:0>

23:16 FLTEN10 MSEL10<1:0> FSEL10<4:0>

15:8 FLTEN9 MSEL9<1:0> FSEL9<4:0>

7:0 FLTEN8 MSEL8<1:0> FSEL8<4:0>

CiFLTCON3(1) 31:24 FLTEN15 MSEL15<1:0> FSEL15<4:0>

23:16 FLTEN14 MSEL14<1:0> FSEL14<4:0>

15:8 FLTEN13 MSEL13<1:0> FSEL13<4:0>

7:0 FLTEN12 MSEL12<1:0> FSEL12<4:0>

CiFLTCON4(1) 31:24 FLTEN19 MSEL19<1:0> FSEL19<4:0>

23:16 FLTEN18 MSEL18<1:0> FSEL18<4:0>

15:8 FLTEN17 MSEL17<1:0> FSEL17<4:0>

7:0 FLTEN16 MSEL16<1:0> FSEL16<4:0:

CiFLTCON5(1) 31:24 FLTEN23 MSEL23<1:0> FSEL23<4:0>

23:16 FLTEN22 MSEL22<1:0> FSEL22<4:0>

15:8 FLTEN21 MSEL21<1:0> FSEL21<4:0>

7:0 FLTEN20 MSEL20<1:0> FSEL20<4:0>

CiFLTCON6(1) 31:24 FLTEN27 MSEL27<1:0> FSEL27<4:0>

23:16 FLTEN26 MSEL26<1:0> FSEL26<4:0>

15:8 FLTEN25 MSEL25<1:0> FSEL25<4:0>

7:0 FLTEN24 MSEL24<1:0> FSEL24<4:0>

CiFLTCON7(1) 31:24 FLTEN31 MSEL31<1:0> FSEL31<4:0>

23:16 FLTEN30 MSEL30<1:0> FSEL30<4:0>

15:8 FLTEN29 MSEL29<1:0> FSEL29<4:0>

7:0 FLTEN28 MSEL28<1:0> FSEL28<4:0>

CiRXFn(1)

(n = 0 through 31)

31:24 SID<10:3>

23:16 SID<2:0> -— EXID — EID<17:16>

15:8 EID<15:8>

7:0 EID<7:0>

CiFIFOBA(1) 31:24 CiFIFOBA<31:24>

23:16 CiFIFOBA<23:16>

15:8 CiFIFOBA<15:8>

7:0 CiFIFOBA<7:0>

CiFIFOCONn(1)

(n = 0 through 31)

31:24 — — — — — — — —

23:16 — — — FSIZE<4:0>

15:8 — FRESET UINC DONLY — — — —

7:0 TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPR<1:0>

Table 34-1: CAN Controller Register Summary (Continued)

Name Bit

Range

Bit

31/2315/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: ‘—’ = unimplemented; read as ‘0’.

Note 1: This register has an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, or 0xC bytes, respectively. These registers have

the same name with CLR, SET, or INV appended to the end of the register name (For example, CiCONCLR). Writing a ‘1’ to any bit

position in these registers will clear, set, or invert valid bits in the associated register. Reads from these registers should be ignored.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

CiFIFOINTn(1)

(n = 0 through 31)

31:24 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE

23:16 — — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE

15:8 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF

7:0 — — — — RXOVFLIF RXFULLIF RXHALFIF RXNEMPTYIF

CiFIFOUAn(1)

(n = 0 through 31)

31:24 CiFIFOUA<31:24>

23:16 CiFIFOUA<23:16>

15:8 CiFIFOUA<15:8>

7:0 CiFIFOUA<7:0>

CiFIFOCIn(1)

(n = 0 through 31)

31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — CiFIFOCI<4:0>

Table 34-1: CAN Controller Register Summary (Continued)

Name Bit

Range

Bit

31/2315/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: ‘—’ = unimplemented; read as ‘0’.

Note 1: This register has an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, or 0xC bytes, respectively. These registers have

the same name with CLR, SET, or INV appended to the end of the register name (For example, CiCONCLR). Writing a ‘1’ to any bit

position in these registers will clear, set, or invert valid bits in the associated register. Reads from these registers should be ignored.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0

— — — — ABAT REQOP<2:0>

23:16 R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0

OPMOD<2:0> CANCAP — — — —

15:8 R/W-0 U-0 U-0R/W-0 U-0 R-0 U-0 U-0

ON(1) — — — — —SIDLE CANBUSY

7:0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DNCNT<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 Unimplemented: Read as ‘0’

bit 27 ABAT: Abort All Pending Transmissions bit

1 = Signal all transmit buffers to abort transmission

0 = Module will clear this bit when all transmissions aborted

bit 26-24 REQOP<2:0>: Request Operation Mode bits

111 = Set Listen All Messages mode

110 = Reserved; do not use

101 = Reserved; do not use

100 = Set Configuration mode

011 = Set Listen-Only mode

010 = Set Loopback mode

001 = Set Disable mode

000 = Set Normal Operation mode

bit 23-21 OPMOD<2:0>: Operation Mode Status bits

111 = Module is in Listen All Messages mode

110 = Reserved

101 = Reserved

100 = Module is in Configuration mode

011 = Module is in Listen-Only mode

010 = Module is in Loopback mode

001 = Module is in Disable mode

000 = Module is in Normal Operation mode

bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit

1 = CANTMR value is stored on valid message reception and is stored with the message

0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power

bit 19-16 Unimplemented: Read as ‘0’

bit 15 ON: CAN On bit(1)

1 = CAN module is enabled

0 = CAN module is disabled

bit 14 Unimplemented: Read as ‘0’

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the

current transaction and responds to this request. The user application should poll the CANBUSY bit to

verify that the request has been honored.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 13 SIDLE: CAN Stop in Idle bit

1 = CAN Stops operation when system enters Idle mode

0 = CAN continues operation when system enters Idle mode

bit 12 Unimplemented: Read as ‘0’

bit 11 CANBUSY: CAN Module is Busy bit

1 = The CAN module is active

0 = The CAN module is completely disabled

bit 10-5 Unimplemented: Read as ‘0’

bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits

11111 = Invalid Selection (compare up to 18-bits of data with EID)

•

10011 = Invalid Selection (compare up to 18-bits of data with EID)

10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)

•

00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)

00000 = Do not compare data bytes

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the

current transaction and responds to this request. The user application should poll the CANBUSY bit to

verify that the request has been honored.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0U-0

— — — — — — — —

23:16 U-0 R/W-0 R/W-0 R/W-0U-0 U-0 U-0 R/W-0

— — — —WAKFIL SEG2PH<2:0>(1,4)

15:8 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

SEG2PHTS(1) SAM(2) SEG1PH<2:0> PRSEG<2:0>

7:0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

SJW<1:0>(3) BRP<5:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as ‘0’

bit 22 WAKFIL: CAN Bus Line Filter Enable bit

1 = Use CAN bus line filter for wake-up

0 = CAN bus line filter is not used for wake-up

bit 21-19 Unimplemented: Read as ‘0’

bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits

(1,5)

111 = Length is 8 x TQ

•

000 = Length is 1 x TQ

bit 15 SEG2PHTS: Phase Segment 2 Time Select bit

(1)

1 = Freely programmable

0 = Maximum of SEG1PH or Information Processing Time, whichever is greater

bit 14 SAM: Sample of the CAN Bus Line bit(2)

1 = Bus line is sampled three times at the sample point

0 = Bus line is sampled once at the sample point

bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits

(4)

111 = Length is 8 x TQ

•

000 = Length is 1 x TQ

Note 1: SEG2PH ≤ SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.

3: SJW ≤ SEG2PH.

4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(CiCON<23:21>) = 100).

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 10-8 PRSEG<2:0>: Propagation Time Segment bits

(4)

111 = Length is 8 x TQ

•

000 = Length is 1 x TQ

bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3)

11 = Length is 4 x TQ

10 = Length is 3 x TQ

01 = Length is 2 x TQ

00 = Length is 1 x TQ

bit 5-0 BRP<5:0>: Baud Rate Prescaler bits

111111 = TQ = (2 x 64)/FSYS

111110 = TQ = (2 x 63)/FSYS

•

000001 = TQ = (2 x 2)/FSYS

000000 = TQ = (2 x 1)/FSYS

Note 1: SEG2PH ≤ SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.

3: SJW ≤ SEG2PH.

4: The Time Quanta per bit must be greater than 7 (that is, T

QBIT > 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(CiCON<23:21>) = 100).

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 U-0 U-0 U-0

IVRIE WAKIE CERRIE SERRIE RBOVIE — — —

23:16 U-0 U-0 U-0 U-0 R/W-0 R/W-0R/W-0 R/W-0

— — — — MODIE CTMRIE RBIE TBIE

15:8 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 U-0 U-0 U-0

IVRIF WAKIF CERRIF SERRIF(1) RBOVIF — — —

7:0 U-0 U-0 U-0 U-0 R/W-0 R/W-0R/W-0 R/W-0

— — — — MODIF CTMRIF RBIF TBIF

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 IVRIE: Invalid Message Received Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 29 CERRIE: CAN Bus Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 28 SERRIE: System Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 26-20 Unimplemented: Read as ‘0’

bit 19 MODIE: Mode Change Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 17 RBIE: Receive Buffer Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 16 TBIE: Transmit Buffer Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 15 IVRIF: Invalid Message Received Interrupt Flag bit

1 = An invalid messages interrupt has occurred

0 = An invalid message interrupt has not occurred

bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit

1 = A bus wake-up activity interrupt has occurred

0 = A bus wake-up activity interrupt has not occurred

Note 1: This bit can only be cleared by turning the CAN module OFF and ON by clearing or setting the ON bit

(CiCON<15>).

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 13 CAN Bus Error Interrupt Flag bitCERRIF:

1 = A CAN bus error has occurred

0 = A CAN bus error has not occurred

bit 12 SERRIF: System Error Interrupt Flag bit

1 = A system error occurred (typically an illegal address was presented to the system bus)

0 = A system error has not occurred

bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit

1 = A receive buffer overflow has occurred

0 = A receive buffer overflow has not occurred

bit 10-4 Unimplemented: Read as ‘0’

bit 3 MODIF: CAN Mode Change Interrupt Flag bit

1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)

0 = A CAN module mode change has not occurred

bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit

1 = A CAN timer (CANTMR) overflow has occurred

0 = A CAN timer (CANTMR) overflow has not occurred

bit 1 RBIF: Receive Buffer Interrupt Flag bit

1 = A receive buffer interrupt is pending

0 = A receive buffer interrupt is not pending

bit 0 TBIF: Transmit Buffer Interrupt Flag bit

1 = A transmit buffer interrupt is pending

0 = A transmit buffer interrupt is not pending

Note 1: This bit can only be cleared by turning the CAN module OFF and ON by clearing or setting the ON bit

(CiCON<15>).

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — FILHIT<4:0>

7:0 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE<6:0>(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12-8 Filter Hit Number bitFILHIT<4:0>:

11111 = Filter 31

11110 = Filter 30

•

00001 = Filter 1

00000 = Filter 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)

1111111 = Reserved

•

1001000 = Reserved

1001000 = Invalid message received (IVRIF)

1000111 = CAN module mode change (MODIF)

1000110 = CAN timestamp timer (CTMRIF)

1000101 = Bus bandwidth error (SERRIF)

1000100 = Address error interrupt (SERRIF)

1000011 = Receive FIFO overflow interrupt (RBOVIF)

1000010 = Wake-up interrupt (WAKIF)

1000001 = Error Interrupt (CERRIF)

1000000 = No interrupt

0111111 = Reserved

•

0100000 = Reserved

0011111 = FIFO31 Interrupt (CiFSTAT<31> set)

0011110 = FIFO30 Interrupt (CiFSTAT<30> set)

•

0000001 = FIFO1 Interrupt (CiFSTAT<1> set)

0000000 = FIFO0 Interrupt (CiFSTAT<0> set)

Note 1: These bits are only updated for enabled interrupts.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — TXBO TXBP RXBP TXWARN RXWARN EWARN

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TERRCNT<7:0>

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-22 Unimplemented: Read as ‘0’

bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT ≥ 256)

bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT ≥ 128)

bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT ≥ 128)

bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT ≥ 96)

bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT ≥ 96)

bit 16 EWARN: Transmitter or Receiver is in Error State Warning

bit 15-8 TERRCNT<7:0>: Transmit Error Counter

bit 7-0 RERRCNT<7:0>: Receive Error Counter

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP31 FIFOIP30 FIFOIP25FIFOIP29 FIFOIP26FIFOIP28 FIFOIP27 FIFOIP24

23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP23 FIFOIP22 FIFOIP17FIFOIP21 FIFOIP18FIFOIP20 FIFOIP19 FIFOIP16

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP15 FIFOIP14 FIFOIP11FIFOIP13 FIFOIP12 FIFOIP10 FIFOIP8FIFOIP9

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FIFOIP7 FIFOIP0FIFOIP6 FIFOIP5 FIFOIP1FIFOIP4 FIFOIP3 FIFOIP2

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 FIFOIP<31:0>: FIFOn Interrupt Pending bits

1 = One or more enabled FIFO interrupts are pending

0 = No FIFO interrupts are pending

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0R-0

RXOVF31 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF24RXOVF30 RXOVF25

23:16 R-0 R-0 R-0 R-0 R-0 R-0 R-0R-0

RXOVF23 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF16RXOVF22 RXOVF17

15:8 R-0 R-0 R-0 R-0 R-0 R-0 R-0R-0

RXOVF15 RXOVF13 RXOVF12RXOVF14 RXOVF11 RXOVF10 RXOVF9 RXOVF8

7:0 R-0 R-0 R-0 R-0 R-0 R-0 R-0R-0

RXOVF7 RXOVF4 RXOVF2RXOVF6 RXOVF5 RXOVF3 RXOVF1 RXOVF0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared

bit 31-0 RXOVF<31:0>: FIFOn Receive Overflow Interrupt Pending bit

1 = FIFO has overflowed

0 = FIFO has not overflowed

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CANTS<15:8>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CANTS<7:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CANTSPRE<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CANTSPRE<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR x = Bit is unknown‘1’ = Bit is set ‘0’ = Bit is cleared

bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits

This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit

(CiCON<20>) is set.

bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits

65535 = CAN time stamp timer (CANTS) increments every 65,535 system clocks

•

0 = CAN time stamp timer (CANTS) increments every system clock

Note 1: CiTMR will be frozen when CANCAP = 0.

2: The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

SID<10:3>

23:16 R/W-0 R/W-0 R/W-0R/W-0 U-0 U-0R/W-0 R/W-0

SID<2:0> — —MIDE EID<17:16>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

EID<15:8>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

EID<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared

bit 31-21 SID<10:0>: Standard Identifier bits

1 = Include bit, SIDx, in filter comparison

0 = Bit SIDx is ‘don’t care’ in filter operation

bit 20 Unimplemented: Read as ‘0’

bit 19 MIDE: Identifier Receive Mode bit

1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter

0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message

SID) or if (FILTER SID/EID) = (Message SID/EID))

bit 18 Unimplemented: Read as ‘0’

bit 17-0 EID<17:0>: Extended Identifier bits

1 = Include bit, EIDx, in filter comparison

0 = Bit EIDx is ‘don’t care’ in filter operation

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>

(CiCON<23:21>) = 100).

PIC32 Family Reference Manual

Bit Range Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN3 MSEL3<1:0> FSEL3<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN2 MSEL2<1:0> FSEL2<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN1 MSEL1<1:0> FSEL1<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN0 MSEL0<1:0> FSEL0<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared

bit 31 FLTEN3: Filter 3 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL3<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN2: Filter 2 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL2<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN1: Filter 1 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL1<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN0: Filter 0 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL0<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN7 MSEL7<1:0> FSEL7<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN6 MSEL6<1:0> FSEL6<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN5 MSEL5<1:0> FSEL5<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN4 MSEL4<1:0> FSEL4<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN7: Filter 7 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL7<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN6: Filter 6 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL6<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN5: Filter 5 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL5<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN4: Filter 4 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL4<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

FLTEN11 MSEL11<1:0> FSEL11<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

FLTEN10 MSEL10<1:0> FSEL10<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

FLTEN9 MSEL9<1:0> FSEL9<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

FLTEN8 MSEL8<1:0> FSEL8<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN11: Filter 11 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL11<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN10: Filter 10 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL10<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN9: Filter 9 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL9<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN8: Filter 8 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL8<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN15 MSEL15<1:0> FSEL15<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN14 MSEL14<1:0> FSEL14<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN13 MSEL13<1:0> FSEL13<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN12 MSEL12<1:0> FSEL12<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN15: Filter 15 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL15<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN14: Filter 14 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL14<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN13: Filter 13 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL13<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN12: Filter 12 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL12<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN19 MSEL19<1:0> FSEL19<4:0>

23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN18 MSEL18<1:0> FSEL18<4:0>

15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN17 MSEL17<1:0> FSEL17<4:0>

7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN16 MSEL16<1:0> FSEL16<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set x = Bit is unknown‘0’ = Bit is cleared

bit 31 FLTEN19: Filter 19 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL19<1:0>: Filter 19 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL19<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN18: Filter 18 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL18<1:0>: Filter 18 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL18<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN17: Filter 17 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL17<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN16: Filter 16 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL16<1:0>: Filter 16 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL16<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN21: Filter 21 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL21<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN20: Filter 20 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL20<1:0>: Filter 20 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL20<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN27 MSEL27<1:0> FSEL27<4:0>

23:16 R/W-0 R/W-0R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN26 MSEL26<1:0> FSEL26<4:0>

15:8 R/W-0 R/W-0R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN25 MSEL25<1:0> FSEL25<4:0>

7:0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

FLTEN24 MSEL24<1:0> FSEL24<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN27: Filter 27 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL27<1:0>: Filter 27 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL27<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN26: Filter 26 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL26<1:0>: Filter 26 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL26<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN25: Filter 25 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL25<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN24: Filter 24 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL24<1:0>: Filter 24 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL24<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN31 MSEL31<1:0> FSEL31<4:0>

23:16 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN30 MSEL30<1:0> FSEL30<4:0>

15:8 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN29 MSEL29<1:0> FSEL29<4:0>

7:0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

FLTEN28 MSEL28<1:0> FSEL28<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN31: Filter 31 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 28-24 FSEL31<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 23 FLTEN30: Filter 30 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 22-21 MSEL30<1:0>: Filter 30 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 20-16 FSEL30<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 15 FLTEN29: Filter 29 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 12-8 FSEL29<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

bit 7 FLTEN28: Filter 28 Enable bit

1 = Filter is enabled

0 = Filter is disabled

bit 6-5 MSEL28<1:0>: Filter 28 Mask Select bits

11 = Acceptance Mask 3 selected

10 = Acceptance Mask 2 selected

01 = Acceptance Mask 1 selected

00 = Acceptance Mask 0 selected

bit 4-0 FSEL28<4:0>: FIFO Selection bits

11111 = Message matching filter is stored in FIFO buffer 31

11110 = Message matching filter is stored in FIFO buffer 30

•

00001 = Message matching filter is stored in FIFO buffer 1

00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0U-0

— — — — — — — —

23:16 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FSIZE<4:0>(1)

15:8 U-0 U-0 U-0 U-0S/HC-0 S/HC-0 R/W-0 U-0

— FRESET UINC DONLY(1) — — — —

7:0 R/W-0 R/W-0 R/W-0R-0 R-0 R-0 R/W-0 R/W-0

TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>

Legend: S = Settable bit HC = Hardware clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 FSIZE<4:0>: FIFO Size bits(1)

11111 = FIFO is 32 messages deep

•

00010 = FIFO is 3 messages deep

00001 = FIFO is 2 messages deep

00000 = FIFO is 1 message deep

bit 15 Unimplemented: Read as ‘0’

bit 14 FRESET: FIFO Reset bits

1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should

poll if this bit is clear before taking any action

0 = No effect

bit 13 UINC: Increment Head/Tail bit

TXEN = 1: (FIFO configured as a Transmit FIFO)

When this bit is set the FIFO head will increment by a single message

TXEN = 0: (FIFO configured as a Receive FIFO)

When this bit is set the FIFO tail will increment by a single message

bit 12 DONLY: Store Message Data Only bit(1)

TXEN = 1: (FIFO configured as a Transmit FIFO)

This bit is not used and has no effect.

TXEN = 0: (FIFO configured as a Receive FIFO)

1 = Only data bytes will be stored in the FIFO

0 = Full message is stored, including identifier

bit 11-8 Unimplemented: Read as ‘0’

bit 7 TXEN: TX/RX Buffer Selection bit

1 = FIFO is a Transmit FIFO

0 = FIFO is a Receive FIFO

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(CiCON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 6 TXABAT: Message Aborted bit(2)

1 = Message was aborted

0 = Message completed successfully

bit 5 TXLARB: Message Lost Arbitration bit(3)

1 = Message lost arbitration while being sent

0 = Message did not loose arbitration while being sent

bit 4 TXERR: Error Detected During Transmission bit(3)

1 = A bus error occured while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3 TXREQ: Message Send Request

TXEN = 1: (FIFO configured as a Transmit FIFO)

Setting this bit to ‘1’ requests sending a message.

The bit will automatically clear when all the messages queued in the FIFO are successfully sent

Clearing the bit to ‘0’ while set (‘1’) will request a message abort.

TXEN = 0: (FIFO configured as a Receive FIFO)

This bit has no effect.

bit 2 RTREN: Auto RTR Enable bit

1 = When a remote transmit is received, TXREQ will be set

0 = When a remote transmit is received, TXREQ will be unaffected

bit 1-0 TXPR<1:0>: Message Transmit Priority bits

11 = Highest Message Priority

10 = High Intermediate Message Priority

01 = Low Intermediate Message Priority

00 = Lowest Message Priority

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits

(CiCON<23:21>) = 100).

2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.

3: This bit is reset on any read of this register or when the FIFO is reset.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0U-0 R/W-0 R/W-0 R/W-0

— — — — — TXNFULLIE TXHALFIE TXEMPTYIE

23:16 U-0 U-0 U-0U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE

15:8 U-0 U-0 U-0 U-0 R-0 R-0 R-0U-0

— — — — — TXNFULLIF(1) TXHALFIF TXEMPTYIF(1)

7:0 U-0 U-0 U-0 R-0 R-0 R-0U-0 R/W-0

— — — — RXOVFLIF RXFULLIF(1) RXHALFIF(1) RXNEMPTYIF(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-27 Unimplemented: Read as ‘0’

bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit

1 = Interrupt enabled for FIFO not full

0 = Interrupt disabled for FIFO not full

bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit

1 = Interrupt enabled for FIFO half full

0 = Interrupt disabled for FIFO half full

bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit

1 = Interrupt enabled for FIFO empty

0 = Interrupt disabled for FIFO empty

bit 23-20 Unimplemented: Read as ‘0’

bit 19 RXOVFLIE: Overflow Interrupt Enable bit

1 = Interrupt enabled for overflow event

0 = Interrupt disabled for overflow event

bit 18 RXFULLIE: Full Interrupt Enable bit

1 = Interrupt enabled for FIFO full

0 = Interrupt disabled for FIFO full

bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit

1 = Interrupt enabled for FIFO half full

0 = Interrupt disabled for FIFO half full

bit 16 RXNEMPTYIE: Empty Interrupt Enable bit

1 = Interrupt enabled for FIFO not empty

0 = Interrupt disabled for FIFO not empty

bit 15-11 Unimplemented: Read as ‘0’

bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

1 = FIFO is not full

0 = FIFO is full

TXEN = 0: (FIFO configured as a Receive Buffer)

Unused, reads ‘0’

Note 1: This bit is read-only and reflects the status of the FIFO.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

1 = FIFO is ≤ half full

0 = FIFO is > half full

TXEN = 0: (FIFO configured as a Receive Buffer)

Unused, reads ‘0’

bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

1 = FIFO is empty

0 = FIFO is not empty, at least 1 message queued to be transmitted

TXEN = 0: (FIFO configured as a Receive Buffer)

Unused, reads ‘0’

bit 7-4 Unimplemented: Read as ‘0’

bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit

TXEN = 1: (FIFO configured as a Transmit Buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a Receive Buffer)

1 = Overflow event has occurred

0 = No overflow event occured

bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a Receive Buffer)

1 = FIFO is full

0 = FIFO is not full

bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a Receive Buffer)

1 = FIFO is ≥ half full

0 = FIFO is < half full

bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit

(1)

TXEN = 1: (FIFO configured as a Transmit Buffer)

Unused, reads ‘0’

TXEN = 0: (FIFO configured as a Receive Buffer)

1 = FIFO is not empty, has at least 1 message

0 = FIFO is empty

Note 1: This bit is read-only and reflects the status of the FIFO.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 R-x R-xR-x R-x R-x R-x R-x R-x

CiFIFOUAn<31:24>

23:16 R-x R-xR-x R-x R-x R-x R-x R-x

CiFIFOUAn<23:16>

15:8 R-x R-xR-x R-x R-x R-x R-x R-x

CiFIFOUAn<15:8>

7:0 R-x R-x R-0R-x R-x R-x R-x (2) R-0(2)

CiFIFOUAn<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits

TXEN = 1: (FIFO configured as a Transmit Buffer)

A read of this register will return the address where the next message is to be written (FIFO head).

TXEN = 0: (FIFO configured as a Receive Buffer)

A read of this register will return the address where the next message is to be read (FIFO tail).

Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.

Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when

the module is not in Configuration mode.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

7:0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — CiFIFOCI<4:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-5 Unimplemented: Read as ‘0’

bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits

TXEN = 1: (FIFO configured as a Transmit Buffer)

A read of this register will return an index to the message that the FIFO will next attempt to transmit.

TXEN = 0: (FIFO configured as a Receive Buffer)

A read of this register will return an index to the message that the FIFO will use to save the next message.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.4 ENABLING AND DISABLING THE CAN MODULE

When the CAN module is OFF, the entire CAN module is held in reset, with only the CAN module

Special Function Registers (SFRs) being user-accessible. The CAN module can be enabled by

setting the ON bit in the CAN Control register (CiCON<15>). When the ON bit (CiCON<15>) is

set, the CAN module is active and the CAN module will request priority on the CAN TX (CiTX)

and RX (CiRX) pins.

Turning the CAN module OFF will place the CAN module into reset and release device control

of the CiTX and CiRX pins. All message FIFOs are reset when the CAN module is turned OFF.

It may take a number of clocks for the CAN module to fully turn OFF. The CAN Module is Busy

(CANBUSY) bit in the CAN Module Control register (CiCON<11>) gives a status of the CAN

module. The user should poll the CANBUSY bit (CiCON<11>) to ensure that the CAN module

has been turned OFF. In addition, it is important to ensure that the CAN module is in

Configuration mode (see 34.5 “CAN Module Operating Modes”) before turning the CAN

module OFF. This prevents bus errors caused by the CAN module being turned OFF during the

transmitting of message. Example 34-1 demonstrates the necessary steps to switch the CAN1

module OFF.

Example 34-1: Disabling the CAN1 Module

34.5 CAN MODULE OPERATING MODES

The CAN module can operate in one of the following modes selected by the user application:

• Configuration mode

• Normal Operation mode

• Listen-Only mode

• Listen All Messages mode

• Loopback mode

• Disable mode

The operating modes are requested by the user application that is writing to the Request

Operation Mode bits (REQOP<2:0>) in the CAN Control register (CiCON<26:24>). The CAN

module acknowledges entry into the requested mode by the Operation Mode bits

(OPMOD<2:0>) in the CAN Control register (CiCON<23:21>). Mode transition is performed in

synchronization with the CAN network.

The user application can choose to be interrupted when a requested mode change has occurred

by enabling the Mode Change Interrupt (MODIE) bit in the CAN Interrupt register (CiINT<19>).

When the new mode has been successfully applied, a CAN interrupt will be generated.

Alternatively, the user can elect to poll the OPMOD<2:0> bits (CiCON<23:21>) to determine

when the CAN module has successfully switched modes (current operation mode matches the

requested operation mode).

/* Place the CAN module in Configuration mode. */

C1CONbits.REQOP = 4;

while(C1CONbits.OPMOD != 4);

/* Switch the CAN module off. */

C1CONCLR = 0x00008000; /*Clear the ON bit */

while(C1CONbits.CANBUSY == 1);

PIC32 Family Reference Manual

34.5.1 Configuration Mode

After a device reset, the CAN module is in Configuration mode (OPMOD<2:0> bits

(CiCON<23:21>) = 100). The error counters are cleared and all registers contain the reset

values. The CAN module can be configured or initialized only in Configuration mode.

Configuration mode is requested by programming the REQOP<2:0> bits (CiCON<26:24>)

to ‘100’. The user application should wait until the CAN module is actually in Configuration mode.

This is done by polling the OPMOD<2:0> bits (CiCON<23:21>) for a value of ‘100’. The following

registers and bits can be modified in Configuration mode only:

• CAN Configuration register (CiCFG)

• CAN FIFO Base Address register (CiFIFOBA)

• CAN Acceptance Filter Mask register (CiRXMn)

• FIFO Size (FSIZE<4:0>) bits in the CAN FIFO Control register (CiFIFOCONn<20:16>) and

the Store Message Data Only (DONLY) bit (CiFIFOCONn<12>)

This protects the user from accidentally violating the CAN protocol through programming errors.

34.5.2 Normal Operation Mode

In Normal Operation mode, the CAN module will be on the CAN bus, and can transmit and

receive CAN messages. Normal Operation mode is requested after initialization by programming

the REQOP<2:0> bits (CiCON<26:24>) to ‘000’. When OPMOD<2:0> = 000, the CAN module

proceeds with normal operation. The CAN module will check for bus idle condition before

entering the Normal Operation mode.

34.5.3 Listen-Only Mode

The Listen-only mode is a variant of Normal Operation mode. If Listen-Only mode is activated,

the CAN module is present on the CAN bus but is passive. It will receive messages but not

transmit. The CAN module will not generate error flags and will not acknowledge signals. The

error counters are deactivated in this state. Listen-Only mode can be used for detecting the baud

rate on the CAN bus. For this to occur, it is necessary that at least two other nodes are present

that communicate with each other. The baud rate can be detected empirically by testing different

values. This mode is also useful as a bus monitor, as the CAN bus does not influence the data

traffic.

34.5.4 Listen All Messages Mode

The Listen All Messages mode is a variant of Normal Operation mode. If Listen All Messages

mode is activated, transmission and reception operate the same as normal operation mode with

the exception that if a message is received with an error, it will be transferred to the receive buffer

as if there was no error. The receive buffer will contain data that was received up to the error. The

filters still need to be enabled and configured.

34.5.5 Loopback Mode

Loopback mode is used for self-test to allow the CAN module to receive its own message. In this

mode, the CAN module transmit path is connected internally to the receive path. A “dummy”

acknowledge is provided, thereby eliminating the need for another node to provide the

Acknowledge bit. The CAN message is not actually transmitted on the CAN bus.

34.5.6 Disable Mode

Disable mode is similar to Configuration mode, except that the CAN module error counters are

not reset. The CAN module is placed in Disable mode by setting the REQOP<2:0> bits

(CiCON<26:24>) to ‘001’. In Disable mode, the CAN module’s internal clock will stop unless the

CAN module is receiving or transmitting a message. The CAN module will not be allowed to enter

Disable mode while a transmission or reception is taking place to prevent the CAN module from

causing errors on the system bus. The CAN module will enter Disable mode when the current

message completes. The OPMOD<2:0> bits (CiCON<23:21>) indicate whether the CAN module

successfully went into Disable mode. The CAN module Transmit (CiTX) pin will stay in the

recessive state while the CAN module is in Disable mode to prevent inadvertent CAN bus errors.

Note: If the CAN module is not connected to the bus or a transceiver, the CAN module will

not enter Normal Operation mode. This is because, the CAN module will always

detect a dominant state at its receive pin.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.6 CAN MESSAGE HANDLING

The CAN module uses device RAM for storing CAN messages that need to be transmitted or

received. The CAN module by itself does not have user-accessible message buffers. Figure 34-8

illustrates the organization of the CAN module buffer memory in device RAM.

Figure 34-8: CAN Message Buffers and Device RAM Organization

As illustrated in , the CAN module organizes message buffers as FIFOs. A total of 32 Figure 34-8

distinct FIFOs are available, which have the following characteristics:

• Minimum size of one CAN message buffer and a maximum size of 32 CAN message

buffers

• Independent configurable size

• Configurable to be a transmit message or a receive message FIFO

• User-readable head and tail pointer

• Independently configurable interrupts

• Status bits to provide the status of the FIFO as messages are transmitted or received

• Can be a transmit FIFO or receive FIFO, but not both (therefore, if a FIFO is configured for

transmit operation, all messages in the FIFO are considered for transmission)

• Can be configured to be a transmit FIFO or receive FIFO, independent of each other and

can be configured in any order

Each of the 32 message FIFOs has the following associated registers:

• CAN FIFO Control register (CiFIFOCONn) (Register 34-20)

• CAN FIFO Interrupt register (CiFIFOINTn) (Register 34-21)

• CAN FIFO User Address register (CiFIFOUAn) (Register 34-22)

• CAN FIFO Message Index register (CiFIFOCIn) (Register 34-23)

The CAN module requires only the start address of the first message buffer in the FIFO. The CAN

FIFO Base Address register (CiFIFOBA) should point to the start address of this message buffer.

The CAN module automatically calculates the address of message buffers in each of the FIFO

based on the configuration of the individual FIFOs. The individual FIFOs will be arranged

contiguously, with all the message buffers being packed. This produces a CAN message buffer

memory without any gaps. While the CiFIFOUAn register provides the address of the next

read/write CAN Message Buffer that the user application must use, the CiFIFOCIn register

provides the corresponding CAN Message Buffer Index of the next message buffer to be

transmitted or written to by the CAN module.

For more information on FIFO related interrupts along with other CAN module interrupts, refer to

34.12 “CAN Interrupts”.

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

Message Buffer 31

Message Buffer 1

Message Buffer 0

CAN

Module

FIFO0 FIFO1 FIFO31

Device RAM

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

For the CAN1 message buffer FIFO configuration illustrated in Figure 34-9, FIFO0 has four

transmit buffers, which would require a total of 16 (4 buffers x 4 words per buffer) words. FIFO1

has two data-only receive buffers, which would require a total of four (2 buffers x 2 words per

buffer) words. FIFO3 has four full receive buffers, which would require a total of 16 (4 buffers x 4

words per buffer) words. Therefore, a total of 36 (16 + 4 + 16) words of memory needs to be

allocated.

Consider another example of a user application illustrated in Figure 34-10, which requires a total

of four FIFOs.

Figure 34-10: Example of CAN FIFO Configuration

FIFO0 and FIFO1 have two message buffers each and are configured to be CAN message

transmit FIFOs. FIFO2 and FIFO3 have three message buffers each and are configured to be

CAN message receive FIFOs. FIFO0 and FIFO1 will require a total of 16 (2 FIFOs x 2 message

buffers per FIFO x 4 words per message buffer) words of memory. FIFO2 and FIFO3 will require

a total of 24 (2 FIFOs x 3 message buffers per FIFO x 4 words per message buffer) words of

memory. Therefore, a total of 40 (16 + 24) words of memory needs to be allocated.

The following steps can be used to configure the CAN module FIFOs:

1. Allocate memory for the CAN message buffer FIFOs.

2. Place the CAN module into Configuration mode (OPMOD<2:0> = 100).

3. Update the CAN FIFO Base Address register (CiFIFOBA) with the base address of the

FIFO. This should be the physical start address of Message Buffer 0 of FIFO0.

4. Update the FSIZE<4:0> bits (CiFIFOCONn<20:16>).

5. Select whether the FIFO is to be a transmit or receive FIFO (TXEN bit

(CiFIFOCONn<7:0>)).

6. Place the CAN module into Normal Operation mode (OPMOD<2:0> = 000).

Example 34-2 illustrates how the above coding steps can be used to configure the CAN message

FIFO as shown in Example 34-10.

FIFO Number Message Buffer

Start Address Message Buffer

FIFO0 0x00002000 MB0

0x00002010 MB1

FIFO1 0x00002020 MB0

0x00002030 MB1

FIFO2

0x00002040 MB0

0x00002050 MB1

0x00002060 MB2

FIFO3

0x00002070 MB0

0x00002080 MB1

0x00002090 MB2

C1FIFOCON0.TXEN = 1

C1FIFOCON0.SIZE = 1

C1FIFOCON1.TXEN = 1

C1FIFOCON1.SIZE = 1

C1FIFOCON2.TXEN = 0

C1FIFOCON2.SIZE = 2

C1FIFOCON3.TXEN = 0

C1FIFOCON3.SIZE = 2

CAN1FIFO Configuration

C1FIFOBA = 0x00002000

PIC32 Family Reference Manual

Example 34-2: Setting Up the CAN Message FIFO

/* This code snippet illustrates the steps required to configure the */

/* PIC32 CAN Message FIFOs. The FIFO configuration example shown in */

/* will be used in this example. */Figure 34-5

/* FIFO0 - Transmit - 2 MESSAGE BUFFERS */

/* FIFO1 - Transmit - 2 MESSAGE BUFFERS */

/* FIF02 - Receive - 3 MESSAGE BUFFERS */

/* FIF03 - Receive - 3 MESSAGE BUFFERS */

/* FIFO4 - FIFO31 - Not used */

/* Allocate a total of 40 words.

unsigned int CanFifoMessageBuffers[40];

/* Request CAN to switch to configuration mode and wait until it has switched */

C1CONbits.REQOP = 100

while(C1CONbits.OPMOD != 100);

/* Initialize C1FIFOBA register with physical address of CAN message Buffer */

C1FIFOBA = KVA_TO_PA(CanFifoMessageBuffers); ;

/* Configure FIFO0 */

C1FIFOCON0bits.FSIZE = 1;

C1FIFOCON0SET = 0x80; /* Set the TXEN bit */

/* Configure FIFO1 */

C1FIFOCON1bits.FSIZE = 1;

C1FIFOCON1SET = 0x80; /* Set the TXEN bit */

/* Configure FIFO2 */

C1FIFOCON2bits.FSIZE = 2;

C1FIFOCON2CLR = 0x80; /* Clear the TXEN bit */

/* Configure FIFO3 */

C1FIFOCON3bits.FSIZE = 2;

C1FIFOCON3CLR = 0x80; /* Clear the TXEN bit */

/* The CAN module can now be placed into normal mode if no further */

/* configuration is required. */

C1CONbits.REQOP = 0;

while(C1CONbits.OPMOD != 0);

PIC32 Family Reference Manual

34.6.3 Accessing Received Messages In the FIFO

To use the FIFO to receive data, the FIFO must be configured as a receive FIFO. This is done

by clearing the TXEN bit (CiFIFOCONn<7>). After a message is received, the user application

should obtain the physical start address of the first message buffer to read (also called the FIFO

tail pointer) from the CiFIFOUAn register. The message can then be read from this address

onward.

After processing the message from the FIFO, the user application should signal the CAN module

that the message has been processed and can be overwritten by setting the UINC bit

(CiFIFOCONn<13>). This will increment the tail pointer and increase the address pointed to by

the CiFIFOUAn register by 4 words or 2 words, depending on the value of the DONLY bit

(CiFIFOCONn<12>). The CiFIFOUAn register rolls over to the start of the FIFO when it has

reached the end of the FIFO.

As a result, the user application need not track the FIFO tail location, and can use the CiFIFOUAn

receive FIFO:

1. Use any of the available interrupts to determine if there is a message in the FIFO.

2. Read the CiFIFOUAn register and process one message (16 bytes) from this address.

3. Set the UINC bit (CiFIFOCONn<13>) to update the CiFIFOUAn register.

4. Perform steps 1 and 2 until the interrupt condition gets cleared.

Example 34-4 illustrates the code using the above steps. In this code example, FIFO1 of the CAN

1 module is configured for receive operation. The code example reads the FIFO until it is empty.

Example 34-4: Reading Received Messages from the FIFO

/* This code snippet illustrates the steps to read messages from receive */

/* message FIFO. This example uses the CAN1 module.*/

/* FIFO1 size is 4 messages and each message is 4 words long. */

unsigned int * currentMessageBuffer; /* Points to message buffer to be read */

while(1)

{

/* Keep reading until the FIFO is empty. */

while(C1FIFOINT1bits.RXNEMPTYIF == 1)

{

/* Get the address of the message buffer to read from the C1FIFOUA1 */

/* register. Convert this physical address to virtual address. */

currentMessageBuffer = PA_TO_KVA1(C1FIF0UA1);

ProcessReceivedMessage(currentMessageBuffer);

/* Set the UINC bit to tell the CAN module that

* a message has been read. */

C1FIFOCON0SET = 0x2000;

}

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.6.4 Resetting the FIFO

The FIFO can be reset by any of the following methods:

• Setting the FIFO Reset (FRESET) bit in the CAN FIFO Control register

(CiFIFOCONn<14>)

• Placing the CAN module into Configuration mode (OPMOD<2:0> bits (CiCON<23:21>) = )100

• Turning the CAN module OFF (CiCON<15> = 0)

Resetting the FIFO will reset the head and tail pointers, the interrupt flags, and the following

status bits in the CAN FIFO Control register (CiFIFOCONn): the Message Aborted (TXABAT) bit

(CiFIFOCONn<6>), the Message Lost Arbitration (TXLARB) bit (CiFIFOCONn<5>) and the Error

Detected During Transmission (TXERR) bit (CiFIFOCONn<4>).

The following should be considered before resetting a FIFO using the FRESET bit

(CiFIFOCONn<14>):

• If the FIFO is a transmit FIFO, no transmissions should be pending

• If the FIFO is a receive FIFO, it should not be pointed to by any active filters

A user application may typically reset the FIFO after coming out of Disable mode. While resetting

the FIFO using the FRESET bit (CiFIFOCONn<14>), the user application must poll the bit to

ensure that the reset operation has completed. This is shown in Example 34-5.

Example 34-5: Resetting a Message FIFO

/* This code snippet shows how to reset a message FIFO. This example */

/* uses FIFO0 of the CAN1 module. */

C1FIFOCON0SET = 0x00004000; /* Set the FRESET bit */

while(C1FIFOCON0bits.FRESET == 1);

PIC32 Family Reference Manual

34.7 TRANSMITTING A CAN MESSAGE

The CAN module will transmit messages that are loaded in a transmit FIFO. For detailed

descriptions on configuring a message FIFO for transmit operation, refer to 34.6.1 “Message

FIFO Configuration” and 34.6.2 “Loading Messages to be Transmitted into the FIFO”.

34.7.1 Format of Transmit Message Buffer

The transmit message FIFO can hold up to 32 CAN transmit message buffers. A transmit

message buffer is 4 words (16 bytes) long and has a fixed format as described in Table 34-2. It

contains four words: CMSGSID, CMSGEID, CMSGDATA0 and CMSGDATA1. The bits in these

registers have a one-to-one correspondence to bit fields in the CAN message, as defined by the

CAN Specification 2.0B. The user application must ensure that every message buffer in the

transmit FIFO conforms to the formats illustrated in Figure 34-11 through Figure 34-14.

Figure 34-11: Format of CMSGSID

Table 34-2: Transmit Message Buffer Format as Stored in System Memory

Name Bit

31/2315/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

CMSGSID 31:24 -— -— -— -— -— -— -— -—

23:16 -— -— -— -— -— -— -— -—

15:8 -— -— -— -— -— SID<10:8>

7:0 SID<7:0>

CMSGEID 31:24 -— -— IDESRR EID<17:14>

23:16 EID<13:6>

15:8 EID<5:0> RTR RB1

7:0 -— -— —-- RB0 DLC<3:0>

CMSGDATA0 31:24 Transmit Buffer Data Byte 3

23:16 Transmit Buffer Data Byte 2

15:8 Transmit Buffer Data Byte 1

7:0 Transmit Buffer Data Byte 0

CMSGDATA1 31:24 Transmit Buffer Data Byte 7

23:16 Transmit Buffer Data Byte 6

15:8 Transmit Buffer Data Byte 5

7:0 Transmit Buffer Data Byte 4

Legend: Shaded bits should be set to ‘0’.

Note: The CAN transmit message is stored in device RAM and has no associated SET/CLR/INV registers.

SID<10:0>

bit 10-0 SID<10:0>: Standard Identifier

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

Figure 34-12: Format of CMSGEID

Figure 34-13: Format of CMSGDATA0

Figure 34-14: Format of CMSGDATA1

— SRR IDE EID<17:0> RTR RB1 — RB0 DLC<3:0>

bit 31-30 Unimplemented: Read as ‘0’

bit 29 SRR: Substitute Remote Request bit

In case of a standard message format (IDE = 0), this bit is don’t care.

In case of an extended message format (IDE = 1), this bit should always be set.

bit 28 IDE: Extended Identifier bit

1 = Message will transmit extended identifier

0 = Message will transmit standard identifier

bit 27-10 EID<17:0>: Extended Identifier bits

bit 9 RTR: Remote Transmission Request bit

1 = Message is a remote transmission request

0 = Message is not a remote transmission request

bit 8 RB1: Reserved bit 1

The user application must set this bit to ‘0’ per the CAN Specification 2.0B.

bit 7-5 Unimplemented: Read as ‘0’

bit 4 RB0: Reserved bit 0

The user application must set this bit to ‘0’ per the CAN Specification 2.0B.

bit 3-0 DLC<3:0>: Data Length Code bits

1xxx = Module will transmit 8 bytes

0111 = 7 bytes of data will be transmitted

•

0001 = 1 byte of data will be transmitted

0000 = 0 bytes of data will be transmitted

Note: This register is in system memory outside the CAN module.

DATA3<7:0> DATA2<7:0> DATA1<7:0> DATA0<7:0>

bit 31-24 DATA3<7:0>: Data Byte 3

bit 23-16 DATA2<7:0>: Data Byte 2

bit 15-8 DATA1<7:0>: Data Byte 1

bit 7-0 DATA0<7:0>: Data Byte 0

Note: This register is in system memory outside the CAN module.

DATA7<7:0> DATA6<7:0> DATA5<7:0> DATA4<7:0>

bit 31-24 DATA7<7:0>: Data Byte 7

bit 23-16 DATA6<7:0>: Data Byte 6

bit 15-8 DATA5<7:0>: Data Byte 5

bit 7-0 DATA4<7:0>: Data Byte 4

Note: This register is in system memory outside the CAN module.

PIC32 Family Reference Manual

Example 34-6 shows a code example data structure for implementing a CAN message buffer in

memory. An example of using this structure is provided in Example 34-7.

Example 34-6: Implementing a CAN Message Buffer in Memory

/* This code snippet shows an example of data structure to implement a CAN */

/* message buffer. */

/* Define the sub-components of the data structure as specified in */Table 34-2

/* Create a CMSGSID data type. */

typedefstruct

{

unsigned SID:11;

unsigned :21;

}txcmsgsid;

/* Create a CMSGEID data type. */

typedef struct

{

unsigned DLC:4;

unsigned RB0:1;

unsigned :3;

unsigned RB1:1;

unsigned RTR:1;

unsigned EID:18;

unsigned IDE:1;

unsigned SRR:1;

unsigned :2;

}txcmsgeid;

/* Create a CMSGDATA0 data type. */

typedef struct

{

unsigned Byte0:8;

unsigned Byte1:8;

unsigned Byte2:8;

unsigned Byte3:8;

}txcmsgdata0;

/* Create a CMSGDATA1 data type. */

typedefstruct

{

unsigned Byte4:8;

unsigned Byte5:8;

unsigned Byte6:8;

unsigned Byte7:8;

}txcmsgdata1;

/* This is the main data structure. */

typedef union uCANTxMessageBuffer {

struct

{

txcmsgsid CMSGSID;

txcmsgeid CMSGEID;

txcmsgdata0 CMSGDATA0;

txcmsgdata0 CMSGDATA1;

};

int messageWord[4];

}CANTxMessageBuffer;

PIC32 Family Reference Manual

The user application should check that the transmit FIFO can accommodate messages (that is,

the transmit FIFO is not full) before writing messages to the FIFO. This can be done by checking

the TxNFULLIF bit in the CAN FIFO Interrupt register (CiFIFOINTn<10>). Writing a message to

a FIFO which is full could cause an untransmitted message to be overwritten.

The following coding steps can be used to transmit CAN messages:

1. Configure the desired number of FIFOs for transmit operation.

2. If desired, set the priority of the individual FIFOs.

3. Create a transmit message using the format shown in Table 34-2.

4. If the TxNFULLIF bit (CiFIFOINTn <10>) is clear, this means the FIFO is full. In this case,

skip to Step 7.

5. Read the CiFIFOUAn register and store the message at the provided address.

6. Set the UINC bit (CiFIFOCONn<13>).

7. Set the TXREQ bit (CiFIFOCONn<3>).

8. Repeat steps 3 through 6 for the number of messages to be transmitted across the

desired number of FIFOs.

9. The transmit FIFO interrupts can be used to monitor the FIFO status.

Example 34-8 shows a code example that provides the steps required to transmit a CAN

message using the CAN1 module to transmit four messages. Message 0 and 1 are Standard

Identifier (SID) CAN messages. Message 2 and 3 are EID messages. FIFO1 is used and its

length is 3.

Example 34-8: Transmitting Standard and Extended ID Messages

/* This code example illustrates how to transmit standard and extended */

/* ID messages with the PIC32 CAN module. */

/* The code example uses CAN1, FIFO0. FIFO0 size is 4 */

/* Four CAN message have to be transmitted. */

/* Msg 0: SID - 0x100 Data - 0x12BC1245 */

/* Msg 1: SID - 0x102 Data - 0x12BC124512BC1245 */

/* Msg 2: SID - 0x100 EID - 0xC000 Data - 0x12BC1245 */

/* Msg 3: SID - 0x102 EID - 0xC000 Data - 0x12BC124512BC1245 */

/* Pointer to CAN Message Buffer */

CANTxMessageBuffer * transmitMessage;

/* This array is the CAN FIFO and message buffers. FIF0 has 4 message */

/* buffers. All other buffers are default size. */

unsigned int CANFIFO[16];

/* Place CAN module in configuration mode */

C1CONbits.REQOP = 4;

while(C1CONbits.OPMOD != 4);

/* Initialize the C1FIFOBA with the start address of the CAN FIFO message */

/* buffer area. */

C1FIFOBA = KVA_TO_PA(CANFIFO);

/* Set FIFO0 size to 3 messages. All other FIFOs at default size. */

/* Configure FIFO0 for transmit.*/

C1FIFOCON0bits.FSIZE = 2

C1FIFOCON0SET = 0x00000080; /* Set the TXEN bit - Transmit FIFO */

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

Example 34-8: Transmitting Standard and Extended ID Messages (Continued)

/* Place the CAN module in Normal mode. */

C1CONbits.REQOP = 0;

while(C1CONbits.OPMOD != 0);

/* Get the address of the message buffer to write to. Load the buffer and */

/* then set the UINC bit. Set the TXREQ bit next to send the message. */

/* Message 0 SID - 0x100 Data - 0x12BC1245*/

transmitMessage = (CANTxMessageBuffer *)(PA_TO_KVA1(C1FIFOUA1));

transmitMessage->CMSGSID.SID = 0x100; /* CMSGSID */

transmitMessage->CMSGEID.IDE = 0;

transmitMessage->CMSGEID.DLC = 0x4;

transmitMessage->messageWord[2] = 0x12BC1245; /* CMSGDAT0 */

C1FIFOCON1SET = 0x00002000; /* Set the UINC bit */

C1FIFOCON1SET = 0x00000008; /* Set the TXREQ bit */

/* Message 1 SID - 0x102 Data - 0x12BC124512BC1245 */

transmitMessage = (CANTxMessageBuffer *)(PA_TO_KVA1(C1FIFOUA1));

transmitMessage->CMSGSID.SID = 0x102; /* CMSGSID */

transmitMessage->CMSGEID.IDE = 0;

transmitMessage->CMSGEID.DLC = 0x8;

transmitMessage->messageWord[2] = 0x12BC1245; /* CMSGDAT0 */

transmitMessage->messageWord[3] = 0x12BC1245; /* CMSGDAT1 */

C1FIFOCON1SET = 0x00002000; /* Set the UINC bit */

C1FIFOCON1SET = 0x00000008; /* Set the TXREQ bit */

/* Message 2 SID - 0x100 EID - 0xC000 Data - 0x12BC1245*/

transmitMessage = (CANTxMessageBuffer *)(PA_TO_KVA1(C1FIFOUA1));

transmitMessage->CMSGSID.SID = 0x100; /* CMSGSID */

transmitMessage->CMSGEID.SID = 0xC000; /* CMSGEID */

transmitMessage->CMSGEID.IDE = 1;

transmitMessage->CMSGEID.DLC = 0x4;

transmitMessage->messageWord[2] = 0x12BC1245; /* CMSGDAT0 */

C1FIFOCON1SET = 0x00002000; /* Set the UINC bit */

C1FIFOCON1SET = 0x00000008; /* Set the TXREQ bit */

/* Message 3 SID - 0x102 EID - 0xC000 Data - 0x12BC124512BC1245*/

transmitMessage = (CANTxMessageBuffer *)(PA_TO_KVA1(C1FIFOUA1));

transmitMessage->CMSGSID.SID = 0x102; /* CMSGSID */

transmitMessage->CMSGEID.SID = 0xC000; /* CMSGEID */

transmitMessage->CMSGEID.IDE = 1;

transmitMessage->CMSGEID.DLC = 0x8;

transmitMessage->messageWord[2] = 0x12BC1245; /* CMSGDAT0 */

transmitMessage->messageWord[3] = 0x12BC1245; /* CMSGDAT1 */

C1FIFOCON1SET = 0x00002000; /* Set the UINC bit */

C1FIFOCON1SET = 0x00000008; /* Set the TXREQ bit */

}

PIC32 Family Reference Manual

34.7.3 Transmit Message Priority

The CAN module allows the user application to control the priority of transmit message buffers.

Prior to sending a message SOF, the CAN module compares the priority of all buffers that are

ready for transmission. The transmit message buffer with the highest priority will be sent first. For

example, if transmit FIFO0 has a higher priority setting than transmit FIFO1, all messages in

FIFO0 will be sent first. In a case where the priority of a FIFO is changed while another FIFO is

being processed, the CAN module will reassess the priority of all FIFOs after it has completed

transmitting the current message. This allows the change in FIFO priority to take effect at the

earliest opportunity.

The priority levels are controlled by the Message Transmit Priority (TXPR<1:0>) bits in the CAN

FIFO Control register (CiFIFOCONn<1:0>). There are four levels of transmit priority as defined

by the (TXPR<1:0>) bits (CiFIFOCONn<1:0>). The selections are as follows:

•11 = This FIFO has the highest priority

•10 = This FIFO has an intermediate high priority

•01 = This FIFO has an intermediate low priority

•00 = This FIFO has the lowest priority

If two FIFOs have the same priority setting, the FIFO with the highest natural order is sent. The

natural order of transmission if all FIFOs have the same priority is as follows:

• FIFO0 = lowest natural priority

• FIFO1 = higher natural priority

•

• FIFO31 = highest natural priority

34.7.4 Aborting Transmission of a Queued Message

A message that has been queued to be transmitted can be aborted by clearing the TXREQ bit

(CiFIFOCONn<3>). If the TXREQ bit (CiFIFOCONn<3>) is cleared, the CAN module will attempt

to abort the transmission.

If the message aborts successfully, the TXABAT bit (CiFIFOCONn<6>) will be set by hardware.

TXREQ will remain set until the message either aborts or is successfully transmitted.

If the message is successfully transmitted, the FIFO pointers will be updated as normal. If the

message is successfully aborted, the FIFO pointers will not change. The user can then use the

internal index (CFIFOCI) to determine which messages have already been transmitted if

required.

To reset the FIFO pointers and erase all pending messages, the user application can set the

FRESET bit (CiFIFOCONn<14>). The FIFO can then be re-enabled and loaded with new

messages to be transmitted.

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.7.5 Remote Transmit Request

As discussed in 34.7.2 “Requesting Transmit of a Message”, the CAN bus system has a

method for allowing a node to request data from another node. The requesting node sends a

message with the RTR bit set. The message contains no data, only an address to trigger a filter

match.

The filter that is configured to respond to an RTR will point to a FIFO that is configured for

transmission. The FIFO must also be enabled to reply to the remote transmission requests by

setting the RTREN = 1.

RTRs can be handled without CPU intervention. If a transmit FIFO is configured correctly, when

a filter matches and that filter points to the FIFO, the buffer will be queued for transmission. The

FIFO must be configured as follows:

1. Set FIFO to Transmit mode by setting the TXEN bit (CiFIFOCONn<7>) to ‘1’.

2. A filter must be enabled and loaded with a matching message identifier.

3. The buffer pointer register for that filter must point to the transmit buffer (note that although

a filter normally points to a receive FIFO, in this case it must point to the transmit FIFO).

4. The RTREN bit (CiFIFOCONn<2>) must be set to ‘1’ to enable RTR.

5. The FIFO must be preloaded with at least one message to be sent.

When a RTR message is received, and it matches a filter pointing to the properly configured

transmit buffer, the TXREQ bit (CiFIFOCONn<3>) is automatically set. The message buffers in

the FIFO are then transmitted in priority order. If no messages are available in the transmit buffer

when a request for a remote transmission occurs, the event will be treated as a FIFO overflow,

and the Receive FIFO Overflow Interrupt Flag (RXOVFLIF) bit in the CAN FIFO Interrupt register

(CiFIFOINTn<3>) will be set. Example 34-9 shows a code example of how a node can request

data from remote node. Example 34-10 shows a code example of how a node can be configured

to respond to a RTR.

Example 34-9: Remote Transmit Request

/* This code snippet shows an example of a Remote Transmit Request. The */

/* node in this case will request a transmission from an application (or */

/* node) with an SID of 0x100. */

CANMessageBuffer * rtrMessage;

rtrMessage = (CANMessageBuffer *)(PA_TO_KVA1(C1FIFOUA1));

/* Clear the message. */

rtrMessage->messageWord[0] = 0x0;

rtrMessage->messageWord[1] = 0x0;

rtrMessage->messageWord[2] = 0x0;

rtrMessage->messageWord[3] = 0x0;

rtrMessage->CMSGSID.SID = 0x100;

rtrMessage->CMSGEID.IDE = 0;

rtrMessage->CMSGEID.RTR = 1;

rtrMessage->CMSGEID.DLC = 0;

C1FIFOCON1SET = 0x00002000; /* Set the UINC bit */

/* The Remote Transmit Request message (rtrMessage) is now ready to be sent.*/

Section 34. Controller Area Network (CAN)

Controller Area

Network (CAN)

34.7.6 Example Message Transmission FIFO Behavior

Consider an example user applicat FO0 and FIFO1, of the CAN1 ion that uses two FIFOs, FI

module. FIFO0 has four message buffers configured for CAN message reception. FIFO1 has

seven message buffers and is configured for message transmission. FIFO2 through FIFO31 are

left in a default state. The CAN message buffer starts at physical address 0x00000100. This

value is loaded in the C1FIFOBA register. Figure 34-16 shows this application configuration.

Figure 34-16: FIFO Configuration for Example FIFO Behavior

The start address of FIFO1 can be calculated from the base address of the CAN message buffer

(0x00000100) and the byte size of FIFO0 (4 message buffers * 16 = 0x40). The physical start

address of FIFO1 is 0x00000140. The below section focuses on the transmit FIFO1.

Figure 34-17 illustrates the case where FIFO1 of CAN1 module is empty and no messages have

been written. The FIFO Transmit Not Full Interrupt Flag (TXNFULLIF), FIFO Transmit Half Empty

interrupt flag (TXHALFIF) and the FIFO Transmit Empty Interrupt Flag (TXEMPTYIF) are set.

Figure 34-17: FIFO1 at Start

FIFO Number Message Buffer

Start Address Message Buffer

FIFO0

(Full Receive Mes-

sage)

0x00000100 MB0

0x00000110 MB1

0x00000120 MB2

0x00000130 MB3

FIFO1

(Transmit FIFO)

0x00000140 MB0

0x00000150 MB1

0x00000160 MB2

0x00000170 MB3

0x00000180 MB4

0x00000190 MB5

0x000001A0 MB6

FIFO2 0x000001B0 MB0

FIFO4 0x000001C0 MB0

•

FIFO31 0x00000380 MB0

C1FIFOCON0.TXEN = 1

C1FIFOCON0.FSIZE = 3

C1FIFOCON1.TXEN = 1

C1FIFOCON1.SIZE = 6

FIFO2 - FIFO31 are not configured

CAN1FIFO Configuration

C1FIFOBA = 0x00000100

MB2

MB1

MB0

MB6

MB5

MB4

MB3

C1FIFOBA = 0x00000100

C1FIFOUA1 = 0x00000140

TXNFULLIF - 1

TXHALFIF - 1

TXEMPTYIF - 1

TXREQ - 0

C1FIFOCI1 = 0x00000000

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	PIC32MX564F064L

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