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USB On-The-Go

(OTG)

Section 27. USB On-The-Go (OTG)

HIGHLIGHTS

This section of the manual contains the following major topics:

27.1 Introduction .................................................................................................................. 27-2

27.2 Control Registers ......................................................................................................... 27-4

27.3 Operation ................................................................................................................... 27-36

27.4 Host Mode Operation................................................................................................. 27-51

27.5 Interrupts.................................................................................................................... 27-59

27.6 I/O Pins ...................................................................................................................... 27-62

27.7 Operation in Debug and Power-Saving Modes.......................................................... 27-64

27.8 Effects of a Reset....................................................................................................... 27-66

27.9 Related Application Notes.......................................................................................... 27-67

PIC32 Family Reference Manual

27.1 INTRODUCTION

The PIC32 USB OTG module includes the following features:

• USB Full-Speed Support for Host and Device

• Low-Speed Host Support

• USB On-The-Go (OTG) Support

• Integrated Signaling Resistors

• Integrated Analog Comparators for VBUS Monitoring

• Integrated USB Transceiver

• Transaction Handshaking Performed by Hardware

• Endpoint Buffering Anywhere in System RAM

• Integrated Bus Master to Access System RAM and Flash

• USB OTG module does not require the PIC32 DMA module for its operation

The USB OTG module contains analog and digital components to provide a USB 2.0 full-speed

and low-speed embedded host, full-speed device, or OTG implementation with a minimum of

external components. This module in Host mode is intended for use as an embedded host and

therefore does not implement a UHCI or OHCI controller.

The USB OTG module consists of the clock generator, the USB voltage comparators, the trans-

ceiver, the Serial Interface Engine (SIE), a dedicated USB Bus Master, pull-up and pull-down

resistors and the register interface. A block diagram of the USB OTG module is presented in

Figure 27-1.

The clock generator provides the 48 MHz clock, which is required for USB full-speed and

low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to

determine the state of the bus. The transceiver provides the analog translation between the USB

bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint

buffers, and generates the hardware protocol for data transfers. The USB Bus Master transfers

data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors

eliminate the need for external signaling components. The register interface allows the CPU to

configure and communicate with the module.

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “USB On-The-Go (OTG)” chapter

in the current device data sheet to check whether this document supports the device

you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

IMPORTANT: The implementation and use of the USB specifications, as well as other

third-party specifications or technologies, may require licensing; including,

but not limited to, USB Implementers Forum, Inc. (also referred to as

USB-IF). The user is fully responsible for investigating and satisfying any

applicable licensing obligations.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

Figure 27-1: PIC32 USB OTG Interface Diagram

Note 1: PB clock is only available on this pin for select EC modes.

2: Pins can be used as digital inputs when USB is not enabled.

3: This bit field is contained in the OSCCON register.

4: This bit field is contained in the OSCTRM register.

5: USB PLL UFIN requirements: 4 MHz ≤ UFIN ≤ 5 MHz.

6: This bit field is contained in the DEVCFG2 register.

7: A 48 MHz clock is required for proper USB operation.

8: Pins can be used as GPIO when the USB OTG module is disabled.

9: Pin is pulled high internally when USB OTG module is enabled.

OSC1

OSC2

Primary Oscillator

8 MHz Typical

FRC

Oscillator

TUN<5:0>(4)

PLL

48 MHz USB Clock(7)

Div x

UPLLEN(6)

(PBOUT)(1)

UFRCEN(3)

(POSC)

FUPLLIDIV(6)

UFIN(5)

Div 2

VUSB

D+(2)

D-(2)

ID(8,9)

VBUS

Transceiver

SIE

VBUSON(8)

Comparators

USB

SRP Charge

SRP Discharge

Registers

and

Control

Interface

Transceiver Power 3.3V

To Clock Generator for Core and Peripherals

Sleep or Idle

Sleep

USBEN

USB Suspend

CPU Clock Not POSC

USB OTG Module

Voltage

System

RAM

USB Suspend

Full-Speed Pull-up

Host Pull-down

Low-Speed Pull-up

Host Pull-down

ID Pull-up

Bus

Master

24xPLL

PIC32 Family Reference Manual

27.2 CONTROL REGISTERS

The USB OTG module includes the following Special Function Registers (SFRs):

•U1OTGIR: USB OTG Interrupt Status Register

This register records changes on the ID, data and VBUS pins, enabling software to determine

which event caused an interrupt. The interrupt bits are cleared by writing a ‘1’ to the corresponding

interrupt.

•U1OTGIE: USB OTG Interrupt Enable Register

This register enables the corresponding interrupt status bits defined in the U1OTGIR register

to generate an interrupt.

•U1OTGSTAT: USB OTG Status Register

This register provides access to the status of the VBUS voltage comparators and the

debounced status of the ID pin.

•U1OTGCON: USB OTG Control Register

This register controls the operation of the VBUS pin, and the pull-up and pull-down resistors.

•U1PWRC: USB Power Control Register

This register controls the power-saving modes, as well as the module enable/disable

control.

•U1IR: USB Interrupt Register

This register contains information on pending interrupts. Once an interrupt bit is set, it can

be cleared by writing a ‘1’ to the corresponding bit.

•U1IE: USB Interrupt Enable Register(1)

The values in this register provide gating of the various interrupt signals onto the USB inter-

rupt signal. These values do not interact with the USB OTG module. Setting any of these

bits enables the corresponding interrupt source in the U1IR register.

•U1EIR: USB Error Interrupt Status Register

This register contains information on pending error interrupt values. Once an interrupt bit is

set, it can be cleared by writing a ‘1’ to the corresponding bit.

•U1EIE: USB Error Interrupt Enable Register(1)

The values in this register provide gating of the various interrupt signals onto the USB

interrupt signal. These values do not interact with the USB OTG module. Setting any of

these bits enables the respective interrupt source in the U1EIR register, if the UERRIE bit

(U1IE<1>) is also set.

•U1STAT: USB Status Register(1)

U1STAT is a 16-deep First In, First Out register (FIFO). It is read-only by the CPU and

read/write by the USB OTG module. U1STAT is only valid when the TRNIF bit (U1IR<3>) is

set.

•U1CON: USB Control Register

This register provides miscellaneous control and information about the module.

•U1ADDR: USB Address Register

U1ADDR is a read/write register from the CPU side and read-only from the USB OTG mod-

ule side. Although the register values affect the settings of the USB OTG module, the

content of the registers does not change during access.

In Device mode, this address defines the USB device address as assigned by the host dur-

ing the SETUP phase. The firmware writes the address in response to the SETUP request.

The address is automatically reset when a USB bus Reset is detected. In Host mode, the

module transmits the address provided in this register with the corresponding token packet.

This allows the USB OTG module to uniquely address the connected device.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

•U1FRML: USB Frame Number Low Register and U1FRMH: USB Frame Number High

U1FRML and U1FRMH are read-only registers. The frame number is formed by concatenat-

ing the two 8-bit registers. The high-order byte is in the U1FRMH register, and the low-order

byte is in U1FRML.

•U1TOK: USB Token Register

U1TOK is a read/write register required when the module operates as a host. It is used to

specify the token type, PID<3:0> (Packet ID), and the endpoint, EP<3:0>, being addressed

by the host processor. Writing to this register triggers a host transaction.

•U1SOF: USB SOF Threshold Register

U1SOF is a read/write register that contains the count bits of the Start of Frame (SOF)

threshold value, and are used in Host mode only.

To prevent colliding a packet data with the SOF token that is sent every 1 ms, the USB OTG

module will not send any new transactions within the last U1SOF byte times. The USB OTG

module will complete any transactions that are in progress. In Host mode, the SOF interrupt

occurs when this threshold is reached, not when the SOF occurs. In Device mode, the inter-

rupt occurs when a SOF is received. Transactions started within the SOF threshold are held

by the USB OTG module until after the SOF token is sent.

•U1BDTP1: USB BDT Register, U1BDTP2: USB BDT PAGE 2 Register, and U1BDTP3:

USB BDT PAGE 3 Register

These registers are read/write registers that define the upper 23 bits of the 32-bit base

address of the Buffer Descriptor Table (BDT) in the system memory. The BDT is forced to

be 512 byte-aligned. This register allows relocation of the BDT in real time.

•U1CNFG1: USB Configuration 1 Register

U1CNFG1 is a read/write register that controls the Debug and Idle behavior of the module.

The register must be preprogrammed prior to enabling the module.

•U1EP0-U1EP15: USB Endpoint Control Registers

These registers control the behavior of the corresponding endpoint.

27.2.1 Associated Registers

Refer to Section 6. “Oscillators” (DS61112) for information on the register bits used to enable

the USB PLL and/or USB FRC clock sources.

Refer to Section 8. “Interrupts” (DS61108) for information on the register bits used to enable

and identify the USB OTG module interrupts.

Refer to Section 32. “Configuration” (DS61124) for information on the configuration bits used

to enable the USB PLL and set the appropriate divisor. This section also describes the bits that

can be used to reclaim the USBID and VBUSON pins if the USB OTG module will only be operated

in a mode that does not require them.

27.2.2 Clearing USB OTG Interrupts

Unlike other device-level interrupts, the USB OTG interrupt status flags are not freely writable in

software. All USB OTG flag bits are implemented as hardware-set-only bits. These bits can only

be cleared in software by writing a ‘1’ to their locations. Writing a ‘0’ to a flag bit has no effect.

Note: Throughout this section, a bit that can only be cleared by writing a ‘1’ to its location

is referred to as “Write ‘ ’ to clear bit”. In register 1descriptions, this function is

indicated by the descriptor ‘K’.

PIC32 Family Reference Manual

27.2.3 Register Summary

All USB OTG registers are summarized in Table 27-1.

Table 27-1: USB OTG Register Summary(1)

Name

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

U1OTGIR 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

U1OTGIE 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

U1OTGSTAT 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 ID — LSTATE — SESVD SESEND — VBUSVD

U1OTGCON 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

U1PWRC 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 UACTPND — — USLPGRD USBBUSY(2) — USUS-

PEND

USBPWR

U1IR 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF

DETACHIF

U1IE 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE

DETACHIE

U1EIR 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF

EOFEF

U1EIE 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE

EOFEE

U1STAT 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 ENDPT<3:0> DIR PPBI — —

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.

2: This bit is not available on all devices. Refer to the specific device data sheet for details.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U1CON 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN

TOKBUSY SOFEN

U1ADDR 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 LSPDEN DEVADDR<6:0>

U1BDTP1 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 BDTPTRL<15:9> —

U1FRML 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 FRML<7:0>

U1FRMH 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — — — FRMH<2:0>

U1TOK 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 PID<3:0> EP<3:0>

U1SOF 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 CNT<7:0>

U1BDTP2 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 BDTPTRH<23:16>

U1BDTP3 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 BDTPTRU<31:24>

U1CNFG1 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 UTEYE UOEMON USBFRZ USBSIDL — — — UASUSPND(2)

U1EP0 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP1 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Table 27-1: USB OTG Register Summary(1) (Continued)

Name

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.

2: This bit is not available on all devices. Refer to the specific device data sheet for details.

PIC32 Family Reference Manual

U1EP2 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP3 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP4 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP5 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP6 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP7 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP8 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP9 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP10 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP11 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP12 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP13 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Table 27-1: USB OTG Register Summary(1) (Continued)

Name

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.

2: This bit is not available on all devices. Refer to the specific device data sheet for details.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U1EP14 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

U1EP15 31:24 — — — — — — — —

23:16 — — — — — — — —

15:8 — — — — — — — —

7:0 — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Table 27-1: USB OTG Register Summary(1) (Continued)

Name

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

Legend: — = unimplemented, read as ‘0’. Address offset values are shown in hexadecimal.

Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.

2: This bit is not available on all devices. Refer to the specific device data sheet for details.

PIC32 Family Reference Manual

27.2.4 Register Definitions

This section provides a detailed description of each USB OTG register.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 U-0 R/K-0

IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (‘0’, ‘1’, x = unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIF: ID State Change Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Change in ID state detected

0 = No change in ID state detected

bit 6 T1MSECIF: 1 Millisecond Timer bit

Write a ‘1’ to this bit to clear the interrupt.

1 = 1 millisecond timer has expired

0 = 1 millisecond timer has not expired

bit 5 LSTATEIF: Line State Stable Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = USB line state has been stable for 1 ms, but different from last time

0 = USB line state has not been stable for 1 ms

bit 4 ACTVIF: Bus Activity Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up

0 = Activity has not been detected

bit 3 SESVDIF: Session Valid Change Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = VBUS voltage has dropped below the session end level

0 = VBUS voltage has not dropped below the session end level

bit 2 SESENDIF: B-Device VBUS Change Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = A change on the session end input was detected

0 = No change on the session end input was detected

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Change on the session valid input detected

0 = No change on the session valid input detected

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIE: ID Interrupt Enable bit

1 = ID interrupt enabled

0 = ID interrupt disabled

bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit

1 = 1 millisecond timer interrupt enabled

0 = 1 millisecond timer interrupt disabled

bit 5 LSTATEIE: Line State Interrupt Enable bit

1 = Line state interrupt enabled

0 = Line state interrupt disabled

bit 4 ACTVIE: Bus Activity Interrupt Enable bit

1 = ACTIVITY interrupt enabled

0 = ACTIVITY interrupt disabled

bit 3 SESVDIE: Session Valid Interrupt Enable bit

1 = Session valid interrupt enabled

0 = Session valid interrupt disabled

bit 2 SESENDIE: B-Session End Interrupt Enable bit

1 = B-session end interrupt enabled

0 = B-session end interrupt disabled

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit

1 = A-VBUS valid interrupt enabled

0 = A-VBUS valid interrupt disabled

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0

ID — LSTATE — SESVD SESEND — VBUSVD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 ID: ID Pin State Indicator bit

1 = No cable is attached or a type B cable has been plugged into the USB receptacle

0 = A “type A” OTG cable has been plugged into the USB receptacle

bit 6 Unimplemented: Read as ‘0’

bit 5 LSTATE: Line State Stable Indicator bit

1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms

0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms

bit 4 Unimplemented: Read as ‘0’

bit 3 SESVD: Session Valid Indicator bit

1 = VBUS voltage is above Session Valid on the A or B device

0 = VBUS voltage is below Session Valid on the A or B device

bit 2 SESEND: B-Session End Indicator bit

1 = VBUS voltage is below Session Valid on the B device

0 = VBUS voltage is above Session Valid on the B device

bit 1 Unimplemented: Read as ‘0’

bit 0 VBUSVD: A-VBUS Valid Indicator bit

1 = VBUS voltage is above Session Valid on the A device

0 = VBUS voltage is below Session Valid on the A device

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 DPPULUP: D+ Pull-Up Enable bit

1 = D+ data line pull-up resistor is enabled

0 = D+ data line pull-up resistor is disabled

bit 6 DMPULUP: D- Pull-Up Enable bit

1 = D- data line pull-up resistor is enabled

0 = D- data line pull-up resistor is disabled

bit 5 DPPULDWN: D+ Pull-Down Enable bit

1 = D+ data line pull-down resistor is enabled

0 = D+ data line pull-down resistor is disabled

bit 4 DMPULDWN: D- Pull-Down Enable bit

1 = D- data line pull-down resistor is enabled

0 = D- data line pull-down resistor is disabled

bit 3 VBUSON: VBUS Power-on bit

1 = VBUS line is powered

0 = VBUS line is not powered

bit 2 OTGEN: OTG Functionality Enable bit

1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control

0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control

bit 1 VBUSCHG: VBUS Charge Enable bit

1 = VBUS line is charged through a pull-up resistor

0 = VBUS line is not charged through a resistor

bit 0 VBUSDIS: VBUS Discharge Enable bit

1 = VBUS line is discharged through a pull-down resistor

0 = VBUS line is not discharged through a resistor

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

HS, HC-x U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

UACTPND — — USLPGRD USBBUSY(1) — USUSPEND USBPWR

bit 7 bit 0

Legend:

HC = Cleared by hardware HS = Set by hardware

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UACTPND: USB Activity Pending bit

1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet

0 = An interrupt is not pending

bit 6-5 Unimplemented: Read as ‘0’

bit 4 USLPGRD: USB Sleep Entry Guard bit

1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending

0 = USB OTG module does not block Sleep entry

bit 3 USBBUSY: USB OTG module Busy bit(1)

1 = USB OTG module is active or disabled, but not ready to be enabled

0 = USB OTG module is not active and is ready to be enabled

Note : When USBPWR = 0 1 and USBBUSY = , status from all other registers is invalid and writes

to all USB OTG module registers produce undefined results.

bit 2 Unimplemented: Read as ‘0’

bit 1 USUSPEND: USB Suspend Mode bit

1 = USB OTG module is placed in Suspend mode

(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)

0 = USB OTG module operates normally

bit 0 USBPWR: USB Operation Enable bit

1 = USB OTG module is turned on

0 = USB OTG module is disabled

(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce

power consumption.)

Note 1: This bit is not available on all devices. Refer to the specific device data sheet for details.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0

STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) URSTIF(5)

DETACHIF(6)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIF: STALL Handshake Interrupt bit

Write a ‘1’ to this bit to clear the interrupt.

1 = In Host mode a STALL handshake was received during the handshake phase of the transaction

In Device mode a STALL handshake was transmitted during the handshake phase of the transaction.

0 = STALL handshake has not been sent

bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)

Write a ‘1’ to this bit to clear the interrupt.

1 = Peripheral attachment was detected by the USB OTG module

0 = Peripheral attachment was not detected

bit 5 RESUMEIF: Resume Interrupt bit

(2)

Write a ‘1’ to this bit to clear the interrupt.

1 = K-State is observed on the D+ or D- pin for 2.5 µs

0 = K-State is not observed

bit 4 IDLEIF: Idle Detect Interrupt bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Idle condition detected (constant Idle state of 3 ms or more)

0 = No Idle condition detected

Note 1: This bit is valid only if the HOSTEN bit is set (see Register 27-11), there is no activity on the USB for

2.5 µs, and the current bus state is not SE0.

2: When not in Suspend mode, this interrupt should be disabled.

3: Clearing this bit will cause the STAT FIFO to advance.

4: Only error conditions enabled through the U1EIE register will set this bit.

5: Device mode.

6: Host mode.

PIC32 Family Reference Manual

bit 3 TRNIF: Token Processing Complete Interrupt bit(3)

Write a ‘1’ to this bit to clear the interrupt.

1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint

information

0 = Processing of current token not complete

bit 2 SOFIF: SOF Token Interrupt bit

Write a ‘1’ to this bit to clear the interrupt.

1 = SOF token received by the peripheral or the SOF threshold reached by the host

0 = SOF token was not received nor threshold reached

bit 1 UERRIF: USB Error Condition Interrupt bit(4)

Write a ‘1’ to this bit to clear the interrupt.

1 = Unmasked error condition has occurred

0 = Unmasked error condition has not occurred

bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5)

1 = Valid USB Reset has occurred

0 = No USB Reset has occurred

DETACHIF: USB Detach Interrupt bit (Host mode)(6)

1 = Peripheral detachment was detected by the USB OTG module

0 = Peripheral detachment was not detected

Note 1: This bit is valid only if the HOSTEN bit is set (see Register 27-11), there is no activity on the USB for

2.5 µs, and the current bus state is not SE0.

2: When not in Suspend mode, this interrupt should be disabled.

3: Clearing this bit will cause the STAT FIFO to advance.

4: Only error conditions enabled through the U1EIE register will set this bit.

5: Device mode.

6: Host mode.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE(2)

DETACHIE(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIE: STALL Handshake Interrupt Enable bit

1 = STALL interrupt enabled

0 = STALL interrupt disabled

bit 6 ATTACHIE: ATTACH Interrupt Enable bit

1 = ATTACH interrupt enabled

0 = ATTACH interrupt disabled

bit 5 RESUMEIE: RESUME Interrupt Enable bit

1 = RESUME interrupt enabled

0 = RESUME interrupt disabled

bit 4 IDLEIE: Idle Detect Interrupt Enable bit

1 = Idle interrupt enabled

0 = Idle interrupt disabled

bit 3 TRNIE: Token Processing Complete Interrupt Enable bit

1 = TRNIF interrupt enabled

0 = TRNIF interrupt disabled

bit 2 SOFIE: SOF Token Interrupt Enable bit

1 = SOFIF interrupt enabled

0 = SOFIF interrupt disabled

bit 1 UERRIE: USB Error Interrupt Enable bit

1 = USB Error interrupt enabled

0 = USB Error interrupt disabled

Note 1: For an interrupt to propagate to the USBIF bit (IFS1<25>), the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

PIC32 Family Reference Manual

bit 0 URSTIE: USB Reset Interrupt Enable bit(2)

1 = URSTIF interrupt enabled

0 = URSTIF interrupt disabled

DETACHIE: USB Detach Interrupt Enable bit(3)

1 = DATTCHIF interrupt enabled

0 = DATTCHIF interrupt disabled

(1) (Continued)

Note 1: For an interrupt to propagate to the USBIF bit (IFS1<25>), the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0

BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF CRC5EF(3,4)

PIDEF

EOFEF(5)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (‘0’, ‘1’, x = unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEF: Bit Stuff Error Flag bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Packet rejected due to bit stuff error

0 = Packet accepted

bit 6 BMXEF: Bus Matrix Error Flag bit

Write a ‘1’ to this bit to clear the interrupt.

1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry,

is invalid.

0 = No address error

bit 5 DMAEF: DMA Error Flag bit(1)

Write a ‘1’ to this bit to clear the interrupt.

1 = USB DMA error condition detected

0 = No DMA error

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

PIC32 Family Reference Manual

bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2)

Write a ‘1’ to this bit to clear the interrupt.

1 = Bus turnaround time-out has occurred

0 = No bus turnaround time-out

bit 3 DFN8EF: Data Field Size Error Flag bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Data field received is not an integral number of bytes

0 = Data field received is an integral number of bytes

bit 2 CRC16EF: CRC16 Failure Flag bit

Write a ‘1’ to this bit to clear the interrupt.

1 = Data packet rejected due to CRC16 error

0 = Data packet accepted

bit 1 CRC5EF: CRC5 Host Error Flag bit(3,4)

Write a ‘1’ to this bit to clear the interrupt.

1 = Token packet rejected due to CRC5 error

0 = Token packet accepted

EOFEF: EOF Error Flag bit(5)

1 = EOF error condition detected

0 = No EOF error condition

bit 0 PIDEF: PID Check Failure Flag bit

1 = PID check failed

0 = PID check passed

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the

module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer

size is not sufficient to store the received data packet causing it to be truncated.

2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)

has elapsed.

3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has

reached zero.

4: Device mode.

5: Host mode.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(2)

PIDEE

EOFEE(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = BTSEF interrupt enabled

0 = BTSEF interrupt disabled

bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit

1 = BMXEF interrupt enabled

0 = BMXEF interrupt disabled

bit 5 DMAEE: DMA Error Interrupt Enable bit

1 = DMAEF interrupt enabled

0 = DMAEF interrupt disabled

bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1 = BTOEF interrupt enabled

0 = BTOEF interrupt disabled

bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit

1 = DFN8EF interrupt enabled

0 = DFN8EF interrupt disabled

bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit

1 = CRC16EF interrupt enabled

0 = CRC16EF interrupt disabled

Note 1: For an interrupt to propagate USBIF bit (IFS1<25>), the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

PIC32 Family Reference Manual

bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(2)

1 = CRC5EF interrupt enabled

0 = CRC5EF interrupt disabled

EOFEE: EOF Error Interrupt Enable bit(3)

1 = EOF interrupt enabled

0 = EOF interrupt disabled

bit 0 PIDEE: PID Check Failure Interrupt Enable bit

1 = PIDEF interrupt enabled

0 = PIDEF interrupt disabled

Note 1: For an interrupt to propagate USBIF bit (IFS1<25>), the UERRIE bit (U1IE<1>) must be set.

2: Device mode.

3: Host mode.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R-x R-x R-x R-x R-x R-x U-0 U-0

ENDPT<3:0> DIR PPBI — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits

(Represents the number of the BDT, updated by the last USB transfer.)

1111 = Endpoint 15

1110 = Endpoint 14

•

0001 = Endpoint 1

0000 = Endpoint 0

bit 3 DIR: Last BD Direction Indicator bit

1 = Last transaction was a transmit transfer (TX)

0 = Last transaction was a receive transfer (RX)

bit 2 PPBI: Ping-Pong BD Pointer Indicator bit

1 = The last transaction was to the ODD BD bank

0 = The last transaction was to the EVEN BD bank

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The U1STAT register is a window into a 4 byte FIFO maintained by the USB OTG module. U1STAT value

is only valid when the TRNIF bit (U1IR<3>) is active. Clearing the TRNIF bit (U1IR<3>) advances the

FIFO. Data in register is invalid when the TRNIF bit (U1IR<3>) = 0.

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

JSTATE SE0 PKTDIS(4)

USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4)

TOKBUSY(1,5) SOFEN(5)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 JSTATE: Live Differential Receiver JSTATE flag bit

1 = JSTATE detected on the USB

0 = No JSTATE detected

bit 6 SE0: Live Single-Ended Zero flag bit

1 = Single Ended Zero detected on the USB

0 = No Single Ended Zero detected

bit 5 PKTDIS: Packet Transfer Disable bit(4)

1 = Token and packet processing disabled (set upon SETUP token received)

0 = Token and packet processing enabled

TOKBUSY: Token Busy Indicator bit(1,5)

1 = Token being executed by the USB OTG module

0 = No token being executed

bit 4 USBRST: Module Reset bit(5)

1 = USB reset generated

0 = USB reset terminated

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register, see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then

clear it to enable remote wake-up. In Host mode, the USB OTG module will append a low-speed EOP to

the RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

bit 3 HOSTEN: Host Mode Enable bit(2)

1 = USB host capability enabled

0 = USB host capability disabled

bit 2 RESUME: RESUME Signaling Enable bit(3)

1 = RESUME signaling activated

0 = RESUME signaling disabled

bit 1 PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Even/Odd buffer pointers to the EVEN BD banks

0 = Even/Odd buffer pointers not being Reset

bit 0 USBEN: USB OTG Module Enable bit(4)

1 = USB OTG module and supporting circuitry enabled

0 = USB OTG module and supporting circuitry disabled

SOFEN: SOF Enable bit(5)

1 = SOF token sent every 1 ms

0 = SOF token disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register, see

2: All host control logic is reset any time that the value of this bit is toggled.

3: Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then

clear it to enable remote wake-up. In Host mode, the USB OTG module will append a low-speed EOP to

the RESUME signaling when this bit is cleared.

4: Device mode.

5: Host mode.

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPDEN DEVADDR<6:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPDEN: Low-Speed Enable Indicator bit

1 = Next token command to be executed at low-speed

0 = Next token command to be executed at full-speed

bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

FRML<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 FRML<7:0>: The 11-bit Frame Number Lower bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — FRMH<2:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-3 Unimplemented: Read as ‘0’

bit 2-0 FRMH<2:0>: The Upper 3 bits of the Frame Number bits

The register bits are updated with the current frame number whenever a SOF TOKEN is received.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PID<3:0>(1) EP<3:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 PID<3:0>: Token Type Indicator bits(1)

0001 = OUT (TX) token type transaction

1001 = IN (RX) token type transaction

1101 = SETUP (TX) token type transaction

Note: All other values are reserved and must not be used.

bit 3-0 EP<3:0>: Token Command Endpoint Address bits

The four bit value must specify a valid endpoint.

Note 1: All other values are reserved and must not be used.

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CNT<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CNT<7:0>: SOF Threshold Value bits

Typical values of the threshold are:

0100 1010 = 64-byte packet

0010 1010 = 32-byte packet

0001 1010 = 16-byte packet

0001 0010 = 8-byte packet

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

BDTPTRL<15:9> —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-1 BDTPTRL<15:9>: BDT Base Address Low bits

This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the BDT’s

starting location in the system memory.

The 32-bit BDT base address is 512 byte aligned.

bit 0 Unimplemented: Read as ‘0’

PIC32 Family Reference Manual

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

————————

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRH<23:16>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRH<23:16>: BDT Base Address High bits

This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the BDT’s

starting location in the system memory.

The 32-bit BDT base address is 512 byte aligned.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BDTPTRU<31:24>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRU<31:24>: BDT Base Address Upper bits

This 8-bit value provides address bits 31 through 24 of the BDT base address, which defines the BDT’s

starting location in the system memory.

The 32-bit BDT base address is 512 byte aligned.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 31 bit 24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 23 bit 16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit

U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)

1 = Direct connection to a low-speed device enabled

0 = Direct connection to a low-speed device disabled; hub required with PRE_PID

bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)

1 = Retry NAK’d transactions disabled

0 = Retry NAK’d transactions enabled; retry done in hardware

bit 5 Unimplemented: Read as ‘0’

bit 4 EPCONDIS: Bidirectional Endpoint Control bit

If EPTXEN = 1 1 and EPRXEN = :

1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed

0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed

Otherwise, this bit is ignored.

bit 3 EPRXEN: Endpoint Receive Enable bit

1 = Endpoint n receive enabled

0 = Endpoint n receive disabled

bit 2 EPTXEN: Endpoint Transmit Enable bit

1 = Endpoint n transmit enabled

0 = Endpoint n transmit disabled

bit 1 EPSTALL: Endpoint Stall Status bit

1 = Endpoint n was stalled

0 = Endpoint n was not stalled

bit 0 EPHSHK: Endpoint Handshake Enable bit

1 = Endpoint Handshake enabled

0 = Endpoint Handshake disabled (typically used for isochronous endpoints)

PIC32 Family Reference Manual

27.3 OPERATION

This section contains a brief overview of USB operation, followed by USB OTG module

implementation specifics, and module initialization requirements.

27.3.1 USB 2.0 Operation Overview

USB is an asynchronous serial interface with a tiered star configuration. USB is implemented as

a master/slave configuration. On a given bus, there can be multiple (up to 127) slaves (devices),

but there is only one master (host).

27.3.2 Modes of Operation

The following USB implementation modes are described in this overview:

• Host mode

- USB Standard Host mode: The USB implementation that is typically used for a

personal computer

- Embedded Host mode: The USB implementation that is typically used for a

microcontroller

• Device mode – the USB implementation that is typically used for a peripheral such as a

thumb drive, keyboard or mouse

• OTG Dual Role mode – the USB implementation in which an application may dynamically

switch its role as either host or device

27.3.2.1 HOST MODE

The host is the master in a USB system and is responsible for identifying all devices connected

to it (enumeration), initiating all transfers, allocating bus bandwidth and supplying power to any

bus-powered USB devices connected directly to it.

27.3.2.1.1 USB Standard Host

In USB Standard Host mode, the following features and requirements are relevant:

• Large variety of devices are supported

• Supports all USB transfer types

• USB hubs are supported (allows connection of multiple devices simultaneously)

• Device drivers can be updated to support new devices

• Type ‘A’ receptacle is used for each port

• Each port must be able to deliver a minimum of 100 mA for a configured or unconfigured

device, and optionally, up to 500 mA for a configured device

• Full-speed and low-speed protocols must be supported (high-speed can be supported)

27.3.2.1.2 Embedded Host

In Embedded Host mode, the following features and requirements are relevant:

• Only supports a specific list of devices, referred to as a Targeted Peripheral List (TPL)

• Only required to support those transfer types that are required by devices in the TPL

• USB hub support is optional

• Device drivers are not required to be updatable

• Type ‘A’ receptacle is used for each port

• Only those speeds required by devices in the TPL must be supported

• Each port must be able to deliver a minimum of 100 mA for a configured or unconfigured

device, and optionally, up to 500 mA for a configured device

Note: A good understanding of USB can be gained from documents that are available on

the USB implementers web site. In particular, refer to “Universal Serial Bus

Specification, Revision 2.0” (http://www.usb.org/developers/docs).

Note: High-speed mode is not supported by the USB OTG module.

Section 27. USB On-The-Go (OTG)

USB On-The-Go

(OTG)

The USB OTG module supports full-speed operation in Host and Device modes, and supports

low-speed operation in Host mode.

Information contrasting the timeliness, data integrity, data size and speed of each transfer, or

transaction, type is shown in Table 27-2.

27.3.3.2 BANDWIDTH ALLOCATION

Control transfers, or transactions, are guaranteed to be at least 10% of the available bandwidth

within a given frame. The remainder is available for allocation to Interrupt and Isochronous trans-

fers. Bulk transfers are allocated from any bandwidth not allocated to control, interrupt or isochro-

nous transfers. Bulk transfers are not assured bandwidth. However, in practice, they have the

greatest bandwidth since frames are rarely completely allocated.

27.3.3.3 ENDPOINTS AND USB DESCRIPTORS

All data transferred on the bus is sent or received through endpoints. USB supports devices with

up to 16 endpoints. Each endpoint can have transmit (TX) and/or receive (RX) functionality. Each

endpoint uses one transaction type. Endpoint 0 is the default control transfer endpoint.

27.3.4 Physical Bus Interface

27.3.4.1 BUS SPEED SELECTION

The USB specification defines full-speed operation as 12 Mbps and low-speed operation as 1.5

Mbps. A data line pull-up resistor is used to identify a device as full-speed or low-speed. For

full-speed operation, the D+ line is pulled up; for low-speed operation, the D- line is pulled up.

27.3.4.2 VBUS CONTROL

VBUS is the 5V USB power supplied by the host, or a hub, to operate bus-powered devices. The

need for VBUS BUS control depends on the role of the application. If V power must be enabled and

disabled, the control must be managed by firmware.

The following list describes the VBUS operation:

• Standard host typically supplies power to the bus at all times

• Host may switch off VBUS to save power

• USB device never powers the bus – VBUS pulsing may be supported as part of the SRP

• OTG A-device supplies power to the bus, and typically turns off VBUS to conserve power

• OTG B-device can pulse VBUS for SRP

Table 27-2: Transaction Types (Full-Speed Operation)

Transaction Type Timeliness Ensured Data Integrity Ensured Maximum Packet

Size

Maximum

Throughput(1)

Control Yes Yes 64 0.83 /s

Interrupt Yes Yes 64 1.22 /s

Isochronous Yes No 1023 1.28 /s

Bulk No Yes 64 1.22 /s

Note 1: These numbers reflect the theoretical maximum data throughput, including protocol overhead, on an other-

wise empty bus. The bit stuffing overhead required by the Non-Return to Zero Inverted (NRZI) encoding is

not included in the calculations.

Note: The PIC32 device does not supply the VBUS power. Refer to the specific device data

sheet for VBUS electrical parameters.

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	PIC32MX440F256H

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