Microchip PIC32MX330F064L Handleiding

Microchip Niet gecategoriseerd PIC32MX330F064L

Lees hieronder de 📖 handleiding in het Nederlandse voor Microchip PIC32MX330F064L (64 pagina's) in de categorie Niet gecategoriseerd. Deze handleiding was nuttig voor 19 personen en werd door 2 gebruikers gemiddeld met 4.5 sterren beoordeeld

Download PDF

Pagina 1/64

Section 13. Parallel Master Port (PMP)

HIGHLIGHTS

This section of the manual contains the following major topics:

13.1 Introduction .................................................................................................................. 13-2

13.2 Control Registers ......................................................................................................... 13-3

13.3 Master Modes of Operation ....................................................................................... 13-18

13.4 Slave Modes of Operation ......................................................................................... 13-41

13.5 Interrupts.................................................................................................................... 13-48

13.6 Operation in Power-Saving and Debug Modes.......................................................... 13-50

13.7 Effects of Various Resets........................................................................................... 13-50

13.8 Parallel Master Port Applications............................................................................... 13-51

13.9 Parallel Slave Port Application...................................................................................13-56

13.10 Direct Memory Access Support ................................................................................. 13-56

13.11 I/O Pin Control ........................................................................................................... 13-57

13.12 Related Application Notes..........................................................................................13-60

13.13 Revision History......................................................................................................... 13-61

PIC32 Family Reference Manual

13.1 INTRODUCTION

The Parallel Master Port (PMP) is a parallel 8-bit/16-bit I/O module specifically designed to

communicate with a wide variety of parallel devices such as communications peripherals, LCDs,

external memory devices and microcontrollers. Because the interfaces to parallel peripherals

vary significantly, the PMP module is highly configurable. The key features of the PMP module

include:

• Up to 24 programmable address lines

• Up to two Chip Select lines with two alternate Chip Selects for extended addressing

• Programmable strobe options:

- Individual read and write strobes or Read/write strobe with enable strobe

• Address auto-increment/auto-decrement

• Programmable address/data multiplexing

• Programmable polarity on control signals

• Legacy parallel slave port support

• Enhanced parallel slave support:

- Address support

- 4 bytes deep, auto-incrementing buffer

• Schmitt Trigger or TTL input buffers

• Programmable Wait states

• Freeze option for in-circuit debugging

• Separate configurable read/write registers or dual buffers for Master mode (not available on

all devices)

Figure 13-1: PMP Module Pinout and Connections to External Devices

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Parallel Master Port (PMP)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

PMA0

PMA14

PMA15

PMRD

PMWR

PMENB

PMRD/PMWR

PMCS1

PMA1

PMA<13:2>

(2)

PMALL

PMALH

PMCS2

EEPROM

Address Bus

Data Bus

Control Lines

LCD FIFO

Microcontroller

8-bit/16-bit data (with or without multiplexed addressing)

Up to 24-bit address

buffer

PMD<15:8>

(1)

PMA<7:0>

PMA<15:8>

PMD<7:0>

Parallel Master Port

PIC32

Note 1: The PMD<15:8> data pins are only available on PIC32 devices with 100 or more pins.

2: 24-bit addressing is available in Extended mode.

Section 13. Parallel Master Port (PMP)

13.2 CONTROL REGISTERS

The PMP module uses these Special Function Registers (SFRs):

•PMCON: Parallel Port Control Register

This register contains the bits that control much of the module’s basic functionality. A key bit

is the ON control bit, which is used to Reset, enable or disable the module.

When the module is disabled, all of the associated I/O pins revert to their designated I/O

function. In addition, any read or write operations active or pending are stopped, and the

BUSY bit is cleared. The data within the module registers is retained, including the data in

PMSTAT register. Therefore, the module could be disabled after a reception, and the last

received data and status would still be available for processing.

When the module is enabled, all buffer control logic is reset, along with PMSTAT.

All other bits in PMCON control address multiplexing enable various port control signals, and

select control signal polarity. These are discussed in detail in

13.3.1 “Parallel Master Port

Configuration Options”.

•PMMODE: Parallel Port Mode Register

This register contains bits that control the operational modes of the module. Master/Slave

mode selection and configuration options for both modes, are set by this register. It also

contains the universal status flag, BUSY, which is used in master modes to indicate that an

operation by the module is in progress.

Details on the use of the PMMODE bits to configure PMP operation are provided in

13.3 “Master Modes of Operation” and 13.4 “Slave Modes of Operation”.

•PMADDR: Parallel Port Address Register

This register contains the address to which outgoing data is to be written, as well as the Chip

Select control bits for addressing parallel slave devices. The PMADDR register is only used

in Single Buffer Master modes.

•PMDOUT: Parallel Port Data Output Register

This register is used only in Slave mode for buffered output data.

•PMDIN: Parallel Port Data Input Register

This register is used by the PMP module in both Master and Slave modes.

In Slave mode, this register is used to hold data that is asynchronously clocked in. Its

operation is described in 13.4.2 “Buffered Parallel Slave Port Mode”.

In Single Buffer Master modes, PMDIN is the holding register for both incoming and outgoing

data. Its operation in Master mode is described in 13.3.3 “Read Operation” and

13.3.4 “Write Operation”.

In Dual Buffer Master modes, the PMDIN is the holding register for the outgoing data. A

separate PMRDIN register holds the incoming data.

•PMAEN: Parallel Port Pin Enable Register

This register controls the operation of address and Chip Select pins associated with the PMP

module. Setting these bits allocates the corresponding microcontroller pins to the PMP

module; clearing the bits allocates the pins to port I/O or other peripheral modules

associated with the pin.

•PMSTAT: Parallel Port Status Register (Slave modes only)

This register contains status bits associated with buffered operating modes when the port is

functioning as a slave port. This includes overflow, underflow and full flag bit.

These flags are discussed in detail in 13.4.2 “Buffered Parallel Slave Port Mode”.

•PMWADDR: Parallel Port Write Address Register

This register contains the address to which outgoing data is to be written, as well as the Chip

Select control bits for addressing parallel slave devices. The PMWADDR register is only

used in Dual Buffer Master modes.

PIC32 Family Reference Manual

•PMRADDR: Parallel Port Read Address Register

This register contains the address to which incoming data is to be read, as well as the Chip

Select control bits for addressing parallel slave devices. The PMRADDR register is only

used in Dual Buffer Master modes.

•PMRDIN: Parallel Port Read Input Data Register

In Dual Buffer Master modes, PMRDIN is the holding register for the incoming data. Its

operation in Master mode is described in 13.3.3 “Read Operation” and 13.3.4 “Write

Operation”.

Table 13-1 provides a brief summary of all PMP-module-related registers. Corresponding registers

detailed description of each bit.

Table 13-1: PMP Special Function Register Summary

Name

(1)

Bit

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 27/11 Bit 25/9 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4Bit 28/12 Bit 26/10 Bit 24/8 Bit 19

PMCON 31:16 — — — — — — — — RDSTART

(2)

— — — —

15:0 ON — SIDL CSF<1:0> CS2P CS1ADRMUX<1:0> PMPTTL PTWREN PTRDEN ALP

PMMODE 31:16 — — — — — — — — — — — — —

15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0>

PMADDR 31:16 — — — — — — — — CS2A CS1A A

ADDR23 ADDR22

15:0

CS2 CS1

ADDR<13:0>

ADDR15

(2)

ADDR14

(2)

PMDOUT 31:16 DATAOUT<31:16>

15:0 DATAOUT<15:0>

PMDIN 31:16 DATAIN<31:16>

15:0 DATAIN<15:0>

PMAEN 31:16 — — — — — — — — PTEN<23:22> P

15:0 PTEN<15:0>

PMSTAT 31:16 — — — — — — — — — — — — —

15:0 IBF IBOV IB1F— — IB3F IB2F IB0F OBE OBUF — — OB

PMWADDR

(2)

31:16 — — — — — — — — WCS2A WCS1A W

WADDR23 WADDR22

15:0

WCS2 WCS1

— — — — — — — — — — —

WADDR15 WADDR14

WADDR<13:0>

PMRADDR

(2)

31:16 — — — — — — — — RCS2A RCS1A R

RADDR23 RADDR22

15:0

RCS2 RCS1

— — — — — — — — — — —

RADDR15 RADDR14

RADDR<13:0>

PMRDIN

(2)

31:16 31:16 — — — — — — — — — — — —

15:0 15:0 RDATAIN<15:0>

Legend: — = unimplemented, read as ‘0’.

Note 1: With the exception of the PMSTAT register, these registers have an associated Clear, Set, and Invert registers at an offset of 0x4, 0x8, and 0xC bytes, respectiv

with CLR, Set, or INV appended to the register name (e.g., PMCONCLR). Writing a ‘1’ to any bit position in these registers will Clear, Set, and Invert valid bits in t

2: This bit or register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific device data sheet to determine availability.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-0, HC

U-0 U-0 U-0 U-0 U-0

R/W-0

U-0

RDSTART

(3)

— — — — — DUALBUF

(3)

EXADDR

(3)

15:8

R/W-0 R/W-0U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1)

— SIDL

ADRMUX<1:0>

PMPTTL PTWREN PTRDEN

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

CSF<1:0>

(2)

ALP

(2)

CS2P

(2)

CS1P

(2)

— WRSP RDSP

Legend: HC = Hardware cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 RDSTART: Start a Read on the PMP Bus bit

(3)

1 = Start a read cycle on the PMP bus

0 = No effect

This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE<15>) = 0.

bit 22-18 Unimplemented: Read as ‘0’

bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit

(3)

This bit is only valid in Master mode.

1 = PMP uses separate registers for reads and writes

Reads: PMRADDR and PMRDIN

Writes: PMRWADDR and PMDOUT

0 = PMP uses legacy registers for reads and writes

Reads/Writes: PMADDR and PMRDIN

bit 16 EXADDR: Parallel Master Port Extended 24-bit Addressing (Valid in Demultiplexed Master Mode Only)

(3)

1 = PMP 24 bit addressing is enabled

0 = PMP 24 bit addressing is disabled

bit 15 ON: Parallel Master Port Enable bit

(1)

1 = PMP enabled

0 = PMP disabled, no off-chip access performed

bit 14 Unimplemented: Write ‘0’; ignore read

bit 13 SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits

11 = All 16 bits of address are multiplexed on PMD<15:0> pins

10 = All 16 bits of address are multiplexed on PMD<7:0> pins

01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>

00 = Address and data appear on separate pins

bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit

1 = PMP module uses TTL input buffers

0 = PMP module uses Schmitt Trigger input buffer

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when its corresponding pin is used as an address line.

3: This bit is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific

device data sheet to determine availability.

Section 13. Parallel Master Port (PMP)

bit 9 PTWREN: Write Enable Strobe Port Enable bit

1 = PMWR/PMENB port is enabled

0 = PMWR/PMENB port is disabled

bit 8 PTRDEN: Read/Write Strobe Port Enable bit

1 = PMRD/PMWR port is enabled

0 = PMRD/PMWR port is disabled

bit 7-6 CSF<1:0>: Chip Select Function bits

(2)

11 = Reserved

10 = PMCS2/PMCS2A and PMCS1/PMCS1A function as Chip Select

01 = PMCS2/PMCS2A functions as Chip Select, PMCS1/PMCS1A functions as address bit

00 = PMCS2/PMCS2A and PMCS1/PMCS1A function as address bits

bit 5 ALP: Address Latch Polarity bit

(2)

1 = Active-high (PMALL and PMALH)

0 = Active-low (PMALL and PMALH)

bit 4 CS2P: Chip Select 2/2A Polarity bit

(2)

1 = Active-high

0 = Active-low

Note: PMCS1A and PMCS2A are only applicable when EXADDR=1

bit 3 CS1P: Chip Select 1/1A Polarity bit

(2)

1 = Active-high

0 = Active-low

bit 2 Unimplemented: Write ‘0’; ignore read

bit 1 WRSP: Write Strobe Polarity bit

For Slave Modes and Master mode 2 MODE <1:0> (PMMODE<9:8> = , , ):00 01 10

1 = Write strobe active-high (PMWR)

0 = )Write strobe active-low (PMWR

For Master mode 1 MODE <1:0> (PMMODE<9:8> = ):11

1 = Enable strobe active-high (PMENB)

0 = Enable strobe active-low (PMENB)

bit 0 RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 MODE <1:0> (PMMODE<9:8> = , , ):00 01 10

1 = Read strobe active-high (PMRD)

0 = )Read strobe active-low (PMRD

For Master mode 1 MODE <1:0> (PMMODE<9:8> = ):11

1 = Read/write strobe active-high (PMRD/PMWR)

0 = Read/write strobe active-low (PMRD/PMWR)

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.

2: These bits have no effect when its corresponding pin is used as an address line.

3: This bit is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific

device data sheet to determine availability.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAITB<1:0>

(1)

WAITM<3:0>

(1)

WAITE<1:0>

(1)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Write ‘0’; ignore read

bit 15 BUSY: Busy bit (Master mode only)

1 = Port is busy

0 = Port is not busy

bit 14-13 IRQM<1:0>: Interrupt Request Mode bits

11 = Reserved, do not use

10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),

or on a read or write operation when PMA<1:0> = 11 (Addressable Slave mode only)

01 = Interrupt generated at the end of the read/write cycle

00 = No Interrupt generated

bit 12-11 INCM<1:0>: Increment Mode bits

11 00 = Slave mode read and write buffers auto-increment MODE<1:0> (PMMODE<9:8> = only)

10 = Decrement ADDR<15:0> by 1 every read/write cycle

(2,4)

01 = Increment ADDR<15:0> by 1 every read/write cycle

(2,4)

00 = No increment or decrement of address

bit 10 MODE16: 8/16-bit Mode bit

1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer

0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer

bit 9-8 MODE<1:0>: Parallel Port Mode Select bits

11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>

(3)

)

10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>

(3)

)

01 = Enhanced Slave mode, control signals (

PMRD

PMWR

PMCS

, PMD<7:0> and PMA<1:0>)

00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)

bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits

(1)

11 = Data wait of 4 T

; multiplexed address phase of 4 T

10 = Data wait of 3 T

; multiplexed address phase of 3 T

01 = Data wait of 2 T

; multiplexed address phase of 2 T

00 = Data wait of 1 T

; multiplexed address phase of 1 T

(default)

Note 1: When WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 T

PBCLK

cycle for a

write operation; WAITB = 1 T

PBCLK

cycle, WAITE = 0 T

PBCLK

cycles for a read operation.

2: Address bit A15/A23 and A14/A22 are not subject to auto-increment/decrement if configured as Chip

Select CS2/CS2A and CS1/CS1A.

3: These pins are active when MODE16 = 1 (16-bit mode).

4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width.

Section 13. Parallel Master Port (PMP)

bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits

(1)

1111 = Wait of 16 T

•

0001 = Wait of 2 T

0000 = Wait of 1 T

(default)

bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits

(1)

11 = Wait of 4 T

10 = Wait of 3 T

01 = Wait of 2 T

00 = Wait of 1 T

(default)

For read operations:

11 = Wait of 3 T

10 = Wait of 2 T

01 = Wait of 1 T

00 = Wait of 0 T

(default)

Note 1: When WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 T

PBCLK

cycle for a

write operation; WAITB = 1 T

PBCLK

cycle, WAITE = 0 T

PBCLK

cycles for a read operation.

2: Address bit A15/A23 and A14/A22 are not subject to auto-increment/decrement if configured as Chip

Select CS2/CS2A and CS1/CS1A.

3: These pins are active when MODE16 = 1 (16-bit mode).

4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0U-0 U-0 U-0 U-0

— — — — — — — —

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CS2A

(2)

CS1A

(2)

ADDR<21:16>

ADDR23

(2)

ADDR22

(2)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

CS2

(1)

CS1

(1)

ADDR<13:8>

ADDR15

(1)

ADDR14

(1)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0

ADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Read as ‘Unimplemented: 0’

bit 23 CS2A: Chip Select 2 bit

(2)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (ADDR23 function is selected)

bit 23 ADDR23: Target Address bit 23

(2)

bit 22 CS1A: Chip Select 1 bit

(2)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (ADDR22 function is selected)

bit 22 ADDR22: Target Address bit 22

(2)

bit 21-16 ADDR<21:16> Address bits

bit 15 CS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (ADDR15 function is selected)

bit 15 ADDR15: Target Address bit 15

(1)

bit 14 CS1: Chip Select 1 bit

(1)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (ADDR14 function is selected)

bit 14 ADDR14: Target Address bit 14

(1)

bit 13-0 ADDR<13:0>: Address bits

Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 0.

2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 1.

Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target

addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the

PMRADDR register for Read operations and the PMWADDR register for Write operations.

Section 13. Parallel Master Port (PMP)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAOUT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DATAOUT<31:0>: Output Data Port bits for 8-bit write operations in Slave mode

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATAIN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DATAIN<31:0>: Input/Output Data Port bits for 8-bit or 16-bit read/write operations in Master mode Input

Data Port for 8-bit read operations in Slave mode.

Section 13. Parallel Master Port (PMP)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

PTEN<23:22> PTEN<21:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN<15:14> PTEN<13:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN<7:2> PTEN<1:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

31-24 Unimplemented: Write ‘0’; ignore read

bit 23-22 PTEN<23:22>: PMCSx Strobe Enable bits

1 = PMA23 and PMA22 function as either PMA<23:22> or PMCS2A and PMCS1A

(1)

0 = PMA23 and PMA22 function as port I/O

bit 21-16 PTEN<21:16>: PMP Address Port Enable bits

1 = PMA<21:16> function as PMP address lines

0 = PMA<21:16> function as port I/O

bit 15-14 PTEN<15:14>: PMCSx Strobe Enable bits

1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1

(1)

0 = PMA15 and PMA14 function as port I/O

bit 13-2 PTEN<13:2>: PMP Address Port Enable bits

1 = PMA<13:2> function as PMP address lines

0 = PMA<13:2> function as port I/O

bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

(2)

0 = PMA1 and PMA0 pads function as port I/O

Note 1: The use of these pins as address or chip select lines selected by the CSF<1:0> bits (PMCON<7:6>).

2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode

selected by the ADRMUX<1:0> bits in the PMCON register.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R-0 U-0R/W-0 U-0 R-0 R-0 R-0 R-0

IBF IBOV IB3F IB2F— — IB1F IB0F

7:0

R-1 U-0R/W-0 U-0 R-1 R-1 R-1 R-1

OBE OBUF — — OB3E OB2E OB1E OB0E

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Write ‘0’; ignore read

bit 15 IBF: Input Buffer Full Status bit

1 = All writable input buffer registers are full

0 = Some or all of the writable input buffer registers are empty

bit 14 IBOV: Input Buffer Overflow Status bit

1 = A write attempt to a full input byte buffer occurred (must be cleared in software)

0 = No overflow occurred

This bit is set (= 1) in hardware; can only be cleared (= 0) in software.

bit 13-12 Unimplemented: Write ‘0’; ignore read

bit 11-8 IBnF: Input Buffer n Status Full bits

1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)

0 = Input Buffer does not contain any unread data

bit 7 OBE: Output Buffer Empty Status bit

1 = All readable output buffer registers are empty

0 = Some or all of the readable output buffer registers are full

bit 6 OBUF: Output Buffer Underflow Status bit

1 = A read occurred from an empty output byte buffer (must be cleared in software)

0 = No underflow occurred

This bit is set (= 1) in hardware; can only be cleared (= 0) in software.

bit 5-4 Unimplemented: Write ‘0’; ignore read

bit 3-0 OBnE: Output Buffer n Status Empty bits

1 = Output buffer is empty (writing data to the buffer will clear this bit)

0 = Output buffer contains data that has not been transmitted

Section 13. Parallel Master Port (PMP)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0

— — — — — — — —

23:26

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

WCS2A

(2)

WCS1A

(2)

WADDR<21:16>

WADDR23

(2)

WADDR22

(2)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

WCS2

(1)

WCS1

(1)

WADDR<13:8>

WADDR15

(1)

WADDR14

(1)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

WADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 WCS2A: Chip Select 2 bit

(2)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (WADDR23 function is selected)

bit 23 WADDR23: Target Address bit 23

(2)

bit 22 WCS1A: Chip Select 1 bit

(2)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (WADDR22 function is selected)

bit 22 WADDR22: Target Address bit 22

(2)

bit 21-16 WADDR<21:16>: Address bits

bit 15 WCS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (WADDR15 function is selected)

bit 15 WADDR15: Target Address bit 15

(1)

bit 14 WCS1: Chip Select 1 bit

(1)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (WADDR14 function is selected)

bit 14 WADDR14: Target Address bit 14

(1)

bit 13-0 WADDR<13:0>: Address bits

Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 0.

2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 1.

Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’.

2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-

cific device data sheet to determine availability.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0

— — — — — — — —

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

RCS2A

(2)

RCS1A

(2)

RADDR<21:16>

RADDR23

(2)

RADDR22

(2)

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

RCS2

(1)

RCS1

(1)

RADDR<13:8>

RADDR15

(1)

RADDR14

(1)

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0

RADDR<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Read as ‘Unimplemented: 0’

bit 23 RCS2A: Chip Select 2 bit

(2)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (RADDR23 function is selected)

bit 23 RADDR23: Target Address bit 23

(2)

bit 22 RCS1A: Chip Select 1 bit

(2)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (RADDR22 function is selected)

bit 22 RADDR22: Target Address bit 22

(2)

bit 21-16 RADDR<21:16>: Address bits

bit 15 RCS2: Chip Select 2 bit

(1)

1 = Chip Select 2 is active

0 = Chip Select 2 is inactive (RADDR15 function is selected)

bit 15 RADDR15: Target Address bit 15

(1)

bit 14 RCS1: Chip Select 1 bit

(1)

1 = Chip Select 1 is active

0 = Chip Select 1 is inactive (RADDR14 function is selected)

bit 14 RADDR14: Target Address bit 14

(1)

bit 13-0 RADDR<13:0>: Address bits

Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 0.

2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)

when EXADDR = 1.

Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’.

2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-

cific device data sheet to determine availability.

Section 13. Parallel Master Port (PMP)

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

RDATAIN<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

RDATAIN<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 RDATAIN<15:0>: Port Read Input Data bits

Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’ and exclusively for reads. If

the DUALBUF bit is ‘0’, the PMDIN register (Register 13-5) is used for reads instead of PMRDIN.

2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-

cific device data sheet to determine availability.

PIC32 Family Reference Manual

13.3 MASTER MODES OF OPERATION

In its master modes, the PMP module can provide a 8-bit or 16-bit data bus, up to 24 bits of

address, and all the necessary control signals to operate a variety of external parallel devices

such as memory devices, peripherals and slave microcontrollers. The PMP master modes

provide a simple interface for reading and writing data, but not executing program instructions

from external devices, such as SRAM or Flash memories.

Because there are a number of parallel devices with a variety of control methods, the PMP

module is designed for flexibility to accommodate a range of configurations. Some of these

features include:

• 8-bit and 16-bit data modes

• Configurable address/data multiplexing

• Up to two Chip Select lines

• Up to 24 selectable address lines

• Address auto-increment and auto-decrement

• Selectable polarity on all control lines

• Configurable Wait states at different stages of the read/write cycle

• Separate configurable read/write registers for Master mode (not available on all devices)

13.3.1 Parallel Master Port Configuration Options

13.3.1.1 8-BIT AND 16-BIT DATA MODES

The PMP in Master mode supports data with widths of 8 and 16 bits. By default, the data width

is 8 bits wide, MODE16 bit . To select a data width of 16 bits, set (PMMODE<10>) = 0

MODE16 = 1. When configured in 8-bit Data mode, the upper 8 bits of the data bus, PMD<15:8>,

are not controlled by the PMP module and are available as general purpose I/O pins.

13.3.1.2 DUAL BUFFER MODE

Dual Buffer mode acts similar to Single Buffer mode, except the PMDIN read and write register,

which has been expanded to both the PMDOUT and PMRDIN read and write registers. This

feature was added to make PMP bus transactions more efficient when both read and write are

being performed at high rates. It saves the time to have to store either read or write data while

switching through transactions.

The PMDOUT and PMRDIN registers share the PMP bus transactions for incoming and outgoing

data. The PMWADDR and PMRADDR registers, instead of the PMADDR register, share the

PMP bus for both incoming and outgoing address line data.

13.3.1.3 CHIP SELECT

Two Chip Select lines, PMCS1 and PMCS2, are available for master modes. These lines are

multiplexed with the Most Significant bits (MSbs) of the address bus. When a pin is configured

as a Chip Select, it is not included in any address auto-increment/decrement. It is possible to

enable both PMCS2 and PMCS1 as Chip Selects, or enable only PMCS2 as a Chip Select,

allowing PMCS1 to function strictly as an address line. It is not possible to enable PMCS1 alone.

If extended addressing is used, then PMCS1A and PMCS2A are used as the chip selects.The

Chip Select signals are configured using the Chip Select Function bits CSF<1:0>

(PMCON<7:6>).

Note: This mode is not available on all devices. Refer to the “Parallel Master Port

(PMP)” chapter in the specific device data sheet to determine availability.

Table 13-2: Chip Select Control

CSF<1:0> Function

10 PMCS2, PMCS1 = Enabled

01 PMCS2 = Enabled, PMCS1 = Disabled

00 PMCS2 = Disabled, PMCS1 = Disabled

Section 13. Parallel Master Port (PMP)

13.3.1.4 PORT PIN CONTROL

There are several bits available to configure the presence or absence of control and address

signals in the module. These bits are PTWREN (PMCON<9>), PTRDEN (PMCON<8>) and

PTEN<23> (PMAEN<23:0>). They provide the ability to conserve pins for other functions and

allow flexibility to control the external address. When any one of these bits is set, the associated

function is present on its associated pin; when clear, the associated pin reverts to its defined I/O

port function.

Setting a PTEN bit will enable the associated pin as an address pin and drive the corresponding

data contained in the PMADDR register. Clearing any PTEN bit will force the pin to revert to its

original I/O function.

For the pins configured as Chip Select (PMCS1/1A or PMCS2/2A) with the corresponding PTEN

bit set, Chip Select pins drive inactive data when a read or write operation is not being performed.

The PTEN0 and PTEN1 bits also control the PMALL and PMALH signals. When multiplexing is

used, the associated address latch signals should be enabled. For I/O pin configuration, see

13.11 “I/O Pin Control”.

13.3.1.5 READ/WRITE CONTROL

The PMP module supports two distinct read/write signaling methods. In Master mode 1, read and

write strobe are combined into a single control line, PMRD/PMWR; a second control line,

PMENB, determines when a read or write action is to be taken. In Master mode 2, read and write

strobes (PMRD and PMWR) are supplied on separate pins.

13.3.1.6 CONTROL LINE POLARITY

All control signals (PMRD, PMWR, PMENB, PMALL, PMALH, PMCS1/1A and PMCS2/2A) can

be individually configured for either positive or negative polarity. Configuration is controlled by

separate bits in the PMCON register, as shown in Table 13-3.

13.3.1.7 AUTO-INCREMENT/DECREMENT

While the PMP module is operating in one of the master modes, the INCM<1:0> bits

(PMMODE<12:11>) control the behavior of the address value. The address in the PMADDR

data width, after each read and write operation is completed, and the BUSY bit (PMMODE<15>)

goes to ‘0’.

Table 13-3: Pin Polarity Configuration

Control Pin PMCON Control Bit Active-High Select Active-Low Select

PMRD RDSP 1 0

PMWR WRSP 1 0

PMALL ALP 1 0

PMALH ALP 1 0

PMCS1/1A CS1P 1 0

PMCS2/2A CS2P 1 0

Note: The polarity of control signals that share the same output pin (for example, PMWR

and PMENB) are controlled by the same bit; the configuration depends on which

Master Port mode is being used.

PIC32 Family Reference Manual

If the Chip Select signals are disabled and configured as address bits, the bits will participate in

the increment and decrement operations; otherwise, CS2/2A and CS1/1A bit values will be

unaffected.

13.3.1.8 WAIT STATES

In Master mode, the user can control the duration of the read, write and address cycles by

configuring the module Wait states. One Wait state period is equivalent to one peripheral bus

clock cycle, T

PBCLK

. Figure 13-2 is an example of a Master mode 2 Read operation using Wait

states.

Figure 13-2: Read Operation, Wait States Enabled

Wait states can be added to the beginning, middle and end of any read or write cycle using the

corresponding WAITB, WAITM and WAITE bits in the PMMODE register.

The WAITB<1:0> bits (PMMODE<7:6>) define the number of wait cycles for the data setup prior

to the PMRD/PMWR strobe in Mode 10, or prior to the PMENB strobe in Mode 11. When

multiplexing the address and data bus, ADRMUX<1:0> bits (PMCON<12:11>) = 01 10, or 11,

WAITB defines the number of wait cycles for which the addressing period is extended.

The WAITM<3:0> bits (PMMODE<5:2>) define the number of wait cycles for the PMRD/PMWR

strobe in Mode 10, or for the PMENB strobe in Mode 11. When this Wait state setting is ‘0000’,

WAITB and WAITE are ignored. The number of Wait states for the data setup time (WAITB)

defaults to one, while the number of Wait states for data hold time (WAITE) defaults to one during

a write operation and zero during a read operation.

The WAITE<1:0> bits (PMMODE<1:0>) define the number of wait cycles for the data hold time

after the PMRD/PMWR strobe in Mode 10, or after the PMENB strobe in Mode 11.

13.3.1.9 ADDRESS MULTIPLEXING

Address multiplexing allows some or all address line signals to be generated from the data bus

during the address cycle of a read/write operation. This can be a useful option for address lines

PMA<15:0> needed as general purpose I/O pins. The user application can select to multiplex the

Table 13-4: Address INC/DEC Control

INCM<1:0> Function

10 Decrement every R/W cycle

01 Increment every R/W cycle

00 No Increment – No Decrement

PMCS2/PMCS1

TPB TPB TPB TPB TPB TPB TPB

TPB

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced

to 1 T

PBCLK

), and WAITE is ignored (E forced to 0 T

PBCLK

PMWR

PMRD

Section 13. Parallel Master Port (PMP)

lower 8 data bits, upper 8 data bits or full 16 data bits. These multiplexing modes are available in

both Master mode 1 and 2. For Multiplexing mode timing diagrams, see

13.3.8 “Master Mode

Timing”.

13.3.1.9.1 Demultiplexed Mode

Demultiplexed mode is selected by configuring the ADRMUX<1:0> bits (PMCON<12:11>) = 00.

In this mode, address bits are presented on pins PMA<15:0>.

When PMCS2 is enabled, address pin PMA15 is not available. When PMCS1 is enabled,

address pin PMA14 is not available. In 16-bit Data mode, data bits are presented on pins

PMD<15:0>. In 8-bit Data mode, data bits are presented on pins PMD<7:0>.

Figure 13-3: Demultiplexed Addressing Mode

Figure 13-4: Demultiplexed Addressing Example

Table 13-5: Address Multiplex Configurations

ADRMUX<1:0> Address/Data Multiplex Modes

11 Fully multiplexed (16 data pins PMD<15:0>)

10 Fully multiplexed (lower eight data pins PMD<7:0>)

01 Partially multiplexed (lower eight data pins PMD<7:0>)

00 Demultiplexed

Address Bus

Data Bus

Control Lines

PMRD

PMWR

PMD<7:0>

PMA14/PMCS1

PMA<13:0>

PMA15/PMCS2

PIC32

PMD<15:8>

ADRMUX<1:0> = 00

Note 1: Address pin PMA<15> is not available if PMCS2 is enabled.

Address pin PMA<14> is not available if PMCS1 is enabled.

See Note 1

PMA<14:0>

D<15:0>

A<14:0>

D<15:0>

A<14:0>

PMRD

PMWR

OE WR

PIC32

PMCS2

PMD<15:0>

32K x 16-bit Device

Address Bus

Data Bus

Control Lines

Note:

Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.

16-bit data width: MODE16 bit (PMMODE<10>) = 1.

Partial Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 00.

Extra Addressing: EXADDR bit = 0.

PIC32 Family Reference Manual

13.3.1.9.2 Partially Multiplexed Mode

Partially Multiplexed mode (8-bit data pins) is available in both 8-bit and 16-bit data bus

configurations and is selected by setting the ADRMUX<1:0> bits (PMCON<12:11>) = 01. In this

mode, the lower eight address bits are multiplexed with the lower eight data bus pins, PMD<7:0>.

The upper eight address bits are unaffected and are presented on PMA<15:8>. In this mode,

address pins PMA<7:1> are available as general purpose I/O pins.

Address pin PMA15 is not available when PMCS2 is enabled; address pin PMA14 is not

available when PMCS1 is enabled.

Address pin PMA<0> is used as an address latch enable strobe, PMALL, during which the lower

eight bits of the address are presented on the PMD<7:0> pins. Read and write sequences are

extended by at least three peripheral bus clock cycles (T

PBCLK

)

If WAITM<3:0> (PMMODE<5:2>) is non-zero, the PMALL strobe will be extended by

WAITB<1:0> (PMMODE<7:6>) Wait states.

Figure 13-5: Partial Multiplexed Addressing Mode

Figure 13-6: Partial Multiplexed Addressing Example

PMRD

PMWR

PMD<7:0>

PMA14/PMCS1

PMA<13:8>

PMA0/PMALL

PMA15/PMCS2

PIC32

Address Bus

Multiplexed Address/Data Bus

Data Bus

Control Lines

PMD<15:8>

ADRMUX<1:0> =

Note 1: Address pin PMA<15> is not available if PMCS2 is enabled.

Address pin PMA<14> is not available if PMCS1 is enabled.

See Note 1

PMA<14:8>

D<7:0> 373 A<14:0>

D<15:0>

A<7:0>

PMRD

PMWR

OE WR

PIC32

PMCS2

PMALL

A<14:8>

PMD<15:0>

32K x 16-bit Device

D<15:0>

Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.

16-bit data width: MODE16 bit (PMMODE<10>) = 1.

Partial Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 01.

The 373 shown in the diagram represents a generic 74XX family 373 latch.

Address Bus

Data Bus

Control Lines

Section 13. Parallel Master Port (PMP)

13.3.1.9.3 Fully Multiplexed Mode (8-bit Data Pins)

Fully Multiplexed mode (8-bit data pins) is available in both 8-bit and 16-bit data bus

configurations and is selected by setting the ADRMUX<1:0> bits (PMCON<12:11>) = 10. In this

mode, the entire 16 bits of the address are multiplexed with the lower eight data bus pins,

PMD<7:0>. In this mode, PMA<13:2> pins are available as general purpose I/O pins.

If PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding

address bit, PMADDR<15> or PMADDR<14> is automatically forced to ‘0’.

Address pins PMA<0> and PMA<1> are used as an address latch enable strobes, PMALL and

PMALH, respectively. During the first cycle, the lower eight address bits are presented on the

PMD<7:0> pins with the PMALL strobe active. During the second cycle, the upper eight address

bits are presented on the PMD<7:0> pins with the PMALH strobe active. The read and write

sequences are extended by at least six peripheral bus clock cycles (T

PBCLK

)

If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended

by WAITB<1:0> (PMMODE<7:6>) Wait states.

Figure 13-7: Fully Multiplexed Addressing Mode (8-bit Bus)

Figure 13-8: Fully Multiplexed Address Example (8-bit Bus)

Fully Multiplexed Address/Data Bus

Control Lines

PMRD

PMWR

PMD<7:0>

PMA14/ PMCS1

PMA1/PMALH

PMA15/ PMCS2

PIC32

PMA0/PMALL

ADRMUX<1:0> =

Note 1: Address bit PMADDR<15> is forced to ‘0’ when PMCS2 is enabled.

Address bit PMADDR<14> is forced to ‘0’ when PMCS1 is enabled.

See Note 1

Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.

8-bit data width: MODE16 bit (PMMODE<10>) = 0.

Fully Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 10.

The block labeled 373 in the diagram represents a generic 74XX family 373 latch.

Address Bus

Data Bus

Control Lines

PMD<7:0>

PMALH

D<7:0>

373 A<14:0>

D<7:0>

A<7:0>

373

PMRD

PMWR

OE WR

PIC32

PMCS2

PMALL

A<14:8>

32K x 8-bit Device

PIC32 Family Reference Manual

13.3.1.9.4 Fully Multiplexed Mode (16-bit Data Pins)

Fully Multiplexed mode (16-bit data pins) is only available in the 16-bit data bus configuration and

is selected by configuring the ADRMUX<1:0> bits (PMCON<12:11>) = 11. In this mode, the

entire 16 bits of the address are multiplexed with all 16 data bus pins, PMD<15:0>.

If PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding

address bit, PMADDR<15> or PMADDR<14> is automatically forced to ‘0’.

Address pins PMA<0> and PMA<1> are used as an address latch enable strobes, PMALL and

PMALH, respectively, and at the same time. While the PMALL and PMALH strobes are active,

the lower eight address bits are presented on the PMD<7:0> pins and the upper eight address

bits are presented on the PMD<15:8> pins. The read and write sequences are extended by at

least 3 peripheral bus clock cycles (T

PBCLK

)

If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended

by WAITB<1:0> (PMMODE<7:6>) Wait states.

Figure 13-9: Fully Multiplexed Addressing Mode (16-bit Bus)

Figure 13-10: Fully Multiplexed Addressing Example (16-bit Bus)

PMRD

PMWR

PMA1/PMALH

PMA15/ PMCS2

PIC32

PMA0/PMALL

PMD<7:0>

PMD<15:8>

PMA14/ PMCS1

ADRMUX<1:0> =

Note 1: Address bit PMADDR<15> is forced to ‘0’ when PMCS2 is enabled.

Address bit PMADDR<14> is forced to ‘0’ when PMCS1 is enabled.

Fully Multiplexed Address/Data Bus

Control Lines

See Note 1

Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.

16-bit data width: MODE16 bit (PMMODE<10>) = 1.

Fully Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) =

11.

The 373 shown in the diagram represents a generic 74XX family 373 latch.

Address Bus

Data Bus

Control Lines

PMD<15:0>

PMALH

D<15:0>

373 A<14:0>

D<15:0>

A<7:0>

373

PMRD

PMWR

OE WR

PIC32

PMCS2

PMALL

A<14:8>

32K x 16-bit Device

D<15:8>

D<7:0>

Section 13. Parallel Master Port (PMP)

13.3.2 Master Mode Configuration

The Master mode configuration is determined primarily by the interface requirements to the

external device. Address multiplexing, control signal polarity, data width and Wait states typically

dictate the specific configuration of the PMP.

To use the PMP as a master, the module must be enabled by setting the ON control bit

(PMCON<15>) = 1, and the mode must be set to one of two possible master modes. Control bits

MODE<1:0> (PMMODE<9:8>) = 10 for Master mode 2, or MODE<1:0> = 11 for Master mode 1.

The following Master mode initialization steps prepares the PMP port for communicating with an

external device.

1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit, PMPIE

(IEC1<2>) = .0

2. Stop and reset the PMP module by clearing the ON control bit (PMCON<15>) = .0

3. Configure the desired settings in the PMCON, PMMODE and PMAEN control registers.

a) Set the EXADDR PMCON<16> bit if 24 bit addressing is being used.

4. If interrupts are used:

a) Clear the interrupt flag bit, PMPIF (IFS1<2>) = .0

b) Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and the interrupt

subpriority bits PMPIS (IPC7<1:0>).

c) Enable the PMP interrupt by setting the interrupt enable bit, PMPIE = .1

5. Enable the PMP master port by setting the ON control bit = .1

The following list illustrates an example setup for a typical Master mode 2 operation:

1. Select Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = .10

2. Select 16-bit Data mode: MODE16 bit (PMMODE<10>) = .0

3. Select partially multiplexed addressing: ADRMUX<1:0> bits (PMCON<12:11>) = .01

4. Select auto address increment: INCM<1:0> bits (PMMODE<12:11>) = .01

5. Enable Interrupt Request mode: IRQM<1:0> bits (PMMODE<14:13>) = .01

6. Enable PMRD strobe: PTRDEN bit (PMCON<8>) = .1

7. Enable PMWR strobe: PTWREN bit (PMCON<9>) = .1

8. Enable PMCS2 and PMCS1 Chip Selects: CSF<1:0> bits (PMCON<7:6>) = .10

9. Select PMRD active-low pin polarity: RDSP bit (PMCON<0>) = .0

10. Select PMWR active-low pin polarity: WRSP bit (PMCON<1>) = .0

11. Select PMCS2, PMCS1 active-low pin polarity: CS2P bit (PMCON<4>) = 0 and CS1P bit

(PMCON<3>) = .0

12. Select 1 wait cycle for data setup: WAITB<1:0> bits (PMMODE<7:6>) = .00

13. Select 2 wait cycles to extend PMRD/PMWR: WAITM<3:0> bits (PMMODE<5:2>) = .0001

14. Select 1 wait cycle for data hold: WAITE<1:0> bits (PMMODE<1:0>) = .00

15. Enable upper 8 PMA<15:8> address pins: PMAEN<15:8> = 1 (the lower 8 bits can be

used as general purpose I/O).

See the code shown in Example 13-1 .

Note: It is recommended to wait for any pending read or write operation to be completed

before reconfiguring the PMP module.

PIC32 Family Reference Manual

Example 13-1: Initialization for Master Mode 2, Demultiplexed Address, 16-bit Data

/* Configuration Example: Master mode 2, 16-bit data, partially multiplexed

address/data, active-lo polarities. */

IEC1CLR = 0x0004 // Disable PMP interrupt

PMCON = 0x0000; // Stop PMP module and clear control register

PMCONSET = 0x0B80; // Configure the addressing and polarities

PMMODE = 0x2A40; // Configure the mode

PMAEN = 0xFF00; // Enable all address and Chip Select lines

IPC7SET = 0x001C; // Set priority level = 7 and

IPC7SET = 0x0003; // Set subpriority level = 3

// Could have also done this in single

// operation by assigning IPC7SET = 0x001F

IEC1SET = 0x0004; // Enable PMP interrupts

PMCONSET = 0x8000; // Enable the PMP module

Section 13. Parallel Master Port (PMP)

13.3.3 Read Operation

To perform a read on the parallel bus, the user application reads the PMDIN register. The effect

of reading the PMDIN register retrieves the current value and causes the PMP to activate the

Chip Select lines and the address bus. The read line PMRD is strobed in Master mode 2,

PMRD/PMWR and PMENB lines in Master mode 1, and the new data is latched into the PMDIN

Note that the read data obtained from the PMDIN register is actually the read value from the

previous read operation. Therefore, the first user application read will be a dummy read to initiate

the first bus read and fill the read register. See Figure 13-11, which illustrates this sequence.

Also, the requested read value will not be ready until after the BUSY bit (PMMODE<15>) is

observed low. Therefore, in a back-to-back read operation, the data read from the register will be

the same for both reads. The next read of the register will yield the new value.

In 16-bit Data mode (MODE16 bit (PMMODE<10>) = 1), the read from the PMDIN register

causes the data bus PMD<15:0> to be read into PMDIN<15:0> (see the following Note). In 8-bit

mode, MODE16 bit (PMMODE<10>) = 0, the read from the PMDIN register causes the data bus

PMD<7:0> to be read into PMDIN<7:0>. The upper 8 bits, PMD<15:8>, are ignored.

Figure 13-11: Example Read Sequence Demonstrating ‘Dummy’ Read Operation

Note: Refer to the 13.3.1.2 “Dual Buffer Mode” for additional information.

Set Initial Address = 0x4000

Dummy Read

Enable Auto-Address Increment

PMADDR = 0x4000

INCM<1:0> = 01

Read PMDIN

3. PMADDR = 0x4001

2. PMDIN updated = 0x02

0x4000 0x02

0x33

0xFA

0x7C

0x0A

1. User Reads PMDIN = (don’t care)

Read PMDIN

0x4001

0x4002

0x4003

0x4004

6. PMADDR = 0x4002

5. PMDIN updated = 0x33

4. User Reads PMDIN = 0x02

9. PMADDR = 0x4003

8. PMDIN updated = 0xFA

7. User Reads PMDIN = 0x33

Read PMDIN

PMADDR = 0x4100

0x4100 0x45

0x76

0x00

0x2A

0x93

0x4101

0x4102

0x4103

0x4104

Set New Address = 0x4100

3. PMADDR = 0x4101

2. PMDIN updated = 0x45

1. User Reads PMDIN = 0xFA (don’t care)

6. PMADDR = 0x4102

5. PMDIN updated = 0x76

4. User Reads PMDIN = 0x45

9. PMADDR = 0x4103

8. PMDIN updated = 0x00

7. User Reads PMDIN = 0x76

Dummy Read

Read PMDIN

Data in external device

memory or registers

Data in external device

memory or registers

Note:

In Dual Buffer mode, PMRDIN and PMADDR can be used. Refer to the

“PMP”

chapter in the specific

device data sheet to determine which registers are available on your device.

PIC32 Family Reference Manual

13.3.4 Write Operation

To perform a write on the parallel port, the user application writes to the PMDIN register (same

and the address bus. The write data from the PMDIN register is placed onto the PMD data bus

and the write line PMPWR is strobed in Master mode 2, PMRD/PMWR and PMENB lines in

Master Mode 1.

In 16-bit Data mode (MODE16 bit (PMMODE<10>) = 1), the write to the PMDIN register causes

PMDIN<15:0> to appear on the data bus, (PMD<15:0>). In 8-bit mode, MODE16 bit

(PMMODE<10>) = 0, the write to the PMDIN register causes PMDIN<7:0> to appear on the data

bus, PMD<7:0>. The upper 8 bits, PMD<15:8>, are ignored.

13.3.5 Master Mode Interrupts

In PMP master modes, the PMPIF bit is set on every read or write strobe. An interrupt request is

generated when the IRQM<1:0> bits (PMMODE<14:13>) are set = 01 and PMP interrupts are

enabled, PMPIE (IEC1<2>) = 1.

13.3.6 Parallel Master Port Status – The BUSY Bit

In addition to the PMP interrupt, the BUSY bit (PMMODE<15>) is provided to indicate the status

of the module. This bit is only used in Master mode.

While any read or write operation is in progress, the BUSY bit is set for all but the very last

peripheral bus cycle of the operation. This is helpful when Wait states are enabled or multiplexed

address/data is selected. While the bit is set, any request by the user to initiate a new operation

will be ignored (i.e., writing or reading the PMDIN register will not initiate a read or a write).

Since the system clock, SYSCLK, can operate faster than the peripheral bus clock in certain

configurations, or if a large number of Wait states are used, it is possible for the PMP module to

be in the process of completing a read or write operation when the next CPU instruction is

reading or writing to the PMP module. For this reason, it is highly recommended that the BUSY

bit be checked prior to any operation that accesses the PMDIN or PMADDR register.

Example 13-2 shows a polling operation of the BUSY bit prior to accessing the PMP module.

In most applications, the PMP module’s Chip Select pin(s) provide the Chip Select interface and

is under the timing control of the PMP module. However, some applications may require the PMP

Chip Select pin(s) to not be configured as a Chip Select, but as a high order address line, such

as PMA<14> or PMA<15>. In this situation, the application’s Chip Select function must be

provided by an available I/O port pin under software control. In these cases, it is especially

important that the user’s software poll the BUSY bit to ensure any read or write operation is

complete before deasserting the software controlled Chip Select.

Note: Refer to the 13.3.1.2 “Dual Buffer Mode” for additional information.

Section 13. Parallel Master Port (PMP)

Example 13-2: Example Code: Polling the BUSY Bit Flag

13.3.7 Addressing Considerations

The PMCS2/PMCS2A and PMCS1/PMCS1A Chip Select pins share functionality with address

lines A15/A23 and A14/A22. It is possible to enable both as Chip Selects, or enable only

PMCS2/PMCS2A as a Chip Select; allowing PMCS1/PMCS1A to function strictly as address line

A14/A22. It is not possible to enable only PMCS1/PMCS1A.

When configured as Chip Selects, a ‘1’ must be written into the CS bit position of the PMADDR

write a ‘1’ to the chip select bit does not prevent the address pins PMA<13:0> from being active

as the specified address appears; however, no Chip Select signal will be active.

In fully multiplexed modes, address bits PMADDR<15:0> are multiplexed with the data bus and

in the event address bits PMA15 or PMA14 are configured as Chip Selects, the corresponding

PMADDR<15:14> address bits are automatically forced to ‘0’. Disabling one or both PMCS2 and

PMCS1 makes these bits available as address bits PMADDR<15:14>.

In any of the master mode multiplexing schemes, disabling both Chip Select pins PMCS2 and

PMCS1 requires the user to provide Chip Select line control through some other I/O pin under

software control, as shown in Figure 13-12.

/* This example reads 256 16-bit words from an external device at address 0x4000 and copies

the data to a second external device at address 0x8000. The PMP port is operating in

Master mode 2. Note how the PMP’s BUSY bit is polled prior to all operations to the

PMDOUT, PMDIN or PMADDR register, except where noted. */

unsigned short DataArray<256>;

// Provide the setup code here including large Wait

// states, auto increment.

...

CopyData(); // A call to the copy function is made.

...

void CopyData()

{

PMADDR = 0x4000; // Initialize PMP address. First time, no need to poll BUSY bit

while(PMMODE & 0x8000); // Poll - if busy, wait before reading.

PMDIN; // Read the PMDIN to clear previous data and latch new

// data.

for(i=0; i<256; i++)

{

while(PMMODE & 0x8000); // Poll - if busy, wait before reading.

DataArray<i> = PMDIN; // Read the external device.

}

while(PMMODE & 0x8000); // Poll - if busy, wait before changing PMADDR.

PMADDR = 0x8000; // Address of second external device.

for(i=0; i<256; i++)

{

while(PMMODE & 0x8000); // Poll - if busy, wait before writing.

PMDIN = DataArray<i> // Write the external device.

}

return();

}

Note: Setting both A15/A23 and A14/A22 = when PMCS2/PMCS2A and 1

PMCS1/PMCS1A are enabled as Chip Selects will cause both chip selects to be

active during a read or write operation. This may enable two devices simultaneously

and should be avoided.

Note: When using Auto-Increment Address mode, the PMCS2/PMCS2A and

PMCS1/PMCS1A bits do not participate and must be controlled by the user’s soft-

ware by writing to ‘1’ to their respective PMADDR address bits.

PIC32 Family Reference Manual

Figure 13-12: PMP Chip Select Address Maps

Device 2

Selected

PMCS2 = 1

Device 1

Selected

PMCS1 = 1

No Device

Selected

Both Devices

Selected

(INVALID)

0x0000

0x4000

0x8000

0xFFFF

0xC000

1 1

PMCS2, CS1

2 – 16K Address Ranges

2 – Chip Selects

Device

Selected

I/O-pin = 1

A15, A14, I/Opin

1 – 64K Address Range

I/O-pin = Software-controlled CS

1 1

Device

Selected

PMCS2 = 1

No Device

Selected

PMCS2, A14

1 – 32K Address Range

1 – Chip Select

Section 13. Parallel Master Port (PMP)

13.3.7.1 ADDRESSING MEMORY DEVICES LARGER THAN 64K (EXADDR = 0)

When using the PMCS2 or PMCS1 Chip Select pins, the addressable range is limited to 16K or

32K locations, depending on the Chip Select pin being used. Disabling PMCS2 and PMCS1 as

Chip Selects allows these pins to function as address lines PMA15 and PMA14, increasing the

range to 64K addressable locations. A dedicated I/O pin is required to function as the Chip Select

and the user’s software must now control the function of this pin.



To interface to memory devices larger than 64K, use additional available I/O pins as the higher

order address lines A16, A17, A18, etc., as shown in Figure 13-13.

Figure 13-13: Interface to a 16 Megabit (1M x 16-bit) SRAM Memory Device

PMA<15:0>

D<15:0>

A<15:0>

D<15:0>

A<15:0>

PMRD

PMWR

OE WR

PIC32

Address Bus

Data Bus

Control Lines

RG15

PMD<15:0>

Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.

16-bit data width: MODE16 bit (PMMODE<10>) = 1.

Demultiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 00.

RD0

RD1

RD2

A<16>

A<17>

A<18>

A<19>RD3

1024K x 16-bit

Device

PIC32 Family Reference Manual

13.3.8 Master Mode Timing

A PMP Master mode cycle time is defined as the number of PBCLK cycles required by the PMP

to perform a read or write operation and is dependent on PBCLK clock speed, PMP

Address/Data Multiplexing modes, and the number of PMP wait states, if any. Refer to the

specific device data sheet for setup and hold timing characteristics.

A PMP Master mode read or write cycle is initiated by accessing (reading or writing) the PMDIN

configuration.

The actual data rate of the PMP (the rate at which the user’s code can perform a sequence of

read or write operations) will be highly dependent on several factors:

• User’s application code content

• Code optimization level

• Internal bus activity

• Other factors relating to the instruction execution speed

The following timing examples represent the common master mode configuration options. These

options vary from 8-bit to 16-bit data, non-multiplexed to fully multiplexed address, as well as with

and without Wait states. For illustration purposes only, all control signal polarities are shown as

“active-high”.

Note: During any Master mode read or write operation, the busy flag will always de-assert

1 peripheral bus clock cycle (T

PBCLK

)

, before the end of the operation, including Wait

states. The user’s application must check the status of the busy flag to ensure it is

equal to ‘0’ before initiating the next PMP operation.

Table 13-6: PMP Read/Write Cycle Times

(1)

Address/Data Multiplex Configuration ADRMUX Bit

Settings

PMP Cycle Time

(PBCLK Cycles)

Read Write

Fully Multiplexed (16-bit data) 11 5 6

Fully Multiplexed (8-bit data) 10 8 9

Partial Multiplex 01 5 6

Demultiplexed 00 2 3

Note 1: Wait states are not enabled.

Section 13. Parallel Master Port (PMP)

13.3.8.1 DEMULTIPLEXED ADDRESS AND DATA TIMING

The timing diagram in Figure 13-14 illustrates the demultiplexed timing (separate address and

data bus) for a read operation with no Wait states. A read operation requires 2 T

PBCLK

, peripheral

bus clock cycles.

Figure 13-14: 8-bit, 16-bit Read Operations, ADRMUX = 00, No Wait States, EXADDR = 0

In this timing diagram with Wait states, shown in Figure 13-15, the read operation requires

6 T

PBCLK

, peripheral bus clock cycles.

Figure 13-15: 8-bit, 16-bit Read Operations, ADRMUX = 00, Wait States Enabled, EXADDR = 0

Data from Target

PMCS2/PMCS1

PMPENB

PMRD/PMPWR

PMD<15:0>

(1)

PMA<13:0>

PMPIF

BUSY

Address<13:0>

User Read from PMDIN

(2)

Data latched into PMDIN

New Latched Data

PMDIN Previous Latched Data

Note 1: In 8-bit mode, PMD<15:8> are not implemented.

2: Read data obtained from the PMDIN register is actually the value from the previous read operation.

PMWR

PMRD

Mode 1

Mode 2

PMCS2/PMCS1

BUSY

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored (E forced

to 0 T

PBCLK

PIC32 Family Reference Manual

The timing diagram in illustrates demultiplexed timing (separate address and data Figure 13-16

bus) for a write operation with no Wait states. A write operation requires 3 T

PBCLK

, peripheral bus

clock cycles.

Figure 13-16: 8-bit, 16-bit Write Operations, ADRMUX = 00, No Wait States, EXADDR = 0

In this timing diagram with Wait states, shown in Figure 13-17, the write operation requires

7 T

PBCLK

, peripheral bus clock cycles.

Figure 13-17: 8-bit, 16-bit Write Operations, ADRMUX = 00, Wait States Enabled, EXADDR = 0

Data to Target

PMCS2, PMCS1

PMD<15:0>

(1)

PMA<13:0>

PMPIF

BUSY

Address<13:0>

Note 1: In 8-bit mode, PMD<15:8> are not implemented.

New Data

PMDIN Previous Data

User Writes to PMDIN

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

PMCS2/PMCS1

BUSY

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (2 Wait states)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored

(E forced to 1 T

PBCLK

Section 13. Parallel Master Port (PMP)

13.3.8.2 PARTIALLY MULTIPLEXED ADDRESS AND DATA TIMING

The timing diagram shown in Figure 13-18 illustrates partially multiplexed timing (address bits

<7:0> multiplexed with data bus, PMD<7:0>) for a read operation with no Wait states. A read

operation requires 5 T

PBCLK

, peripheral bus clock cycles.

Figure 13-18: 8-bit, 16-bit Read Operations, ADRMUX = 01, No Wait States

In this timing diagram with Wait states, shown in Figure 13-19, the read operation requires

10 T

PBCLK

, peripheral bus clock cycles.

Figure 13-19: 8-bit, 16-bit Read Operations, ADRMUX = 01, Wait States Enabled

PMCS2, PMCS1

PMALL

PMD<7:0>

PMA<13:8>

PMPIF

ADDRESS<7:0> LSB

BUSY

ADDRESS<13:8>

PMD<15:8>

(2)

MSB

Data from Target

New Latched Data

PMDIN Previous Latched Data

User Read from PMDIN

(1)

Data latched into PMDIN

Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation.

2: In 8-bit mode, PMD<15:8> are not implemented.

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

PMCS2/PMCS1

PMALL

BUSY

PMWR

PMRD

Mode 2

PMENB

PMRD/PMWR

Mode 1

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored (E forced

to 0 T

PBCLK

PIC32 Family Reference Manual

The timing diagram shown in Figure 13-20 illustrates partially multiplexed timing (address bits

<7:0> multiplexed with data bus, PMD<7:0>) for a write operation with no Wait states. A write

operation requires 6 T

PBCLK

, peripheral bus clock cycles.

Figure 13-20: 8-bit, 16-bit Write Operations, ADRMUX = 01, No Wait States

In this timing diagram with Wait states, shown in Figure 13-21, the write operation requires

11 T

PBCLK

, peripheral bus clock cycles.

Figure 13-21: 8-bit, 16-bit Write Operations, ADRMUX = 01, Wait States Enabled

PMCS2/PMCS1

PMALL

PMD<15:8>

(2)

PMA<13:8>

PMPIF

MSB Data to Target

BUSY

ADDRESS<13:8>

PMD<7:0> ADDRESS<7:0> LSB Data to Target

Note 1: During a write operation, there is one T

PBCLK

hold cycle following the PMWR signal.

2: In 8-bit mode, PMD<15:8> are not implemented.

New Data

PMDIN Previous Data

PMWR

(1)

PMRD

Mode 2

User Writes to PMDIN

PMENB

PMRD/PMWR

Mode 1

PMCS2/PMCS1

PMALL

BUSY

PMWR

PMRD

Mode 2

PMENB

PMRD/PMWR

Mode 1

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored (E forced

to 1 T

PBCLK

Section 13. Parallel Master Port (PMP)

13.3.8.3 FULLY MULTIPLEXED (8-BIT BUS) ADDRESS AND DATA TIMING

The timing diagram in illustrates fully multiplexed timing (address bits <15:0> Figure 13-22

multiplexed with data bus, PMD<7:0>) for a read operation with no Wait states. A read operation

requires 8 T

PBCLK

, peripheral bus clock cycles.

Figure 13-22: 8-bit, 16-bit Read Operations, ADRMUX = 10, No Wait States

In this timing diagram with Wait states, shown in Figure 13-23, the read operation requires

14 T

PBCLK

, peripheral bus clock cycles.

Figure 13-23: 8-bit, 16-bit Read Operations, ADRMUX = 10, Wait States Enabled

PMCS2/PMCS1

PMD<15:8>

(2)

PMPIF

BUSY

PMALL

PMALH

Data from Target

PMD<7:0>

MSB

LSB

ADDRESS<7:0> ADDRESS<13:8>

(3)

New Latched Data

PMDIN Previous Latched Data

Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation.

2: In 8-bit mode, PMD<15:8> are not implemented.

3: PMADDR address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects.

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

Data latched into PMDIN

User Read from PMDIN

(1)

PMCS2/PMCS1

PMALL

BUSY

PMWR

PMRD

Mode 2

PMENB

PMRD/PMWR

Mode 1

PMALH

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored

(E forced to 0 T

PBCLK

Section 13. Parallel Master Port (PMP)

13.3.8.4 FULLY MULTIPLEXED (16-BIT BUS) ADDRESS AND DATA TIMING

The timing diagram shown in illustrates fully multiplexed timing (address bits Figure 13-26

<15:0> multiplexed with data bus, PMD<15:0>) for a read operation with no Wait states. A read

operation requires 5 T

PBCLK

, peripheral bus clock cycles.

Figure 13-26: 16-bit Read Operation, ADRMUX = 11, No Wait States

In this timing diagram with Wait states, shown in Figure 13-27, the read operation requires

10 T

PBCLK

, peripheral bus clock cycles.

Figure 13-27: 16-bit Read Operation, ADRMUX = 11, Wait States Enabled

PMCS2/PMCS1

PMD<15:8>

PMPIF

BUSY

PMALL

PMALH

MSB

PMD<7:0> ADDRESS<7:0>

ADDRESS<13:8>

(2)

New Latched Data

PMDIN Previous Latched Data

LSB Data from Target

Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation.

2: PMADDR address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects.

PMENB

PMRD/PMWR

Mode 1

PMWR

PMRD

Mode 2

Data latched into PMDIN

User Read from PMDIN

(1)

PMCS2/PMCS1

PMALL

BUSY

PMWR

PMRD

Mode 2

PMENB

PMRD/PMWR

Mode 1

PMALH

Legend:

B = WAITB<1:0> = 01 (2 Wait states)

M = WAITM<3:0> = 0010 (3 Wait states)

E = WAITE<1:0> = 01 (1 Wait state)

Note: If WAITM<3:0> = 0000, M is forced to 1 T

PBCLK

, WAITB is ignored (B forced to 1 T

PBCLK

), and WAITE is ignored 

(E forced to 0 T

PBCLK

Section 13. Parallel Master Port (PMP)

13.4 SLAVE MODES OF OPERATION

The PMP module provides 8-bit (byte) legacy Parallel Slave Port (PSP) functionality as well as

new buffered and addressable slave modes.

All slave modes support 8-bit data only and the module control pins are automatically dedicated

when any of these modes are selected. The user application only needs to configure the polarity

of the PMCS1, PMRD and PMWR signals.

13.4.1 Legacy Slave Port Mode

In 8-bit PMP Legacy Slave mode, the module is configured as a PSP using control bits

MODE<1:0> (PMMODE<9:8>) = 00. In this mode, an external device such as another

microcontroller or microprocessor can asynchronously read and write data using the 8-bit data

bus PMD<7:0>, the read PMRD, write PMWR and Chip Select PMCS1 inputs.

Figure 13-30: Parallel Master/Slave Connection Example

13.4.1.1 INITIALIZATION STEPS

The following Slave mode initialization steps properly prepares the PMP port for communicating

with an external device.

1. Clear the ON control bit (PMCON<15> = ) to disable the PMP module.0

2. Select Legacy mode with the MODE<1:0> bits (PMMODE<9:8>) = 00.

3. Select the polarity of the Chip Select pin, CS1P (PMCON<3>).

4. Select the polarity of the control pins, WRSP (PMCON<1>) and RDSP (PMCON<0>).

5. If interrupts are used:

a) Clear the interrupt flag bit, PMPIF (IFS1<2>) = 0.

b) Configure the PMP interrupt priority bits, PMPIP<2:0> (IPC7<4:2>) and the interrupt

subpriority bits PMPIS (IPC7<1:0>).

c) Enable the PMP interrupt by setting the interrupt enable bit, PMPIE (IEC1<2>) = 1.

6. Set the ON control bit to ‘1’ to enable the PMP module.

Table 13-7: Slave Mode Selection

Slave Mode PMMODE<9:8> bits

(MODE<1:0>)

PMMODE<12:11> bits

(INCM<1:0>)

Addressable 01 x = don’t care

Legacy 00 x = don’t care

Buffered 00 11

Table 13-8: Slave Mode Pin Polarity Configuration

CONTROL

PMCON

Control Bit

Active-High

Select

Active-Low

Select

PMRD RDSP 1 0

PMWR WRSP 1 0

PMCS1 CS1P 1 0

Data Bus

Control Lines

D<7:0>

Master

PMD<7:0>

PMRD

PMWR

PIC32 Slave

PMCS1

PIC32 Family Reference Manual

Example 13-3: Legacy Parallel Slave Port Initialization (Example Code)

13.4.1.2 WRITE TO SLAVE PORT

When Chip Select is active and a write strobe occurs, the data on the bus pins PMD<7:0> is

captured into the lower 8 bits of the PMDIN register, PMDIN<7:0>. The PMPIF (interrupt flag bit)

is set during the write strobe. The IB0F bit will remain set until the PMDIN register is read by the

user application. If a write operation occurs while the IB0F = , the write data will be ignored and 1

an overflow condition will be generated, IB0V = 1. See the timing diagrams in 13.4.4 “Slave

Mode Read and Write Timing Diagrams”.

13.4.1.3 READ FROM SLAVE PORT

When Chip Select is active and a read strobe occurs, the data from the lower 8 bits of the

PMDOUT register (PMDOUT<7:0>) is presented onto data bus pins PMD<7:0> and read by the

master device. The PMPIF (interrupt flag bit) is set during the read strobe. The OB0E bit will

remain set until the PMDOUT register is written to by the user application. If a read operation

occurs while the OB0E = 1, the read data will be the same as the previous read data and an

underflow condition will be generated, OBUF = 1. See the timing diagrams in 13.4.4 “Slave

Mode Read and Write Timing Diagrams”.

13.4.1.4 LEGACY MODE INTERRUPT OPERATION

In PMP Legacy Slave mode, the PMPIF bit is set every read or write strobe. If using interrupts,

the user’s application vectors to an Interrupt Service Routine (ISR) where the IBF and OBE

status bits can be examined to determine if the buffer is full or empty. If not using interrupts, the

user’s application should wait for PMPIF to be set before polling the IBF and OBE Status bits to

determine if the buffer is full or empty.

13.4.2 Buffered Parallel Slave Port Mode

The 8-bit Buffered Parallel Slave Port mode is functionally identical to the Legacy Parallel Slave

Port mode with one exception: the implementation of 4-level read and write buffers. Buffered

Slave mode is enabled by setting the MODE<1:0> bits (PMMODE<9:8>) = 00, and the

INCM<1:0> bits (PMMODE<12:11>) = 11.

When the buffered mode is active, the module uses the PMDIN register as write buffers and the

PMDOUT register as read buffers. Each register is divided into four 8-bit buffer registers, four

read buffers in PMDOUT and four write buffers in PMDIN. Buffers are numbered 0 through 3,

starting with the lower byte <7:0> and progressing upward through the high byte <31:24>.

Note: On persistent interrupt implementations of the PMP, the interrupt is generated on

the falling edge of the WR signal with the WR signal configured to active-high

polarity. On non-persistent interrupt implementations of the PMP, the interrupt is

generated on the rising edge of the WR signal with the WR signal configured to

active-high polarity. Firmware should poll the IBF or IBnF bit to ensure the data is

valid before attempting to read the data from the PMP module.

Example configuration for Legacy Slave mode

IEC1CLR = 0x0004; // Disable PMP interrupt in case it is already enabled

PMCON = 0x0008; // Stop and Configure PMCON register for Legacy mode

PMMODE = 0x0000; // Configure PMMODE register

IPC7SET = 0x001C; // Set priority level = 7 and

IPC7SET = 0x0003; // Set subpriority level = 3

// Could have also done this in single

// operation by assigning IPC7SET = 0x001F

IFS1CLR = 0x0004; // Clear the PMP interrupt status flag 

IEC1SET = 0x0004; // Enable PMP interrupts

PMCONSET = 0x8000; // Enable PMP module

Section 13. Parallel Master Port (PMP)

Figure 13-31: Parallel Master/Slave Connection Buffered Example

13.4.2.1 INITIALIZATION STEPS

The following Buffered Slave mode initialization properly prepares the PMP port for

communicating with an external device.

1. Clear the ON control bit (PMCON<15> = 0) to disable the PMP module.

2. Select the Legacy mode with MODE<1:0> bits (PMMODE<9:8>) = 00.

3. Select Buffer mode with INCM<1:0> bits (PMMODE<12:11>) = 11.

4. Select the polarity of the Chip Select CS1P (PMCON<3>).

5. Select the polarity of the control pins WRSP (PMCON<1>) and RDSP (PMCON<0>).

6. If interrupts are used:

a) Clear interrupt flag bit PMPIF (IFS1<2>).

b) Configure interrupt priority and subpriority levels in IPC7.

c) Set interrupt enable bit PMPIE (IEC1<2>).

7. Set the ON control bit to ‘1’ to enable the PMP module.

Example 13-4: Buffered Parallel Slave Port Initialization (Example Code)

13.4.2.2 READ FROM SLAVE PORT

For read operations, the bytes will be sent out sequentially, starting with Buffer 0,

PMDOUT<7:0>, and ending with Buffer 3, PMDOUT<31:24>, for every read strobe. The module

maintains an internal pointer to keep track of which buffer is to be read.

Each of the buffers has a corresponding read Status bit, OBnE, in the PMSTAT register. This bit

is cleared when a buffer contains data that has not been written to the bus, and is set when data

is written to the bus. If the current buffer location being read from is empty, a buffer underflow is

generated, and the Buffer Overflow flag bit OBUF is set. If all four OBnE Status bits are set, the

Output Buffer Empty flag OBE will also be set. See the timing diagrams in 13.4.4 “Slave Mode

Read and Write Timing Diagrams”.

D<7:0>

Master

Data Bus

Control Lines

PMRD

PMWR

PIC32 Slave

PMCS1

PMDOUT (0)

PMDOUT (1)

PMDOUT (2)

PMDOUT (3)

PMDIN (0)

PMDIN (1)

PMDIN (2)

PMDIN (3)

PMD<7:0> Write

Address

Pointer

Read

Address

Pointer

/* Example configuration for Buffered Slave mode */

IEC1CLR = 0x0004 // Disable PMP interrupt in case it is already enabled

PMCON = 0x0000 // Stop and configure PMCON register for Buffered mode

PMMODE = 0x1800 // Configure PMMODE register

IPC7SET = 0x001C; // Set priority level = 7 and

IPC7SET = 0x0003; // Set subpriority level = 3

// Could have also done this in single operation by

// by assigning IPC7SET = 0x001F

IFS1CLR = 0x0004; // Clear the PMP interrupt status flag 

IEC1SET = 0x0004; // Enable PMP interrupts

PMCONSET = 0x8000; // Enable the PMP module

Section 13. Parallel Master Port (PMP)

13.4.3.1 INITIALIZATION STEPS

The following Addressable Buffered Slave mode initialization steps properly prepares the PMP

port for communicating with an external device.

1. Clear the ON control bit (PMCON<15> = 0) to disable the PMP module.

2. Select the Legacy mode with MODE<1:0> bits (PMMODE<9:8) = 00.

3. Select the polarity of the Chip Select CS1P (PMCON<3>).

4. Select the polarity of the control pins WRSP (PMCON<1>) and RDSP (PMCON<0>).

5. If interrupts are used:

a) Clear interrupt flag bit PMPIF (IFS1<2>).

b) Configure interrupt priority and subpriority levels in IPC7.

c) Set interrupt enable bit PMPIE (IEC1<2>).

6. Set the ON control bit to ‘1’ to enable the PMP module.

Example 13-5: Addressable Parallel Slave Port Initialization (Example Code)

13.4.3.2 READ FROM SLAVE PORT

When Chip Select is active and a read strobe occurs, the data from one of the four output 8-bit

buffers is presented onto PMD<7:0>. The byte selected to be read depends on the 2-bit address

placed on PMA<1:0>. Table 13-9 shows the corresponding output registers and their associated

address. When an output buffer is read, the corresponding OBnE bit is set. The OBE flag bit is

set when all the buffers are empty. If any buffer is already empty, OBnE = 1, the next read to that

buffer will generate an OBUF event. See the timing diagrams in 13.4.4 “Slave Mode Read and

Write Timing Diagrams”.

13.4.3.3 WRITE TO SLAVE PORT

When Chip Select is active and a write strobe occurs (PMCS = = 1 and PMWR 1), the data from

PMD<7:0> is captured into one of the four input buffer bytes. The byte selected to be written

depends on the 2-bit address placed on ADDR<1:0>. Table 13-9 shows the corresponding input

registers and their associated address.

When an input buffer is written, the corresponding IBnF bit is set. The IBF flag bit is set when all

the buffers are written. If any buffer is already written, IBnF = 1, the next write strobe to that buffer

will generate an IBOV event, and the byte will be discarded. See the timing diagrams in

13.4.4 “Slave Mode Read and Write Timing Diagrams”.

13.4.3.4 ADDRESSABLE BUFFERED MODE INTERRUPT OPERATION

In Addressable Slave mode, the module can be configured to generate an interrupt on every read

or write strobe, IRQM<1:0> bits (PMMODE<14:13>) = 01. It can also be configured to generate

an interrupt on any read from Read Buffer 3 or write to Write Buffer 3, IRQM<1:0> = 10; in other

words, an interrupt will occur whenever a read or write occurs when PMA<1:0> is ‘11’.

If using interrupts, the user application vectors to an Interrupt Service Routine (ISR) where the

IBF and OBE Status bits can be examined to determine if the buffer is full or empty. If not using

interrupts, the user application should wait for PMPIF to be set before polling the IBF and OBE

Status bits to determine if the buffer is full or empty.

/* Example configuration for Addressable Slave mode */

IEC1CLR = 0x0004 // Disable PMP interrupt in case it is already enabled

PMCON = 0x0000 // Stop and configure PMCON register for Address mode

PMMODE = 0x0100 // Configure PMMODE register

IPC7SET = 0x001C; // Set priority level = 7 and

IPC7SET = 0x0003; // Set subpriority level = 3

// Could have also done this in single operation

// by assigning IPC7SET = 0x001F

IFS1CLR = 0x0004; // Clear the PMP interrupt status flag 

IEC1SET = 0x0004; // Enable PMP interrupts

PMCONSET = 0x8000; // Enable the PMP module

Section 13. Parallel Master Port (PMP)

Figure 13-35: Parallel Slave Port Read Operation

Figure 13-36: Parallel Slave Port Read Operation – Buffer Empty, Underflow Condition

PMCS1

PMWR

PMRD

OB0E

PMPIF

PMD<7:0> Data to Master

Same Data

PMDOUT Data

User Writes New Data to PMDIN

Buffer Empty, Ready to Write New Data

OBUF

Note: Control signal polarity are configurable and are shown active-high in this example.

2-3 T

PBCLK

Cycles

New Data

PMCS1

PMWR

PMRD

OB0E

PMPIF

PMD<7:0> Old Data to Master

PMDOUT Old Data

User Writes PMDIN

Buffer Underflow Condition

OBUF

Note: Control signal polarity are configurable and are shown active-high in this example.

2-3 T

PBCLK

Cycles

User Clears OBUF

New Data

PIC32 Family Reference Manual

13.5 INTERRUPTS

The Parallel Master Port module can generate an interrupt, depending on the selected operating

mode.

• PMP (Master) mode:

Interrupt on every completed read or write operation.

• PSP (Legacy Slave) mode:

Interrupt on every read and write byte

• PSP (Buffered Slave) mode:

- Interrupt on every read and write byte

- Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>)

• EPSP (Enhanced Addressable Slave) mode:

- Interrupt on every read and write byte

- Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>), PMA<1:0> = .11

The PMPIF bit must be cleared in software.

The PMP module is enabled as a source of interrupt through the PMP Interrupt Enable bit,

PMPIE. The Interrupt Priority bits (PMPIP<2:0>) and Interrupt Subpriority bits (PMPIS<1:0>)

must also be configured. For more details, refer to Section 8. “Interrupts” (DS60001108).

13.5.1 Interrupt Configuration

The PMP module has a dedicated interrupt flag bit, PMPIF, and a corresponding interrupt

enable/mask bit, PMPIE. These bits are used to determine the source of an interrupt and to

enable or disable an individual interrupt source.

The PMPIE bit is used to define the behavior of the Vector Interrupt Controller or Interrupt

Controller when the PMPIF bit is set. When the PMPIE bit is clear, the Interrupt Controller module

does not generate a CPU interrupt for the event. If the PMPIE bit is set, the Interrupt Controller

module will generate an interrupt to the CPU when the PMPIF bit is set (subject to the priority

and subpriority as outlined below).

It is the responsibility of the user’s software routine that services a particular interrupt to clear the

appropriate Interrupt Flag bit before the service routine is complete.

The priority of PMP module can be set with the PMPIP<2:0> bits. This priority defines the priority

group to which the interrupt source will be assigned. The priority groups range from a value of 7,

the highest priority, to a value of 0, which does not generate an interrupt. An interrupt being

serviced will be preempted by an interrupt in a higher priority group.

The subpriority bits allow setting the priority of a interrupt source within a priority group. The

values of the subpriority, PMPIS<1:0>, range from 3, the highest priority, to 0 the lowest priority.

An interrupt with the same priority group but having a higher subpriority value will preempt a

lower subpriority interrupt that is in progress.

The priority group and subpriority bits allow more than one interrupt source to share the same

priority and subpriority. If simultaneous interrupts occur in this configuration, the natural order of

the interrupt sources within a priority/subgroup pair determine the interrupt generated. The

natural priority is based on the vector numbers of the interrupt sources. The lower the vector

number the higher the natural priority of the interrupt. Any interrupts that were overridden by

natural order will then generate their respective interrupts based on priority, subpriority and

natural order after the interrupt flag for the current interrupt is cleared.

After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt.

The vector number for the interrupt is the same as the natural order number. The CPU will then

begin executing code at the vector address. The user’s code at this vector address should

perform any application specific operations and clear the PMPIF interrupt flag, and then exit. For

more information on interrupts and the vector addresses, refer to Section 8. “Interrupts”

(DS60001108).

PIC32 Family Reference Manual

13.9 PARALLEL SLAVE PORT APPLICATION

Figure 13-46 illustrates the connections to a master peripheral in 8-bit Data mode as a slave,

MODE<1:0> bits (PMMODE<9:8>) = 00. The microcontroller’s PMP is controlled by a Chip

Select (PMCS1).

Figure 13-46: Legacy Mode Slave Port

13.10 DIRECT MEMORY ACCESS SUPPORT

Direct Memory Access (DMA) reads from and writes to the PMDIN register when the PMP

module is configured for Master mode. The following steps are to be performed for using DMA.

1. Set the CHSIRQ<7:0> bits (DCHxECON<15:8>) to the PMP IRQ number.

2. Configure the PMP module for the required mode (Master or Legacy Slave).

3. Set the IRQM<1:0> bits (PMMODE<14:13>) = 01 to generate the PMP interrupts on every

byte.

D<7:0>

PMRD

PMWR

PIC32

PMCS1

PMD<7:0>

MASTER

Note: Legacy Slave mode: MODE<1:0> bits (PMMODE<9:8>) = 00.

Data Bus

Control Lines

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	PIC32MX330F064L

Heb je hulp nodig?

Als je hulp nodig hebt met Microchip PIC32MX330F064L stel dan hieronder een vraag en andere gebruikers zullen je antwoorden

Uw naam*

Jouw email*

Schrijf hier uw vraag

Handleiding Niet gecategoriseerd Microchip

Microchip MCP4902 Handleiding

11 Maart 2025

Microchip ATA6574 Handleiding

11 Maart 2025

Microchip mcp42010 Handleiding

25 Februari 2025

Microchip MCP47CVB04 Handleiding

25 Februari 2025

Microchip WFI32E04UC Handleiding

25 Februari 2025

Microchip mcp42050 Handleiding

25 Februari 2025

Microchip MCP47CVB14 Handleiding

25 Februari 2025

Microchip MCP48CMB08 Handleiding

25 Februari 2025

Microchip MCP47CVB28 Handleiding

25 Februari 2025

Microchip MCP48FVB18 Handleiding

25 Februari 2025

Handleiding Niet gecategoriseerd

Nieuwste handleidingen voor Niet gecategoriseerd

Tunturi Signature T80 Handleiding

17 Maart 2025

Klein Tools 34056 Handleiding

17 Maart 2025

StarTech.com 1P1FFC-USB-SERIAL Handleiding

17 Maart 2025

StarTech.com P2ADD121D-KVM-SWITCH Handleiding

17 Maart 2025

Strong LEAP-NEVE Handleiding

17 Maart 2025

Allibert Oslo 826172 Handleiding

17 Maart 2025

Allibert Oslo 826174 Handleiding

17 Maart 2025

Foppapedretti Stendipiu Handleiding

17 Maart 2025

Tascam Audio File Manager Handleiding

17 Maart 2025

Vonroc S_PT501XX Handleiding

17 Maart 2025