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© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-1
Section 13. Parallel Master Port (PMP)
HIGHLIGHTS
This section of the manual contains the following major topics:
13.1 Introduction .................................................................................................................. 13-2
13.2 Control Registers ......................................................................................................... 13-3
13.3 Master Modes of Operation ....................................................................................... 13-18
13.4 Slave Modes of Operation ......................................................................................... 13-41
13.5 Interrupts.................................................................................................................... 13-48
13.6 Operation in Power-Saving and Debug Modes.......................................................... 13-50
13.7 Effects of Various Resets........................................................................................... 13-50
13.8 Parallel Master Port Applications............................................................................... 13-51
13.9 Parallel Slave Port Application...................................................................................13-56
13.10 Direct Memory Access Support ................................................................................. 13-56
13.11 I/O Pin Control ........................................................................................................... 13-57
13.12 Related Application Notes..........................................................................................13-60
13.13 Revision History......................................................................................................... 13-61
PIC32 Family Reference Manual
DS60001128H-page 13-2 © 2007-2015 Microchip Technology Inc.
13.1 INTRODUCTION
The Parallel Master Port (PMP) is a parallel 8-bit/16-bit I/O module specifically designed to
communicate with a wide variety of parallel devices such as communications peripherals, LCDs,
external memory devices and microcontrollers. Because the interfaces to parallel peripherals
vary significantly, the PMP module is highly configurable. The key features of the PMP module
include:
Up to 24 programmable address lines
Up to two Chip Select lines with two alternate Chip Selects for extended addressing
Programmable strobe options:
- Individual read and write strobes or Read/write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Legacy parallel slave port support
Enhanced parallel slave support:
- Address support
- 4 bytes deep, auto-incrementing buffer
Schmitt Trigger or TTL input buffers
Programmable Wait states
Freeze option for in-circuit debugging
Separate configurable read/write registers or dual buffers for Master mode (not available on
all devices)
Figure 13-1: PMP Module Pinout and Connections to External Devices
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “Parallel Master Port (PMP)”
chapter in the current device data sheet to check whether this document supports
the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
PMA0
PMA14
PMA15
PMRD
PMWR
PMENB
PMRD/PMWR
PMCS1
PMA1
PMA<13:2>
(2)
PMALL
PMALH
PMCS2
EEPROM
Address Bus
Data Bus
Control Lines
LCD FIFO
Microcontroller
8-bit/16-bit data (with or without multiplexed addressing)
Up to 24-bit address
buffer
PMD<15:8>
(1)
PMA<7:0>
PMA<15:8>
PMD<7:0>
Parallel Master Port
PIC32
Note 1: The PMD<15:8> data pins are only available on PIC32 devices with 100 or more pins.
2: 24-bit addressing is available in Extended mode.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-3
Section 13. Parallel Master Port (PMP)
13.2 CONTROL REGISTERS
The PMP module uses these Special Function Registers (SFRs):
PMCON: Parallel Port Control Register
This register contains the bits that control much of the module’s basic functionality. A key bit
is the ON control bit, which is used to Reset, enable or disable the module.
When the module is disabled, all of the associated I/O pins revert to their designated I/O
function. In addition, any read or write operations active or pending are stopped, and the
BUSY bit is cleared. The data within the module registers is retained, including the data in
PMSTAT register. Therefore, the module could be disabled after a reception, and the last
received data and status would still be available for processing.
When the module is enabled, all buffer control logic is reset, along with PMSTAT.
All other bits in PMCON control address multiplexing enable various port control signals, and
select control signal polarity. These are discussed in detail in
13.3.1 “Parallel Master Port
Configuration Options”.
PMMODE: Parallel Port Mode Register
This register contains bits that control the operational modes of the module. Master/Slave
mode selection and configuration options for both modes, are set by this register. It also
contains the universal status flag, BUSY, which is used in master modes to indicate that an
operation by the module is in progress.
Details on the use of the PMMODE bits to configure PMP operation are provided in
13.3 “Master Modes of Operation” and 13.4 “Slave Modes of Operation”.
PMADDR: Parallel Port Address Register
This register contains the address to which outgoing data is to be written, as well as the Chip
Select control bits for addressing parallel slave devices. The PMADDR register is only used
in Single Buffer Master modes.
PMDOUT: Parallel Port Data Output Register
This register is used only in Slave mode for buffered output data.
PMDIN: Parallel Port Data Input Register
This register is used by the PMP module in both Master and Slave modes.
In Slave mode, this register is used to hold data that is asynchronously clocked in. Its
operation is described in 13.4.2 “Buffered Parallel Slave Port Mode”.
In Single Buffer Master modes, PMDIN is the holding register for both incoming and outgoing
data. Its operation in Master mode is described in 13.3.3 “Read Operation” and
13.3.4 “Write Operation”.
In Dual Buffer Master modes, the PMDIN is the holding register for the outgoing data. A
separate PMRDIN register holds the incoming data.
PMAEN: Parallel Port Pin Enable Register
This register controls the operation of address and Chip Select pins associated with the PMP
module. Setting these bits allocates the corresponding microcontroller pins to the PMP
module; clearing the bits allocates the pins to port I/O or other peripheral modules
associated with the pin.
PMSTAT: Parallel Port Status Register (Slave modes only)
This register contains status bits associated with buffered operating modes when the port is
functioning as a slave port. This includes overflow, underflow and full flag bit.
These flags are discussed in detail in 13.4.2 “Buffered Parallel Slave Port Mode”.
PMWADDR: Parallel Port Write Address Register
This register contains the address to which outgoing data is to be written, as well as the Chip
Select control bits for addressing parallel slave devices. The PMWADDR register is only
used in Dual Buffer Master modes.
PIC32 Family Reference Manual
DS60001128H-page 13-4 © 2007-2015 Microchip Technology Inc.
PMRADDR: Parallel Port Read Address Register
This register contains the address to which incoming data is to be read, as well as the Chip
Select control bits for addressing parallel slave devices. The PMRADDR register is only
used in Dual Buffer Master modes.
PMRDIN: Parallel Port Read Input Data Register
In Dual Buffer Master modes, PMRDIN is the holding register for the incoming data. Its
operation in Master mode is described in 13.3.3 “Read Operation” and 13.3.4 “Write
Operation”.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-5
Table 13-1 provides a brief summary of all PMP-module-related registers. Corresponding registers
detailed description of each bit.
Table 13-1: PMP Special Function Register Summary
Register
Name
(1)
Bit
Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 27/11 Bit 25/9 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4Bit 28/12 Bit 26/10 Bit 24/8 Bit 19
PMCON 31:16 — — — RDSTART
(2)
— — —
15:0 ON SIDL CSF<1:0> CS2P CS1ADRMUX<1:0> PMPTTL PTWREN PTRDEN ALP
PMMODE 31:16 — — — — —
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0>
PMADDR 31:16 — — — CS2A CS1A A
ADDR23 ADDR22
15:0
CS2 CS1
ADDR<13:0>
ADDR15
(2)
ADDR14
(2)
PMDOUT 31:16 DATAOUT<31:16>
15:0 DATAOUT<15:0>
PMDIN 31:16 DATAIN<31:16>
15:0 DATAIN<15:0>
PMAEN 31:16 — — — PTEN<23:22> P
15:0 PTEN<15:0>
PMSTAT 31:16 — — — — —
15:0 IBF IBOV IB1F IB3F IB2F IB0F OBE OBUF OB
PMWADDR
(2)
31:16 — — — WCS2A WCS1A W
WADDR23 WADDR22
15:0
WCS2 WCS1
— — — — — —
WADDR15 WADDR14
WADDR<13:0>
PMRADDR
(2)
31:16 — — — RCS2A RCS1A R
RADDR23 RADDR22
15:0
RCS2 RCS1
— — — — — —
RADDR15 RADDR14
RADDR<13:0>
PMRDIN
(2)
31:16 31:16 — — — — — — — —
15:0 15:0 RDATAIN<15:0>
Legend: — = unimplemented, read as ‘0’.
Note 1: With the exception of the PMSTAT register, these registers have an associated Clear, Set, and Invert registers at an offset of 0x4, 0x8, and 0xC bytes, respectiv
with CLR, Set, or INV appended to the register name (e.g., PMCONCLR). Writing a 1’ to any bit position in these registers will Clear, Set, and Invert valid bits in t
register should be ignored.
2: This bit or register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific device data sheet to determine availability.
PIC32 Family Reference Manual
DS60001128H-page 13-6 © 2007-2015 Microchip Technology Inc.
Register 13-1: PMCON: Parallel Port Control Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0U-0 U-0 U-0 U-0 U-0 U-0
— — —
23:16
R/W-0, HC
U-0 U-0 U-0 U-0 U-0
R/W-0
U-0
RDSTART
(3)
— — — DUALBUF
(3)
EXADDR
(3)
15:8
R/W-0 R/W-0U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ON
(1)
— SIDL
ADRMUX<1:0>
PMPTTL PTWREN PTRDEN
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
CSF<1:0>
(2)
ALP
(2)
CS2P
(2)
CS1P
(2)
WRSP RDSP
Legend: HC = Hardware cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23 RDSTART: Start a Read on the PMP Bus bit
(3)
1 = Start a read cycle on the PMP bus
0 = No effect
This bit is cleared by hardware at the end of the read cycle when the BUSY bit (PMMODE<15>) = 0.
bit 22-18 Unimplemented: Read as ‘0’
bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit
(3)
This bit is only valid in Master mode.
1 = PMP uses separate registers for reads and writes
Reads: PMRADDR and PMRDIN
Writes: PMRWADDR and PMDOUT
0 = PMP uses legacy registers for reads and writes
Reads/Writes: PMADDR and PMRDIN
bit 16 EXADDR: Parallel Master Port Extended 24-bit Addressing (Valid in Demultiplexed Master Mode Only)
(3)
1 = PMP 24 bit addressing is enabled
0 = PMP 24 bit addressing is disabled
bit 15 ON: Parallel Master Port Enable bit
(1)
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 14 Unimplemented: Write ‘0’; ignore read
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD<15:0> pins
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when its corresponding pin is used as an address line.
3: This bit is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific
device data sheet to determine availability.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-7
Section 13. Parallel Master Port (PMP)
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits
(2)
11 = Reserved
10 = PMCS2/PMCS2A and PMCS1/PMCS1A function as Chip Select
01 = PMCS2/PMCS2A functions as Chip Select, PMCS1/PMCS1A functions as address bit
00 = PMCS2/PMCS2A and PMCS1/PMCS1A function as address bits
bit 5 ALP: Address Latch Polarity bit
(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 CS2P: Chip Select 2/2A Polarity bit
(2)
1 = Active-high
0 = Active-low
Note: PMCS1A and PMCS2A are only applicable when EXADDR=1
bit 3 CS1P: Chip Select 1/1A Polarity bit
(2)
1 = Active-high
0 = Active-low
bit 2 Unimplemented: Write ‘0’; ignore read
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 MODE <1:0> (PMMODE<9:8> = , , ):00 01 10
1 = Write strobe active-high (PMWR)
0 = )Write strobe active-low (PMWR
For Master mode 1 MODE <1:0> (PMMODE<9:8> = ):11
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 MODE <1:0> (PMMODE<9:8> = , , ):00 01 10
1 = Read strobe active-high (PMRD)
0 = )Read strobe active-low (PMRD
For Master mode 1 MODE <1:0> (PMMODE<9:8> = ):11
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Register 13-1: PMCON: Parallel Port Control Register (Continued)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when its corresponding pin is used as an address line.
3: This bit is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the specific
device data sheet to determine availability.
PIC32 Family Reference Manual
DS60001128H-page 13-8 © 2007-2015 Microchip Technology Inc.
Register 13-2: PMMODE: Parallel Port Mode Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
15:8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAITB<1:0>
(1)
WAITM<3:0>
(1)
WAITE<1:0>
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Write ‘0’; ignore read
bit 15 BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode),
or on a read or write operation when PMA<1:0> = 11 (Addressable Slave mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 00 = Slave mode read and write buffers auto-increment MODE<1:0> (PMMODE<9:8> = only)
10 = Decrement ADDR<15:0> by 1 every read/write cycle
(2,4)
01 = Increment ADDR<15:0> by 1 every read/write cycle
(2,4)
00 = No increment or decrement of address
bit 10 MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>
(3)
)
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>
(3)
)
01 = Enhanced Slave mode, control signals (
PMRD
,
PMWR
,
PMCS
, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits
(1)
11 = Data wait of 4 T
PB
; multiplexed address phase of 4 T
PB
10 = Data wait of 3 T
PB
; multiplexed address phase of 3 T
PB
01 = Data wait of 2 T
PB
; multiplexed address phase of 2 T
PB
00 = Data wait of 1 T
PB
; multiplexed address phase of 1 T
PB
(default)
Note 1: When WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 T
PBCLK
cycle for a
write operation; WAITB = 1 T
PBCLK
cycle, WAITE = 0 T
PBCLK
cycles for a read operation.
2: Address bit A15/A23 and A14/A22 are not subject to auto-increment/decrement if configured as Chip
Select CS2/CS2A and CS1/CS1A.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-9
Section 13. Parallel Master Port (PMP)
bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits
(1)
1111 = Wait of 16 T
PB
0001 = Wait of 2 T
PB
0000 = Wait of 1 T
PB
(default)
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits
(1)
11 = Wait of 4 T
PB
10 = Wait of 3 T
PB
01 = Wait of 2 T
PB
00 = Wait of 1 T
PB
(default)
For read operations:
11 = Wait of 3 T
PB
10 = Wait of 2 T
PB
01 = Wait of 1 T
PB
00 = Wait of 0 T
PB
(default)
Register 13-2: PMMODE: Parallel Port Mode Register (Continued)
Note 1: When WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 T
PBCLK
cycle for a
write operation; WAITB = 1 T
PBCLK
cycle, WAITE = 0 T
PBCLK
cycles for a read operation.
2: Address bit A15/A23 and A14/A22 are not subject to auto-increment/decrement if configured as Chip
Select CS2/CS2A and CS1/CS1A.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width.
PIC32 Family Reference Manual
DS60001128H-page 13-10 © 2007-2015 Microchip Technology Inc.
Register 13-3: PMADDR: Parallel Port Address Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0U-0 U-0 U-0 U-0
— — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
CS2A
(2)
CS1A
(2)
ADDR<21:16>
ADDR23
(2)
ADDR22
(2)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
CS2
(1)
CS1
(1)
ADDR<13:8>
ADDR15
(1)
ADDR14
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0
ADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Read asUnimplemented: 0
bit 23 CS2A: Chip Select 2 bit
(2)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (ADDR23 function is selected)
bit 23 ADDR23: Target Address bit 23
(2)
bit 22 CS1A: Chip Select 1 bit
(2)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (ADDR22 function is selected)
bit 22 ADDR22: Target Address bit 22
(2)
bit 21-16 ADDR<21:16> Address bits
bit 15 CS2: Chip Select 2 bit
(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (ADDR15 function is selected)
bit 15 ADDR15: Target Address bit 15
(1)
bit 14 CS1: Chip Select 1 bit
(1)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (ADDR14 function is selected)
bit 14 ADDR14: Target Address bit 14
(1)
bit 13-0 ADDR<13:0>: Address bits
Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 0.
2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 1.
Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target
addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the
PMRADDR register for Read operations and the PMWADDR register for Write operations.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-11
Section 13. Parallel Master Port (PMP)
Register 13-4: PMDOUT: Parallel Port Data Output Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAOUT<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAOUT<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAOUT<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAOUT<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DATAOUT<31:0>: Output Data Port bits for 8-bit write operations in Slave mode
PIC32 Family Reference Manual
DS60001128H-page 13-12 © 2007-2015 Microchip Technology Inc.
Register 13-5: PMDIN: Parallel Port Data Input Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAIN<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAIN<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAIN<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DATAIN<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 DATAIN<31:0>: Input/Output Data Port bits for 8-bit or 16-bit read/write operations in Master mode Input
Data Port for 8-bit read operations in Slave mode.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-13
Section 13. Parallel Master Port (PMP)
Register 13-6: PMAEN: Parallel Port Pin Enable Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
PTEN<23:22> PTEN<21:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN<15:14> PTEN<13:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN<7:2> PTEN<1:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
31-24 Unimplemented: Write ‘0’; ignore read
bit 23-22 PTEN<23:22>: PMCSx Strobe Enable bits
1 = PMA23 and PMA22 function as either PMA<23:22> or PMCS2A and PMCS1A
(1)
0 = PMA23 and PMA22 function as port I/O
bit 21-16 PTEN<21:16>: PMP Address Port Enable bits
1 = PMA<21:16> function as PMP address lines
0 = PMA<21:16> function as port I/O
bit 15-14 PTEN<15:14>: PMCSx Strobe Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1
(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2 PTEN<13:2>: PMP Address Port Enable bits
1 = PMA<13:2> function as PMP address lines
0 = PMA<13:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1: The use of these pins as address or chip select lines selected by the CSF<1:0> bits (PMCON<7:6>).
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by the ADRMUX<1:0> bits in the PMCON register.
PIC32 Family Reference Manual
DS60001128H-page 13-14 © 2007-2015 Microchip Technology Inc.
Register 13-7: PMSTAT: Parallel Port Status Register (Slave modes only)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
15:8
R-0 U-0R/W-0 U-0 R-0 R-0 R-0 R-0
IBF IBOV IB3F IB2F IB1F IB0F
7:0
R-1 U-0R/W-0 U-0 R-1 R-1 R-1 R-1
OBE OBUF OB3E OB2E OB1E OB0E
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Write ‘0’; ignore read
bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = No overflow occurred
This bit is set (= 1) in hardware; can only be cleared (= 0) in software.
bit 13-12 Unimplemented: Write ‘0’; ignore read
bit 11-8 IBnF: Input Buffer n Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow occurred
This bit is set (= 1) in hardware; can only be cleared (= 0) in software.
bit 5-4 Unimplemented: Write ‘0’; ignore read
bit 3-0 OBnE: Output Buffer n Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-15
Section 13. Parallel Master Port (PMP)
Register 13-8: PMWADDR: Parallel Port Write Address Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0
— — — — — —
23:26
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
WCS2A
(2)
WCS1A
(2)
WADDR<21:16>
WADDR23
(2)
WADDR22
(2)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
WCS2
(1)
WCS1
(1)
WADDR<13:8>
WADDR15
(1)
WADDR14
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
WADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Unimplemented: Read as 0
bit 23 WCS2A: Chip Select 2 bit
(2)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (WADDR23 function is selected)
bit 23 WADDR23: Target Address bit 23
(2)
bit 22 WCS1A: Chip Select 1 bit
(2)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (WADDR22 function is selected)
bit 22 WADDR22: Target Address bit 22
(2)
bit 21-16 WADDR<21:16>: Address bits
bit 15 WCS2: Chip Select 2 bit
(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (WADDR15 function is selected)
bit 15 WADDR15: Target Address bit 15
(1)
bit 14 WCS1: Chip Select 1 bit
(1)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (WADDR14 function is selected)
bit 14 WADDR14: Target Address bit 14
(1)
bit 13-0 WADDR<13:0>: Address bits
Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 0.
2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 1.
Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1.
2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-
cific device data sheet to determine availability.
PIC32 Family Reference Manual
DS60001128H-page 13-16 © 2007-2015 Microchip Technology Inc.
Register 13-9: PMRADDR: Parallel Port Read Address Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0
— — — — — —
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
RCS2A
(2)
RCS1A
(2)
RADDR<21:16>
RADDR23
(2)
RADDR22
(2)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
RCS2
(1)
RCS1
(1)
RADDR<13:8>
RADDR15
(1)
RADDR14
(1)
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0
RADDR<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-24 Read asUnimplemented: 0
bit 23 RCS2A: Chip Select 2 bit
(2)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (RADDR23 function is selected)
bit 23 RADDR23: Target Address bit 23
(2)
bit 22 RCS1A: Chip Select 1 bit
(2)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (RADDR22 function is selected)
bit 22 RADDR22: Target Address bit 22
(2)
bit 21-16 RADDR<21:16>: Address bits
bit 15 RCS2: Chip Select 2 bit
(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive (RADDR15 function is selected)
bit 15 RADDR15: Target Address bit 15
(1)
bit 14 RCS1: Chip Select 1 bit
(1)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive (RADDR14 function is selected)
bit 14 RADDR14: Target Address bit 14
(1)
bit 13-0 RADDR<13:0>: Address bits
Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 0.
2: The use of these pins as PMA23/PMA22 or CS2A/CS1A is selected by the CSF<1:0> bits (PMCON<7:6>)
when EXADDR = 1.
Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’.
2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-
cific device data sheet to determine availability.
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-17
Section 13. Parallel Master Port (PMP)
Register 13-10: PMRDIN: Parallel Port Read Input Data Register
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0
— — — — — —
23:16
U-0 U-0 U-0 U-0 U-0U-0 U-0 U-0
— — — — — —
15:8
R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0
RDATAIN<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0
RDATAIN<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 Unimplemented: Read as 0
bit 15-0 RDATAIN<15:0>: Port Read Input Data bits
Note 1: This register is only used when the DUALBUF bit (PMCON<17>) is set to ‘1’ and exclusively for reads. If
the DUALBUF bit is ‘0’, the PMDIN register (Register 13-5) is used for reads instead of PMRDIN.
2: This register is not available on all devices. Refer to the “Parallel Master Port (PMP)” chapter in the spe-
cific device data sheet to determine availability.
PIC32 Family Reference Manual
DS60001128H-page 13-18 © 2007-2015 Microchip Technology Inc.
13.3 MASTER MODES OF OPERATION
In its master modes, the PMP module can provide a 8-bit or 16-bit data bus, up to 24 bits of
address, and all the necessary control signals to operate a variety of external parallel devices
such as memory devices, peripherals and slave microcontrollers. The PMP master modes
provide a simple interface for reading and writing data, but not executing program instructions
from external devices, such as SRAM or Flash memories.
Because there are a number of parallel devices with a variety of control methods, the PMP
module is designed for flexibility to accommodate a range of configurations. Some of these
features include:
8-bit and 16-bit data modes
Configurable address/data multiplexing
Up to two Chip Select lines
Up to 24 selectable address lines
Address auto-increment and auto-decrement
Selectable polarity on all control lines
Configurable Wait states at different stages of the read/write cycle
Separate configurable read/write registers for Master mode (not available on all devices)
13.3.1 Parallel Master Port Configuration Options
13.3.1.1 8-BIT AND 16-BIT DATA MODES
The PMP in Master mode supports data with widths of 8 and 16 bits. By default, the data width
is 8 bits wide, MODE16 bit . To select a data width of 16 bits, set (PMMODE<10>) = 0
MODE16 = 1. When configured in 8-bit Data mode, the upper 8 bits of the data bus, PMD<15:8>,
are not controlled by the PMP module and are available as general purpose I/O pins.
13.3.1.2 DUAL BUFFER MODE
Dual Buffer mode acts similar to Single Buffer mode, except the PMDIN read and write register,
which has been expanded to both the PMDOUT and PMRDIN read and write registers. This
feature was added to make PMP bus transactions more efficient when both read and write are
being performed at high rates. It saves the time to have to store either read or write data while
switching through transactions.
The PMDOUT and PMRDIN registers share the PMP bus transactions for incoming and outgoing
data. The PMWADDR and PMRADDR registers, instead of the PMADDR register, share the
PMP bus for both incoming and outgoing address line data.
13.3.1.3 CHIP SELECT
Two Chip Select lines, PMCS1 and PMCS2, are available for master modes. These lines are
multiplexed with the Most Significant bits (MSbs) of the address bus. When a pin is configured
as a Chip Select, it is not included in any address auto-increment/decrement. It is possible to
enable both PMCS2 and PMCS1 as Chip Selects, or enable only PMCS2 as a Chip Select,
allowing PMCS1 to function strictly as an address line. It is not possible to enable PMCS1 alone.
If extended addressing is used, then PMCS1A and PMCS2A are used as the chip selects.The
Chip Select signals are configured using the Chip Select Function bits CSF<1:0>
(PMCON<7:6>).
Note: This mode is not available on all devices. Refer to the “Parallel Master Port
(PMP)” chapter in the specific device data sheet to determine availability.
Table 13-2: Chip Select Control
CSF<1:0> Function
10 PMCS2, PMCS1 = Enabled
01 PMCS2 = Enabled, PMCS1 = Disabled
00 PMCS2 = Disabled, PMCS1 = Disabled
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-19
Section 13. Parallel Master Port (PMP)
13.3.1.4 PORT PIN CONTROL
There are several bits available to configure the presence or absence of control and address
signals in the module. These bits are PTWREN (PMCON<9>), PTRDEN (PMCON<8>) and
PTEN<23> (PMAEN<23:0>). They provide the ability to conserve pins for other functions and
allow flexibility to control the external address. When any one of these bits is set, the associated
function is present on its associated pin; when clear, the associated pin reverts to its defined I/O
port function.
Setting a PTEN bit will enable the associated pin as an address pin and drive the corresponding
data contained in the PMADDR register. Clearing any PTEN bit will force the pin to revert to its
original I/O function.
For the pins configured as Chip Select (PMCS1/1A or PMCS2/2A) with the corresponding PTEN
bit set, Chip Select pins drive inactive data when a read or write operation is not being performed.
The PTEN0 and PTEN1 bits also control the PMALL and PMALH signals. When multiplexing is
used, the associated address latch signals should be enabled. For I/O pin configuration, see
13.11 “I/O Pin Control”.
13.3.1.5 READ/WRITE CONTROL
The PMP module supports two distinct read/write signaling methods. In Master mode 1, read and
write strobe are combined into a single control line, PMRD/PMWR; a second control line,
PMENB, determines when a read or write action is to be taken. In Master mode 2, read and write
strobes (PMRD and PMWR) are supplied on separate pins.
13.3.1.6 CONTROL LINE POLARITY
All control signals (PMRD, PMWR, PMENB, PMALL, PMALH, PMCS1/1A and PMCS2/2A) can
be individually configured for either positive or negative polarity. Configuration is controlled by
separate bits in the PMCON register, as shown in Table 13-3.
13.3.1.7 AUTO-INCREMENT/DECREMENT
While the PMP module is operating in one of the master modes, the INCM<1:0> bits
(PMMODE<12:11>) control the behavior of the address value. The address in the PMADDR
register can be made to automatically increment or decrement by 1, regardless of the transfer
data width, after each read and write operation is completed, and the BUSY bit (PMMODE<15>)
goes to ‘0.
Table 13-3: Pin Polarity Configuration
Control Pin PMCON Control Bit Active-High Select Active-Low Select
PMRD RDSP 1 0
PMWR WRSP 1 0
PMALL ALP 1 0
PMALH ALP 1 0
PMCS1/1A CS1P 1 0
PMCS2/2A CS2P 1 0
Note: The polarity of control signals that share the same output pin (for example, PMWR
and PMENB) are controlled by the same bit; the configuration depends on which
Master Port mode is being used.
PIC32 Family Reference Manual
DS60001128H-page 13-20 © 2007-2015 Microchip Technology Inc.
.
If the Chip Select signals are disabled and configured as address bits, the bits will participate in
the increment and decrement operations; otherwise, CS2/2A and CS1/1A bit values will be
unaffected.
13.3.1.8 WAIT STATES
In Master mode, the user can control the duration of the read, write and address cycles by
configuring the module Wait states. One Wait state period is equivalent to one peripheral bus
clock cycle, T
PBCLK
. Figure 13-2 is an example of a Master mode 2 Read operation using Wait
states.
Figure 13-2: Read Operation, Wait States Enabled
Wait states can be added to the beginning, middle and end of any read or write cycle using the
corresponding WAITB, WAITM and WAITE bits in the PMMODE register.
The WAITB<1:0> bits (PMMODE<7:6>) define the number of wait cycles for the data setup prior
to the PMRD/PMWR strobe in Mode 10, or prior to the PMENB strobe in Mode 11. When
multiplexing the address and data bus, ADRMUX<1:0> bits (PMCON<12:11>) = 01 10, or 11,
WAITB defines the number of wait cycles for which the addressing period is extended.
The WAITM<3:0> bits (PMMODE<5:2>) define the number of wait cycles for the PMRD/PMWR
strobe in Mode 10, or for the PMENB strobe in Mode 11. When this Wait state setting is ‘0000’,
WAITB and WAITE are ignored. The number of Wait states for the data setup time (WAITB)
defaults to one, while the number of Wait states for data hold time (WAITE) defaults to one during
a write operation and zero during a read operation.
The WAITE<1:0> bits (PMMODE<1:0>) define the number of wait cycles for the data hold time
after the PMRD/PMWR strobe in Mode 10, or after the PMENB strobe in Mode 11.
13.3.1.9 ADDRESS MULTIPLEXING
Address multiplexing allows some or all address line signals to be generated from the data bus
during the address cycle of a read/write operation. This can be a useful option for address lines
PMA<15:0> needed as general purpose I/O pins. The user application can select to multiplex the
Table 13-4: Address INC/DEC Control
INCM<1:0> Function
10 Decrement every R/W cycle
01 Increment every R/W cycle
00 No Increment – No Decrement
PMCS2/PMCS1
TPB TPB TPB TPB TPB TPB TPB
TPB
Legend:
B = WAITB<1:0> = 01 (2 Wait states)
M = WAITM<3:0> = 0010 (3 Wait states)
E = WAITE<1:0> = 01 (1 Wait state)
Note: If WAITM<3:0> = 0000, M is forced to 1 T
PBCLK
, WAITB is ignored (B forced
to 1 T
PBCLK
), and WAITE is ignored (E forced to 0 T
PBCLK
).
B
M
E
PMWR
PMRD
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-21
Section 13. Parallel Master Port (PMP)
lower 8 data bits, upper 8 data bits or full 16 data bits. These multiplexing modes are available in
both Master mode 1 and 2. For Multiplexing mode timing diagrams, see
13.3.8 “Master Mode
Timing”.
13.3.1.9.1 Demultiplexed Mode
Demultiplexed mode is selected by configuring the ADRMUX<1:0> bits (PMCON<12:11>) = 00.
In this mode, address bits are presented on pins PMA<15:0>.
When PMCS2 is enabled, address pin PMA15 is not available. When PMCS1 is enabled,
address pin PMA14 is not available. In 16-bit Data mode, data bits are presented on pins
PMD<15:0>. In 8-bit Data mode, data bits are presented on pins PMD<7:0>.
Figure 13-3: Demultiplexed Addressing Mode
Figure 13-4: Demultiplexed Addressing Example
Table 13-5: Address Multiplex Configurations
ADRMUX<1:0> Address/Data Multiplex Modes
11 Fully multiplexed (16 data pins PMD<15:0>)
10 Fully multiplexed (lower eight data pins PMD<7:0>)
01 Partially multiplexed (lower eight data pins PMD<7:0>)
00 Demultiplexed
Address Bus
Data Bus
Control Lines
PMRD
PMWR
PMD<7:0>
PMA14/PMCS1
PMA<13:0>
PMA15/PMCS2
PIC32
PMD<15:8>
ADRMUX<1:0> = 00
Note 1: Address pin PMA<15> is not available if PMCS2 is enabled.
Address pin PMA<14> is not available if PMCS1 is enabled.
See Note 1
PMA<14:0>
D<15:0>
A<14:0>
D<15:0>
A<14:0>
PMRD
PMWR
OE WR
CE
PIC32
PMCS2
PMD<15:0>
32K x 16-bit Device
Address Bus
Data Bus
Control Lines
Note:
Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.
16-bit data width: MODE16 bit (PMMODE<10>) = 1.
Partial Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 00.
Extra Addressing: EXADDR bit = 0.
PIC32 Family Reference Manual
DS60001128H-page 13-22 © 2007-2015 Microchip Technology Inc.
13.3.1.9.2 Partially Multiplexed Mode
Partially Multiplexed mode (8-bit data pins) is available in both 8-bit and 16-bit data bus
configurations and is selected by setting the ADRMUX<1:0> bits (PMCON<12:11>) = 01. In this
mode, the lower eight address bits are multiplexed with the lower eight data bus pins, PMD<7:0>.
The upper eight address bits are unaffected and are presented on PMA<15:8>. In this mode,
address pins PMA<7:1> are available as general purpose I/O pins.
Address pin PMA15 is not available when PMCS2 is enabled; address pin PMA14 is not
available when PMCS1 is enabled.
Address pin PMA<0> is used as an address latch enable strobe, PMALL, during which the lower
eight bits of the address are presented on the PMD<7:0> pins. Read and write sequences are
extended by at least three peripheral bus clock cycles (T
PBCLK
)
.
If WAITM<3:0> (PMMODE<5:2>) is non-zero, the PMALL strobe will be extended by
WAITB<1:0> (PMMODE<7:6>) Wait states.
Figure 13-5: Partial Multiplexed Addressing Mode
Figure 13-6: Partial Multiplexed Addressing Example
PMRD
PMWR
PMD<7:0>
PMA14/PMCS1
PMA<13:8>
PMA0/PMALL
PMA15/PMCS2
PIC32
Address Bus
Multiplexed Address/Data Bus
Data Bus
Control Lines
PMD<15:8>
ADRMUX<1:0> =
01
Note 1: Address pin PMA<15> is not available if PMCS2 is enabled.
Address pin PMA<14> is not available if PMCS1 is enabled.
See Note 1
PMA<14:8>
D<7:0> 373 A<14:0>
D<15:0>
A<7:0>
PMRD
PMWR
OE WR
CE
PIC32
PMCS2
PMALL
A<14:8>
PMD<15:0>
32K x 16-bit Device
D<15:0>
Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.
16-bit data width: MODE16 bit (PMMODE<10>) = 1.
Partial Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 01.
The 373 shown in the diagram represents a generic 74XX family 373 latch.
Address Bus
Data Bus
Control Lines
© 2007-2015 Microchip Technology Inc. DS60001128H-page 13-23
Section 13. Parallel Master Port (PMP)
13.3.1.9.3 Fully Multiplexed Mode (8-bit Data Pins)
Fully Multiplexed mode (8-bit data pins) is available in both 8-bit and 16-bit data bus
configurations and is selected by setting the ADRMUX<1:0> bits (PMCON<12:11>) = 10. In this
mode, the entire 16 bits of the address are multiplexed with the lower eight data bus pins,
PMD<7:0>. In this mode, PMA<13:2> pins are available as general purpose I/O pins.
If PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding
address bit, PMADDR<15> or PMADDR<14> is automatically forced to 0’.
Address pins PMA<0> and PMA<1> are used as an address latch enable strobes, PMALL and
PMALH, respectively. During the first cycle, the lower eight address bits are presented on the
PMD<7:0> pins with the PMALL strobe active. During the second cycle, the upper eight address
bits are presented on the PMD<7:0> pins with the PMALH strobe active. The read and write
sequences are extended by at least six peripheral bus clock cycles (T
PBCLK
)
.
If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended
by WAITB<1:0> (PMMODE<7:6>) Wait states.
Figure 13-7: Fully Multiplexed Addressing Mode (8-bit Bus)
Figure 13-8: Fully Multiplexed Address Example (8-bit Bus)
Fully Multiplexed Address/Data Bus
Control Lines
PMRD
PMWR
PMD<7:0>
PMA14/ PMCS1
PMA1/PMALH
PMA15/ PMCS2
PIC32
PMA0/PMALL
ADRMUX<1:0> =
10
Note 1: Address bit PMADDR<15> is forced to ‘0’ when PMCS2 is enabled.
Address bit PMADDR<14> is forced to ‘0’ when PMCS1 is enabled.
See Note 1
Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.
8-bit data width: MODE16 bit (PMMODE<10>) = 0.
Fully Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) = 10.
The block labeled 373 in the diagram represents a generic 74XX family 373 latch.
Address Bus
Data Bus
Control Lines
PMD<7:0>
PMALH
D<7:0>
373 A<14:0>
D<7:0>
A<7:0>
373
PMRD
PMWR
OE WR
CE
PIC32
PMCS2
PMALL
A<14:8>
32K x 8-bit Device
PIC32 Family Reference Manual
DS60001128H-page 13-24 © 2007-2015 Microchip Technology Inc.
13.3.1.9.4 Fully Multiplexed Mode (16-bit Data Pins)
Fully Multiplexed mode (16-bit data pins) is only available in the 16-bit data bus configuration and
is selected by configuring the ADRMUX<1:0> bits (PMCON<12:11>) = 11. In this mode, the
entire 16 bits of the address are multiplexed with all 16 data bus pins, PMD<15:0>.
If PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding
address bit, PMADDR<15> or PMADDR<14> is automatically forced to 0’.
Address pins PMA<0> and PMA<1> are used as an address latch enable strobes, PMALL and
PMALH, respectively, and at the same time. While the PMALL and PMALH strobes are active,
the lower eight address bits are presented on the PMD<7:0> pins and the upper eight address
bits are presented on the PMD<15:8> pins. The read and write sequences are extended by at
least 3 peripheral bus clock cycles (T
PBCLK
)
.
If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended
by WAITB<1:0> (PMMODE<7:6>) Wait states.
Figure 13-9: Fully Multiplexed Addressing Mode (16-bit Bus)
Figure 13-10: Fully Multiplexed Addressing Example (16-bit Bus)
PMRD
PMWR
PMA1/PMALH
PMA15/ PMCS2
PIC32
PMA0/PMALL
PMD<7:0>
PMD<15:8>
PMA14/ PMCS1
ADRMUX<1:0> =
11
Note 1: Address bit PMADDR<15> is forced to ‘0 when PMCS2 is enabled.
Address bit PMADDR<14> is forced to 0when PMCS1 is enabled.
Fully Multiplexed Address/Data Bus
Control Lines
See Note 1
Note: Master mode 2: MODE<1:0> bits (PMMODE<9:8>) = 10.
16-bit data width: MODE16 bit (PMMODE<10>) = 1.
Fully Multiplexed mode: ADRMUX<1:0> bits (PMCON<12:11>) =
11.
The 373 shown in the diagram represents a generic 74XX family 373 latch.
Address Bus
Data Bus
Control Lines
PMD<15:0>
PMALH
D<15:0>
373 A<14:0>
D<15:0>
A<7:0>
373
PMRD
PMWR
OE WR
CE
PIC32
PMCS2
PMALL
A<14:8>
32K x 16-bit Device
D<15:8>
D<7:0>


Product specificaties

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Categorie: Niet gecategoriseerd
Model: PIC32MX330F064L

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