Microchip PIC24FJ64GA106 Handleiding

Microchip Niet gecategoriseerd PIC24FJ64GA106

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2007-2015 Microchip Technology Inc. DS70000195G-page 1
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 I
2
C Bus Characteristics..................................................................................................... 4
3.0 Control and Status Registers ............................................................................................ 8
4.0 Enabling I
2
C Operation ................................................................................................... 18
5.0 Communicating as a Master in a Single Master Environment ........................................ 20
6.0 Communicating as a Master in a Multi-Master Environment .......................................... 34
7.0 Communicating as a Slave ............................................................................................. 37
8.0 Connection Considerations for I
2
C Bus .......................................................................... 61
9.0 Operation in Power-Saving Modes ................................................................................. 63
10.0 Peripheral Module Disable (PMDx) Registers ................................................................ 63
11.0 Effects of a Reset............................................................................................................ 63
12.0 Constant-Current Source ................................................................................................ 64
13.0 Register Maps................................................................................................................. 66
14.0 Design Tips ..................................................................................................................... 67
15.0 Related Application Notes............................................................................................... 68
16.0 Revision History .............................................................................................................. 69
Inter-Integrated Circuit (I2C)
2007-2015 Microchip Technology Inc. DS70000195G-page 3
Inter-Integrated Circuit (I
2
C)
Figure 1-1: I
2
C Block Diagram
I2CxRCV
Internal
Data Bus
SCLx
SDAx
Shift
Match Detect
Clock
Address Match
Clock
Stretching
I2CxTRN
LSB
Shift Clock
BRG
Reload
Control
T
CY
or T
CY
/2
(1)
Acknowledge
Generation
I2CxCONH
I2CxSTAT
Control Logic
Read
LSB
Write
Read
I2CxBRG
I2CxRSR
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Down Counter
I2CxCONL
Write
Read
Note 1: Refer to the specific device data sheet for the clock rate.
I2CxADD
Start and Stop
Bit Detect
Start and Stop
Bit Generation
Collision
Detect
I2CxMSK
dsPIC33/PIC24 Family Reference Manual
DS70000195G-page 4 2007-2015 Microchip Technology Inc.
2.0 I2C BUS CHARACTERISTICS
The I
2
C bus is a 2-wire serial interface. Figure 2-1 illustrates the schematic of an I
2
C connection
between a dsPIC33/PIC24 device and a 24LC256 I
2
C serial EEPROM, which is a typical
example for any I
2
C interface.
The I
2
C interface uses a comprehensive protocol to ensure reliable transmission and reception
of the data. When communicating, one device acts as the “master” and it initiates transfer on the
bus, and generates the clock signals to permit that transfer, while the other devices act as the
“slave” responding to the transfer. The clock line, SCLx, is output from the master and input to
the slave, although occasionally the slave drives the SCLx line. The data line, SDAx, may be
output and input from both the master and slave.
Because the SDAx and SCLx lines are bidirectional, the output stages of the devices driving the
SDAx and SCLx lines must have an open-drain in order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high level when no device is pulling the line down.
In the I
2
C interface protocol, each device has an address. When a master needs to initiate a data
transfer, it first transmits the address of the device that it wants to “communicate”. All of the
devices “listen” to see if this is their address. Within this address, bit 0 specifies whether the
master wants to read from or write to the slave device. The master and slave are always in
opposite modes (Transmitter or Receiver) of operation during a data transfer. That is, they
operate in either of the following two relationships:
• Master-Transmitter and Slave-Receiver
• Slave-Transmitter and Master-Receiver
In both cases, the master originates the SCLx clock signal.
Figure 2-1: Typical I
2
C Interconnection Block Diagram
Note:
SCLx and SDAx must be configured as digital.
SCLx
SDAx
dsPIC33/PIC24
SDA
SCL
V
DD
V
DD
2.2 k24LC256
(typical)

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: PIC24FJ64GA106

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