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© 2013 Microchip Technology Inc. DS70005131A-page 1
Oscillator Module
HIGHLIGHTS
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CPU Clocking.................................................................................................................... 5
3.0 Oscillator Configuration Registers .................................................................................... 6
4.0 Special Function Registers ............................................................................................... 9
5.0 Primary Oscillator (POSC).............................................................................................. 21
6.0 Internal Fast RC (FRC) Oscillator................................................................................... 25
7.0 Phase-Locked Loop (PLL) .............................................................................................. 26
8.0 Secondary Oscillator (SOSC) ......................................................................................... 31
9.0 Low-Power RC (LPRC) Oscillator................................................................................... 32
10.0 Auxiliary Oscillator .......................................................................................................... 33
11.0 Auxiliary Phase-Locked Loop (APLL) ............................................................................. 34
12.0 Auxiliary PLL (x16).......................................................................................................... 37
13.0 Fail-Safe Clock Monitor (FSCM)..................................................................................... 39
14.0 Clock Switching............................................................................................................... 40
15.0 Two-Speed Start-up ........................................................................................................ 44
16.0 Reference Clock Output.................................................................................................. 44
17.0 Linear Feedback Shift Register....................................................................................... 44
18.0 Register Maps................................................................................................................. 45
19.0 Related Application Notes............................................................................................... 46
20.0 Revision History.............................................................................................................. 47
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 2 © 2013 Microchip Technology Inc.
1.0 INTRODUCTION
The dsPIC33/PIC24 family oscillator system includes these characteristics:
External and internal oscillator sources
On-chip Phase-Locked Loop (PLL) to boost internal operating frequency on select internal
and external oscillator sources
Auxiliary PLL (APLL) clock generator to boost operating frequency for ADC and PWM
Auxiliary Oscillator (AOSC) and Auxiliary PLL Clock (ACLK) generator for USB
Doze mode for system power savings
Scalable Reference Clock Output (REFCLKO)
On-the-fly clock switching between various clock sources
Linear Feedback Shift Register (LFSR) to generate pseudorandom data
Fail-Safe Clock Monitoring (FSCM) that detects clock failure and permits safe application
recovery or shutdown
A block diagram of the dsPIC33/PIC24 family oscillator system is shown in Figure 1-1.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. This document applies to all dsPIC33/PIC24 family devices. However,
some features in this document will not apply to all devices.
Please consult the note at the beginning of the “Oscillator Configuration” chapter
in the current device data sheet to check whether this document supports the
device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com.
© 2013 Microchip Technology Inc. DS70005131A-page 3
Oscillator Module
Figure 1-1: Oscillator System Block Diagram
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FRCDIVN
FRCDIV16
ECPLL, FRCPLL (F
PLLO
)
NOSC<2:0> FNOSC<2:0>
Reset
FRC
Oscillator
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
÷ 16
Clock Switch
0b000
Clock Fail
TUN<5:0>
PLL(1) FCY(3)
FOSC
FRCDIV
DOZE
Note 1: See Figure 7-1 for the source of the FVCO signal.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: The term, FP, refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when
Doze mode is used in any ratio other than 1:1.
FSCM
POSCCLK
FRCCLK
FVCO(1)
OSC2
OSC1
Primary Oscillator (POSC)
R(2)
POSCMD<1:0>
FP(3)
REFERENCE CLOCK OUTPUT
POSCCLK
ROSEL
FOSC
÷ N
RPn
REFCLKO
RODIV<3:0>
S4
SOSCO
Secondary Oscillator (SOSC)
POSCMD<1:0>
LPOSCEN
SOSCI
Auxiliary
Oscillator (AOSC)
ENAPLL
To Auxiliary Clock Generator
SOSC
÷ 2
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 4 © 2013 Microchip Technology Inc.
Figure 1-2: Auxiliary Clock Generator for PWM and ADC
Figure 1-3: Auxiliary Clock Generator for USB
ACLK
POSCCLK
SELACLK
FVCO(2)
ASRCSEL ENAPLL
÷ N
APSTSCLR<2:0>(1)
FRCCLK
FRCSEL
1
0
1
0
1
0
0
1
GND
PWM/ADC/LFSR
Note 1: The Auxiliary Clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation of the PWM and
ADC modules.
2: See Figure 7-1 for the source of the F VCO signal.
APLL x 16
ACLK
POSCCLK
SELACLK
FVCO(1)
ASRCSEL ENAPLL
APLL ÷ N
APLLPOST<1:0>
FRCCLK
FRCSEL
1
0
1
0
1
0
0
1
Note 1: See Figure 7-1 for source of F VCO signal.
USB
48 MHz
From Either Secondary Oscillator (SOSC)
or from Auxiliary Oscillator (A
OSC
)
© 2013 Microchip Technology Inc. DS70005131A-page 5
Oscillator Module
2.0 CPU CLOCKING
The system clock (FOSC) source can be provided by one of the following options:
Primary Oscillator (POSC) on the OSC1 and OSC2 pins
Internal Fast RC Oscillator (FRC) with optional clock divider
Internal Low-Power RC Oscillator (LPRC)
Primary Oscillator with PLL
Internal Fast RC Oscillator with PLL
Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins
The system clock source is divided by two to produce the internal instruction cycle clock. In this
document, the instruction cycle clock is denoted by FCY. The timing diagram in Figure 2-1
illustrates the relationship between the system clock (FOSC), the instruction cycle clock (FCY) and
the Program Counter (PC).
The internal instruction cycle clock (FCY) can be output on the OSC2 I/O pin if the Primary
Oscillator mode or the HS mode is not selected as the clock source. For more information, see
Section 5.0 “Primary Oscillator (POSC)”.
Figure 2-1: Clock and Instruction Cycle Timing
PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2) Fetch INST (PC + 2)
Execute INST (PC) Fetch INST (PC + 4)
Execute INST (PC + 2)
T
CY
FOSC
FCY
PC PC
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 6 © 2013 Microchip Technology Inc.
3.0 OSCILLATOR CONFIGURATION REGISTERS
Depending on the device, the Oscillator Configuration registers are implemented in one of two
ways:
- Oscillator Configuration registers are located in the program memory space and are
not Special Function Registers (SFRs). These registers are mapped into program
memory space and are programmed at the time of device programming.
- Can only be programmed indirectly by programming the Flash Configuration Word.
FOSCSEL: Oscillator Source Selection Register
FOSCSEL selects the initial oscillator source and start-up option. FOSCSEL contains the
following Configuration bits:
The FNOSC<2:0> Configuration bits in the Oscillator Source Selection register
(FOSCSEL<2:0>) determine the clock source that is used at a Power-on Reset (POR).
Thereafter, the clock source can be changed between permissible clock sources with
clock switching.
The Internal FRC Oscillator with Postscaler (FRCDIVN) is the default (unprogrammed)
selection.
FOSC: Oscillator Configuration Register
FOSC configures the Primary Oscillator mode, OSC2 pin function, Peripheral Pin Select (PPS),
and the Fail-Safe and Clock Switching modes. FOSC contains the following Configuration bits:
- The POSCMD<1:0> (FOSC<1:0>) Configuration bits select the operation mode of the
POSC.
- The OSCIOFNC (FOSC<2>) Configuration bit selects the OSC2 pin function, except in
HS or Medium Speed Oscillator (XT) mode.
If OSCIOFNC is unprogrammed (‘1’), the FCY clock is output on the OSC2 pin.
If OSCIOFNC is programmed (‘0’), the OSC2 pin becomes a general purpose I/O pin.
Table 3-1 lists the configuration settings that select the device oscillator source and operating
mode at a POR.
Table 3-1: Configuration Bit Values for Clock Selection
Oscillator
Source Oscillator Mode FNOSC<2:0>
Value
POSCMD<1:0>
Value Notes
S0 Fast RC Oscillator (FRC) 000 xx 1
S1 Fast RC Oscillator with PLL (FRCPLL) 001 xx 1
S2 Primary Oscillator (EC) 010 00 1
S2 Primary Oscillator (XT) 010 01
S2 Primary Oscillator (HS) 010 10
S3 Primary Oscillator with PLL (ECPLL) 011 00 1
S3 Primary Oscillator with PLL (XTPLL) 011 01
S3 Primary Oscillator with PLL (HSPLL) 011 10
S4 Secondary Oscillator (SOSC) 100 xx 1
S5 Low-Power RC Oscillator (LPRC) 101 xx 1
S6 Fast RC Oscillator with ÷ 16 Divider
(FRCDIV16)
110 xx 1
S7 Fast RC Oscillator with ÷ N Divider
(FRCDIVN)
111 xx 1 2,
Note 1: The OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
© 2013 Microchip Technology Inc. DS70005131A-page 7
Oscillator Module
Register 3-1: FOSCSEL: Oscillator Source Selection Register
U-Z U-Z U-Z U-Z U-Z U-Z U-Z U-Z
— —
bit 15 bit 8
R/P U-Z U-Z U-Z U-Z R/P R/P R/P
IESO FNOSC2 FNOSC1 FNOSC0
bit 7 bit 0
Legend: Z = Either a ‘1’ or a ‘0’, depending on device
R = Readable bit P = Programmable bit U = Unused bits, Program to Logic ‘1’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Reserved: Reserved bits must be programmed as1
bit 7 IESO: Internal External Start-up Option bit
1 = Start up device with Internal FRC Oscillator, then automatically switch to the user-selected oscillator
source when ready
0 = Start up device with user-selected oscillator source
bit 6-3 Reserved: Reserved bits must be programmed as ‘1
bit 2-0 FNOSC<2:0>: Initial Oscillator Source Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 8 © 2013 Microchip Technology Inc.
Register 3-2: FOSC: Oscillator Configuration Register
U-Z U-Z U-Z U-Z U-Z U-Z U-Z R/P
— PLLKEN
bit 15 bit 8
R/P R/P R/P U-Z U-Z R/P R/P R/P
FCKSM1 FCKSM0 IOL1WAY OSCIOFNC POSCMD1 POSCMD0
bit 7 bit 0
Legend: Z = Either a ‘1’ or a ‘0’, depending on device
R = Readable bit P = Programmable bit U = Unused bits, Program to Logic ‘1’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Reserved: Reserved bits must be programmed as1
bit 8 PLLKEN: PLL Lock Enable bit
1 = Source for PLL lock signal is the lock detect
0 = Source for PLL lock signal is the PLL enable signal
bit 7-6 FCKSM<1:0>: Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 5 IOL1WAY: Peripheral Pin Select (PPS) Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
bit 4-3 Reserved: Reserved bits must be programmed as1
bit 2 OSCIOFNC: OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output and the instruction cycle (F
CY) clock is output on the OSC2 pin
0 = OSC2 is a general purpose digital I/O pin
bit 1-0 POSCMD<1:0>: Primary Oscillator Mode Selection bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode (10 MHz to 40 MHz)
01 = XT Crystal Oscillator mode (3.5 MHz to 10 MHz)
00 = EC (External Clock) mode (0 MHz to 60 MHz)
© 2013 Microchip Technology Inc. DS70005131A-page 9
Oscillator Module
4.0 SPECIAL FUNCTION REGISTERS
These Special Function Registers provide run-time control and status of the oscillator system:
OSCCON: Oscillator Control Register(4)
This register controls clock switching and provides status information that allows current
clock source, PLL lock and clock fail conditions to be monitored.
CLKDIV: Clock Divisor Register
This register controls the Doze mode and selects the PLL prescaler, PLL postscaler and
FRC postscaler.
PLLFBD: PLL Feedback Divisor Register
This register selects the PLL feedback divisor.
OSCTUN: FRC Oscillator Tuning Register
This register is used to tune the Internal FRC oscillator frequency in software.
REFOCON: Reference Oscillator Control Register
This register controls the reference oscillator output.
ACLKCON1: Auxiliary Clock Control Register 1(1)
This register enables and controls the PLL Auxiliary Oscillator.
ACLKCON3: Auxiliary Clock Control Register 3(1)
This register controls and provides prescalar and postscalar values for the Auxiliary PLL
module.
ACLKDIV3: Auxiliary Clock Divisor Control Register 3(1)
This register selects the PLL feedback divisor for the Auxiliary PLL module.
LFSR: Linear Feedback Shift Register(1)
This register provides pseudorandom values.
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 10 © 2013 Microchip Technology Inc.
Register 4-1: OSCCON: Oscillator Control Register( )4
U-0 R-y R-y R-y U-0 R/W-y R/W-y R/W-y
— COSC2( , )1 2 COSC1( , )1 2 COSC0( , )1 2 NOSC2 NOSC1 NOSC0
bit 15 bit 8
R/S-0 R/W-0 R-0 U-0 R/C-0 U-0 R/W-0 R/W-0
CLKLOCK IOLOCK LOCK CF LPOSCEN OSWEN
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’ y = Depends on FNOSCx bits (FOSCSEL<2:0>)
R = Readable bit W = Writable bit C = Clearable bit S = Settable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0
bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)( , )1 2
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16 (FRCDIV16)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(3)
111 = Fast RC Oscillator with Divide by N (FRCDIVN)
110 = Fast RC Oscillator with Divide by 16 (FRCDIV16)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled (FCKSM<1:0> (FOSC<7:6>) = 01):
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source may be modified by clock switching
bit 6 IOLOCK: Peripheral Pin Select (PPS) Lock bit
1 = Peripheral Pin Select is locked; writes to Peripheral Pin Select registers are not allowed
0 = Peripheral Pin Select is not locked; writes to Peripheral Pin Select registers are allowed
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4 Unimplemented: Read as ‘0
Note 1: COSC<2:0> are set to FRC value on POR or BOR.
2: COSC<2:0> are loaded with NOSC<2:0> on Reset (not POR or BOR) and at the completion of a successful
clock switch.
3: Set to the value specified by the FNOSC<2:0> Configuration bits on any Reset.
4: Writes to this register require an unlock sequence. For more information and examples, see Section 14.0
“Clock Switching”.
© 2013 Microchip Technology Inc. DS70005131A-page 11
Oscillator Module
bit 3 CF: Clock Fail Detect bit (read or cleared by application)
1 = FSCM has detected a clock failure
0 = FSCM has not detected a clock failure
bit 2 Unimplemented: Read as 0
bit 1 LPOSCEN: 32 kHz Secondary (LP) Oscillator Enable bit
1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Register 4-1: OSCCON: Oscillator Control Register( )4 (Continued)
Note 1: COSC<2:0> are set to FRC value on POR or BOR.
2: COSC<2:0> are loaded with NOSC<2:0> on Reset (not POR or BOR) and at the completion of a successful
clock switch.
3: Set to the value specified by the FNOSC<2:0> Configuration bits on any Reset.
4: Writes to this register require an unlock sequence. For more information and examples, see Section 14.0
“Clock Switching”.
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 12 © 2013 Microchip Technology Inc.
Register 4-2: CLKDIV: Clock Divisor Register
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
ROI DOZE2( , )2 3 DOZE1( , )2 3 DOZE0( , )2 3 DOZEN( )1FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLLPOST1 PLLPOST0 PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits( , )2 3
111 = FCY divided by 128
110 = FCY divided by 64
101 = FCY divided by 32
100 = FCY divided by 16
011 = FCY divided by 8 (default)
010 = FCY divided by 4
001 = FCY divided by 2
000 = FCY divided by 1
bit 11 DOZEN: Doze Mode Enable bit( )1
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio are forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
bit 5 Unimplemented: Read as ‘0
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: The DOZE<2:0> bits can only be written when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
© 2013 Microchip Technology Inc. DS70005131A-page 13
Oscillator Module
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
00001 = Input divided by 3
00000 = Input divided by 2 (default)
Register 4-2: CLKDIV: Clock Divisor Register (Continued)
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: The DOZE<2:0> bits can only be written when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
© 2013 Microchip Technology Inc. DS70005131A-page 15
Oscillator Module
Register 4-4: OSCTUN: FRC Oscillator Tuning Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1 = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as 0
bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
011111 = Center frequency + (See data sheet for tolerance)
011110 = Center frequency + (See data sheet for tolerance)
000010 = Center frequency + (See data sheet for tolerance)
000001 = Center frequency + (See data sheet for tolerance)
000000 = Center frequency (7.373 MHz nominal)
111111 = Center frequency - (See data sheet for tolerance)
100001= Center frequency – (See data sheet for tolerance)
100000= Center frequency – (See data sheet for tolerance)
dsPIC33/PIC24 Family Reference Manual
DS70005131A-page 16 © 2013 Microchip Technology Inc.
Register 4-5: REFOCON: Reference Oscillator Control Register
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON ROSSLP ROSEL RODIV3( )1RODIV2( )1RODIV1( )1RODIV0( )1
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is enabled on REFOCLK pin
( )2
0 = Reference oscillator output is disabled
bit 14 Unimplemented: Read as 0
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep
0 = Reference oscillator output is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits( )1
1111 = Reference clock divided by 32,768
1110 = Reference clock divided by 16,384
1101 = Reference clock divided by 8,192
1100 = Reference clock divided by 4,096
1011 = Reference clock divided by 2,048
1010 = Reference clock divided by 1,024
1001 = Reference clock divided by 512
1000 = Reference clock divided by 256
0111 = Reference clock divided by 128
0110 = Reference clock divided by 64
0101 = Reference clock divided by 32
0100 = Reference clock divided by 16
0011 = Reference clock divided by 8
0010 = Reference clock divided by 4
0001 = Reference clock divided by 2
0000 = Reference clock
bit 7-0 Unimplemented: Read as ‘0
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See the “I/O Ports” chapter in the specific device data sheet for information.
© 2013 Microchip Technology Inc. DS70005131A-page 17
Oscillator Module
Register 4-6: ACLKCON1: Auxiliary Clock Control Register 1( )1
R/W-0 R/W-0 R/W-Z U-0 U-0 R/W-1 R/W-1 R/W-1
ENAPLL APLLCK SELACLK APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15 bit 8
R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0
ASRCSEL FRCSEL
bit 7 bit 0
Legend: Z = Either a ‘1’ or a ‘0’, depending on device
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ENAPLL: Auxiliary PLL Enable bit
1 = Auxiliary PLL is enabled
0 = Auxiliary PLL is disabled
bit 14 APLLCK: Auxiliary PLL Phase Locked State Status bit (read-only)
1 = Auxiliary PLL is in lock
0 = Auxiliary PLL is not in lock
bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary PLL, FRC or POSC provides the source clock for the Auxiliary Clock divider
0 = PLL output (FVCO) provides the source clock for the Auxiliary Clock divider
bit 12-11 Unimplemented: Read as 0
bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divide-by-1 (default)
110 = Divide-by-2
101 = Divide-by-4
100 = Divide-by-8
011 = Divide-by-16
010 = Divide-by-32
001 = Divide-by-64
000 = Divide-by-256
bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary Oscillator is the clock source
0 = Reserved
bit 6 FRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Selects FRC clock for clock source
0 = POSC is the clock source for APLL (determined by the ASRCSEL bit)
bit 5-0 Unimplemented: Read as ‘0
Note 1: This register is not available on all devices. Refer to the “Oscillator Configuration” chapter in the specific
device data sheet for availability.


Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: PIC24EP512MC206

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