Microchip PIC18F452 Handleiding

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2010 Microchip Technology Inc. DS39576C-page 1
PIC18FXX2/XX8
1.0 DEVICE OVERVIEW
This document includes the programming specifica-
tions for the following devices:
• PIC18F242
• PIC18F248
• PIC18F252
• PIC18F258
• PIC18F442
• PIC18F448
• PIC18F452
• PIC18F458
2.0 PROGRAMMING OVERVIEW
OF THE PIC18FXX2/XX8
The PIC18FXX2/XX8 can be programmed using the
high voltage In-Circuit Serial ProgrammingTM (ICSPTM)
method, or the low voltage ICSP method. Both of these
can be done with the device in the users’ system. The
low voltage ICSP method is slightly different than the
high voltage method, and these differences are noted
where applicable. This programming specification
applies to PIC18FXX2/XX8 devices in all package
types.
2.1 Hardware Requirements
In high voltage ICSP mode, the PIC18FXX2/XX8
requires two programmable power supplies: one for
VDD and one for MCLR/VPP. Both supplies should have
a minimum resolution of 0.25V. Refer to Section 6.0 for
additional hardware parameters.
2.1.1 LOW VOLTAGE ICSP
PROGRAMMING
In low voltage ICSP mode, the PIC18FXX2/XX8 can be
programmed using a VDD source in the operating
range. This only means that MCLR/VPP does not have
to be brought to a different voltage, but can instead be
left at the normal operating voltage. Refer to
Section 6.0 for additional hardware parameters.
2.2 Pin Diagrams
The pin diagrams for the PIC18FXX2/XX8 family are
shown in Figure 2-1. The pin descriptions of these dia-
grams do not represent the complete functionality of
the device types. Users should refer to the appropriate
device data sheet for complete pin descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18FXX2/XX8
Pin Name
During Programming
Pin Name Pin Type Pin Description
MCLR/VPP VPP P Programming Enable
VDD DDV P Power Supply
Vss VSS P Ground
RB5 PGM I Low Voltage ICSP™ Input when LVP
Configuration bit equals ‘1’(1)
RB6 SCLK I Serial Clock
RB7 SDATA I/O Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: See Section 5.3 for more detail.
Flash Microcontroller Programming Specification
PIC18FXX2/XX8
DS39576C-page 2 2010 Microchip Technology Inc.
FIGURE 2-1: PIC18FXX2/XX8 FAMILY PIN DIAGRAMS
Note: Not all multiplexed pin definitions are shown. Refer to the appropriate data sheet for complete pin descriptions.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9PIC18F4X2
RA4
RA5
RE0
OSC2
NC
RE1
RE2
VDD
OSC1
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
VSS
RC0
PIC18F4X8
44L PLCC
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
NC
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
PIC18F4X2
PIC18F4X8
44L QFP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4X2/8 40L DIP
9
MCLR/VPP
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
1
2
3
4
5
6
7
8
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
9
PIC18F2X2/8 28L DIP
PIC18F2X2/8 28L SOIC
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3
RA2
RA1
RA0
MCLR/VPP
RB3
RB7
RB6
RB5
RB4
NC
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
PIC18F4X2 AVSS
VDD
AVDD
PIC18F4X8
44L QFN
2010 Microchip Technology Inc. DS39576C-page 3
PIC18FXX2/XX8
2.3 Memory Map
The code memory space extends from 0000h to 7FFFh
(32 Kbytes) in four, 8-Kbyte panels. Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Panel 1. All code
memory is on-chip.
In addition to the code memory space, there are three
blocks in the configuration and ID space that are acces-
sible to the user through Table Reads and Table Writes.
Their locations in the memory map are shown in
Figure 2-3.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-2: CODE MEMORY SPACE FOR PIC18FXX2/XX8 DEVICES
Device Code Memory Size
(Bytes)
PIC18F242 0000h - 3FFFh (16K)
PIC18F248
PIC18F252 0000h - 7FFFh (32K)
PIC18F258
PIC18F442 0000h - 3FFFh (16K)
PIC18F448
PIC18F452 0000h - 7FFFh (32K)
PIC18F458
MEMORY SIZE / DEVICE
Block Code Protection
Controlled By:
16 Kbytes
(PIC18FX42)
32 Kbytes
(PIC18FX52)
Address
Range
Boot Block Boot Block 000000h
0001FFh CPB, WRTB, EBTRB
Block 0 Block 0
000200h
001FFFh
CP0, WRT0, EBTR0
Block 1 Block 1
002000h
003FFFh
CP1, WRT1, EBTR1
Unimplemented
Read ‘0’s Block 2
004000h
005FFFh
CP2, WRT2, EBTR2
Unimplemented
Read ‘0’s Block 3
006000h
007FFFh
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
008000h
1FFFFFh
(Unimplemented Memory Space)

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: PIC18F452

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