Microchip MIC45404 Handleiding

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2015-2017 Microchip Technology Inc. DS20005478B-page 1
MIC45404
Features
• Input Voltage Range: 4.5V to 19V
• Output Current: Up to 5A
• 82% Peak Efficiency at 12 VIN, 0.9 VOUT
• Pin-Selectable Output Voltages: 0.7V, 0.8V, 0.9V,
1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V
• ±1% Output Voltage Accuracy
• Supports Safe Pre-Biased Start-Up
• Pin-Selectable Current Limit
• Pin-Selectable Switching Frequency
• Internal Soft Start
• Thermal Shutdown
• Hiccup Mode Short-Circuit Protection
• Available in a 54-Lead 6 mm x 10 mm QFN
Package
• Ultra-Low Profile: 2.0 mm Height
• -40°C to +125°C Junction Temperature Range
Applications
• Servers, Data Storage, Routers and Base Stations
• FPGAs, SSD, DSP and Low-Voltage ASIC Power
General Description
The MIC45404 device is an ultra-low profile, synchro-
nous step-down regulator module, featuring a unique
2.0 mm height. The module incorporates a DC-to-DC
regulator, bootstrap capacitor, high-frequency input
capacitor and an inductor in a single package. The
module pinout is optimized to simplify the Printed
Circuit Board (PCB) layout process.
This highly-integrated solution expedites system
design and improves product time to market. The inter-
nal MOSFETs and inductor are optimized to achieve
high efficiency at low output voltage. Due to the fully
optimized design, MIC45404 can deliver up to 5A
current with a wide input voltage range of 4.5V to 19V.
The MIC45404 is available in a 54-lead 6 mm x
10 mm x 2.0 mm QFN package with a junction operat-
ing temperature range from -40C to +125C, which
makes an excellent solution for systems in which PCB
real-estate and height are important limiting factors,
and air flow is restricted.
Typical Application
VIN
OUT
VIN
4.5V to 19V
FREQ
VDDA
VOSET1
PG
GND
GND
VOSET0
COMP
EN/DLY
OUTSNS
MIC45404
V
DDA
Power-Good
Enable
VDDA
VDDA
Output
Voltage
Selection
VDDA
Frequency
Selection
ILIM
VDDA
Current Limit
Selection
VOUT
MIC45404 12V 5A DC-to-DC Converter
19V 5A Ultra-Low Profile DC-to-DC Power Module
MIC45404
DS20005478B-page 2 2015-2017 Microchip Technology Inc.
Package Types
Functional Diagram
MIC45404
6 mm x 10 mm QFN*
(Top View)
8
26
22
24
23
3
37
35
34
25
47
46
7
KEEPOUT
GND
GND
BST
PG
VDDA
LX
OUT
GND
21
KEEPOUT
48
38
4
1
2
AGND
VOSET1
NC
41
43
53
OUTSNS
EN/DLY
33
VOSET0
LX
44
45
VDDP
31
30
29
32
52
36
28
20
9
LX
LX
LX
LX
LX
LX
LX
LX
LX
OUT
OUT
12
OUT13
OUT14
OUT15
OUT16
OUT17
OUT18
OUT19
GND
VIN
VIN
27
LX
LX
39
40
LX
KEEPOUT
BST 42
NC
ILIM
49
FREQ
50
51
GND
COMP
54
OUTSNS
KEEPOUT10
OUT11
6 GND_EXT
5 GND_EXT
MIC45404YMP
GND_EP
* Includes Exposed Thermal Pad (EP); see Table 3-1.
LX
BST
ILIM
FREQ
VDDA
VOSET1
PG
AGND
VOSET0
COMP
EN/DLY
OUTSNS
VIN
PGND
VDDP
PWM
Regulator
100 nF
47 pF
LX
BST
VOSET1
AGND
VOSET0
GND_EP
OUTSNS
GND
COMP
OUT
ILIM
FREQ
VDDA
PG
EN/DLY
VIN
VDDP
GND_EXT
VDDP
LDO
VIN
2015-2017 Microchip Technology Inc. DS20005478B-page 3
MIC45404
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN to AGND ................................................................................................................................................ -0.3V to +20V
VDDP
, VDDA to AGND ..................................................................................................................................... -0.3V to +6V
VDDP to VDDA ............................................................................................................................................ -0.3V to +0.3V
VOSETX, FREQ, ILIM, to AGND .................................................................................................................... -0.3V to +6V
BST to LX..................................................................................................................................................... -0.3V to +6V
BST to AGND .............................................................................................................................................. -0.3V to +26V
EN/DLY to AGND...................................................................................................................... -0.3V to V
DDA + 0.3V, +6V
PG to AGND .................................................................................................................................................. -0.3V to +6V
COMP, OUTSNS to A
GND ....................................................................................................... -0.3V to V
DDA + 0.3V, +6V
AGND to GND ............................................................................................................................................ -0.3V to +0.3V
Junction Temperature .......................................................................................................................................... +150°C
Storage Temperature (TS)...................................................................................................................... -65°C to +150°C
Lead Temperature (soldering, 10s) ........................................................................................................................ 260°C
ESD Rating
( )1
HBM ........................................................................................................................................................................... 2kV
MM ........................................................................................................................................................................... 150V
CDM....................................................................................................................................................................... 1500V
Note 1: Devices are ESD-sensitive. Handling precautions are recommended. Human body model, 1.5 k in series
with 100 pF.
Operating Ratings( )1
Supply Voltage (VIN) ..................................................................................................................................... 4.5V to 19V
Externally Applied Analog and Drivers Supply Voltage (V
IN = VDDA = VDDP).............................................. 4.5V to 5.5V
Enable Voltage (EN/DLY)............................................................................................................................... 0V to V
DDA
Power Good (PG) Pull-up Voltage (VPU_PG) ................................................................................................ 0V to 5.5V
Output Current ............................................................................................................................................................. 5A
Junction Temperature (TJ) ..................................................................................................................... -40°C to +125°C
Note 1: The device is not ensured to function outside the operating range.
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
MIC45404
DS20005478B-page 4 2015-2017 Microchip Technology Inc.
ELECTRICAL CHARACTERISTICS( )1
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
VIN Supply
Input Range VIN 4.5 —19 V
Disable Current IVINQ — 33 60 µA EN/DLY = 0V
Operating Current IVINOp — 5.35 8.5 mA EN/DLY > 1.28V,
OUTSNS = 1.15 x VOUT(NOM),
no switching
VDDA 5V Supply
Operating Voltage VDDA 4.8 5.1 5.4 V EN/DLY > 0.58V,
IVDDA = 0 mA to 10 mA
Dropout Operation 3.6 3.75 — V VIN = 4.5V, EN/DLY > 0.58V,
IVDDA = 10 mA
VDDA Undervoltage Lockout
VDDA UVLO Rising UVLO_R 3.1 3.5 3.9 V V
DDA Rising, EN/DLY > 1.28V
VDDA UVLO Falling UVLO_F 2.87 3.2 3.45 V V
DDA Falling, EN/DLY > 1.28V
VDDA UVLO Hysteresis UVLO_H — 300 — mV
EN/DLY Control
LDO Enable Threshold EN_LDO_R — 515 600 mV Turns on VDDA LDO
LDO Disable Threshold EN_LDO_F 450 485 — mV Turns off VDDA LDO
LDO Threshold Hysteresis EN_LDO_H — 30 — mV
EN/DLY Rising Threshold EN_R 1.14 1.21 1.28 V Initiates power stage operation
EN/DLY Falling Threshold EN_F — 1.06 — V Stops power stage operation
EN/DLY Hysteresis EN_H — 150 — mV
EN/DLY Pull-up Current EN_I 1 32 µA
Switching Frequency
Programmable
Frequency (High Z)
fSZ 360 400 440 kHz FREQ = High Z (open)
Programmable Frequency 0 fS0 500 565 630 kHz FREQ= Low (GND)
Programmable Frequency 1 fS1 700 790 880 kHz FREQ = High (VDDA)
Overcurrent Protection
HS Current Limit 0 ILIM_HS0 6.0 7.1 8.1 A ILIM = Low (GND)
HS Current Limit 1 ILIM_HS1 8.1 10.39.3 A ILIM = High (VDDA)
HS Current Limit High Z ILIM_HSZ 9.3 10.5 11.9 A ILIM = High Z (open)
Top FET Current Limit
Leading-Edge Blanking Time
LEB — 108 — ns
LS Current Limit 0 ILIM_LS0 3.0 4.6 6.3 A ILIM = Low (GND)
LS Current Limit 1 ILIM_LS1 4.0 6.2 7.9 A ILIM = High (VDDA)
LS Current Limit High Z ILIM_LSZ 5.0 6.8 8.6 A ILIM = High Z (Open)
OC Events Count for Hiccup INHICC_DE — 15 — Clock
Cycles
Number of subsequent cycles
in current limit before entering
hiccup overload protection
Hiccup Wait Time tHICC_WAIT — 3 x Soft
Start Time
— Duration of the High Z state on
LX before new soft start
Note 1: Specification for packaged product only.
2015-2017 Microchip Technology Inc. DS20005478B-page 5
MIC45404
Pulse-Width Modulation (PWM)
Minimum LX On Time TON(MIN) — 26 — ns TA = TJ = +25°C
Minimum LX Off Time TOFF(MIN) 90 135 190 ns V
IN = VDDA = 5V, OUTSNS = 3V,
FREQ = Open (400 kHz setting),
VOSET0 = VOSET1 = 0V
(3.3V setting),
TA = TJ = +25°C
Minimum Duty Cycle DMIN — 0 — % OUTSNS > 1.1 x VOUT(NOM)
Gm Error Amplifier
Error Amplifier
Transconductance
GmEA — 1.4 — mS
Error Amplifier DC Gain AEA — 50000 — V/V
Error Amplifier Source/Sink
Current
ISR_SNK -400 — +400 µA TA = TJ = +25°C
COMP Output Swing High COMP_H — 2.5 — V
COMP Output Swing Low COMP_L — 0.8 — V
COMP-to-Inductor Current
Transconductance
GmPS — 12.5 — A/V VOUT = 1.2V, IOUT = 4A
Output Voltage DC Accuracy
Output Voltage Accuracy for
Ranges 1 and 2
OutErr12 -1 —1% 4.75V VIN 19V,
VOUT = 0.7V to 1.8V,
TA = TJ = -40°C to +125°C,
IOUT = 0A
Output Voltage Accuracy for
Range 3
OutErr3 —-1.5 1.5 % 4.75V VIN 19V,
VOUT = 2.49V to 3.3V,
TA = TJ = -40°C to +125°C,
IOUT = 0A
Load Regulation LoadReg — 0.03 — % IOUT = 0A to 5A
Line Regulation LineReg — 0.01 — % 6V < VIN < 19V, IOUT = 2A
Internal Soft Start
Reference Soft Start
Slew Rate
SS_SR — 0.42 — V/ms VOUT = 0.7V, 0.8V, 0.9V,
1.0V, 1.2V
Power Good (PG)
PG Low Voltage PG_VOL — 0.17 0.4 V IPG = 4 mA
PG Leakage Current PG_ILEAK -1 0.02 1µA PG = 5V
PG Rise Threshold PG_R 90 9592 % VOUT Rising
PG Fall Threshold PG_F 87.5 90 92.5 % VOUT Falling
PG Rise Delay PG_R_DLY — 0.45 — ms VOUT Rising
PG Fall Delay PG_F_DLY — 80 — µs VOUT Falling
ELECTRICAL CHARACTERISTICS( )1 (CONTINUED)
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Note 1: Specification for packaged product only.
MIC45404
DS20005478B-page 6 2015-2017 Microchip Technology Inc.
Thermal Shutdown
Thermal Shutdown TSHDN — 160 — °C
Thermal Shutdown
Hysteresis
TSHDN_HYST — 25 — °C
Efficiency
Efficiency η— 82 — % VIN = 12V, VOUT = 0.9V,
IOUT = 2A, fS = fSZ = 400 kHz,
TA = +25°C
ELECTRICAL CHARACTERISTICS( )1 (CONTINUED)
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Note 1: Specification for packaged product only.
TEMPERATURE SPECIFICATIONS
Electrical Specifications: unless otherwise specified, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
Boldface values indicate -40°C TJ +125°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Ambient Junction Range TJ-40 — +125 °C
Storage Temperature Range TA-65 — +150 °C
Maximum Junction Temperature TJ-40 — +150 °C
Package Thermal Resistances
Thermal Resistance, 54 Lead,
6 mm x10 mm QFN
JA — 20 — °C/W See “MIC45404 Evaluation
Board User’s Guide,
DS50002448”
2015-2017 Microchip Technology Inc. DS20005478B-page 7
MIC45404
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-1: Operating Current (IQ) vs.
Input Voltage.
FIGURE 2-2: VDDA Voltage vs. Input
Voltage.
FIGURE 2-3: Output Current Limit vs.
Input Voltage.
FIGURE 2-4: Enable Threshold vs. Input
Voltage.
FIGURE 2-5: EN/DLY Pull-up Current vs.
Input Voltage.
FIGURE 2-6: Operating Current (IQ) vs.
Temperature.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
31.00
33.00
35.00
4 6 8 10 12 14 16 18 20
IQ (mA)
VIN (V)
f = 565 kHz
VOUT = 1.8V
f = 400 kHz
VOUT = 1.0V
Switching
IOUT = 0A
f = 790 kHz
VOUT = 3.3V
4
4.2
4.4
4.6
4.8
5
5.2
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5
VDDA (V)
VIN (V)
I
V
DD
A
= 0 mA
IVDDA = 10 mA
5
5.5
6
6.5
7
7.5
8
8.5
4.5 5 5.5 6 8 10 12 14 16 18 19
IOUT (A)
VIN(V)
ILIM = GND
ILIM = VDDA
ILIM = high Z
VOUT
= 1.2V
f = 400 kHz
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5
Enable (V)
V
IN (V)
Enable rising
Enable falling
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Current (µA)
VIN (V)
EN/DLY = 0V
15
20
25
30
35
-40 -25 -10 5 20 35 50 65 80 95 110 125
IQ (mA)
Temperature (°C)
Switching
V
IN = 12V
I
OUT = 0A
f = 565 kHz
VOUT = 1.8V
f = 790 kHz
VOUT = 3.3V
f = 400 kHz
VOUT = 1.0V
MIC45404
DS20005478B-page 8 2015-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-7: EA Output Current vs.
Temperature.
FIGURE 2-8: EA Transconductance vs.
Temperature.
FIGURE 2-9: Efficiency vs. Output
Current (VIN = 12V).
FIGURE 2-10: Efficiency vs. Output
Current (VIN = 5V).
FIGURE 2-11: Output Voltage vs. Output
Current (VOUT = 0.9V).
FIGURE 2-12: Output Voltage vs. Output
Current (VOUT = 1.0V).
-800
-600
-400
-200
0
200
400
600
800
-40 -20 0 20 40 60 80 100 120 140
EA Output Current (µA)
Temperature(°C)
VIN = 12V
Sinking
Sourcing
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-40 -20 0 20 40 60 80 100 120 140
EA Transconductance (mS)
Temperature (°C)
VIN = 12V
VOUT = 1.0V
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
80.00%
90.00%
100.00%
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Efficiency (%)
IOUT (A)
1
1
1
1
1
1
1
1
1
0.7V
0.8V
0.9V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
2015-2017 Microchip Technology Inc. DS20005478B-page 9
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-13: Output Voltage vs. Output
Current (VOUT = 1.2V).
FIGURE 2-14: Output Voltage vs. Output
Current (VOUT = 1.5V).
FIGURE 2-15: Output Voltage vs. Output
Current (VOUT = 1.8V).
FIGURE 2-16: Output Voltage vs. Output
Current (VOUT = 2.5V).
FIGURE 2-17: Output Voltage vs. Output
Current (VOUT = 3.3V).
2.480
2.485
2.490
2.495
2.500
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOUT (V)
IOUTt (A)
VIN = 12V
VIN = 5V
3.290
3.292
3.294
3.296
3.298
3.300
3.302
3.304
3.306
3.308
3.310
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOUT (V)
IOUT (A)
VIN = 12V
VIN = 5V
MIC45404
DS20005478B-page 10 2015-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-18: VIN Turn-On.
FIGURE 2-19: VIN Turn-Off.
FIGURE 2-20: Enable Turn-On.
FIGURE 2-21: Enable Turn-Off.
FIGURE 2-22:
Enable Start-Up with
Pre-Biased Output.
FIGURE 2-23: Enable Start-Up with
Pre-Biased Output.
VIN = 12V
VOUT = 1.2V
RLOAD = 0.3
fSW = 400 kHz
VIN
(5V/div)
VOUT
(500 mV/div)
PG
(5V/div)
Time (2 ms/div)
V
IN
(5V/div)
V
OUT
(500 mV/div
PG
(5V/div)
VIN = 12V
VOUT = 1.2V
RLOAD = 0.6
fSW = 400 kHz
Time (2 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
ROUT = 0.24
fSW = 400 kHz IOUT(2A/div)
Time (1 ms/div)
EN/DLY(2V/div
V
OUT (500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
R
OUT = 0.24
fSW = 400 kHz
IOUT (2A/div)
Time (40 µs/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
VPRE-BIAS = 0.6V
fSW = 400 kHz
Time (1 ms/div)
EN/DLY(2V/div
VOUT (500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
VPRE-BIAS = 1.0V
fSW = 400 kHz
Time (1 ms/div)
2015-2017 Microchip Technology Inc. DS20005478B-page 11
MIC45404
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-24: Power-Up into Short Circuit.
FIGURE 2-25: Enable Into Short Circuit.
FIGURE 2-26: Output Current Limit
(ILIM = 0V).
FIGURE 2-27: Output Current Limit
(ILIM = High Z).
FIGURE 2-28: Hiccup Mode Short Circuit
and Output Recovery.
FIGURE 2-29: Thermal Shutdown and
Thermal Recovery.
VIN(5V/div)
VOUT
(500 mV/div)
PG(5V/div)
IOUT(5A/div)
Time (1 ms/div)
EN/DLY(2V/div
VOUT
(500 mV/div)
PG(5V/div)
I
OUT (5A/div)
Time (1 ms/div)
VOUT
(500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
fSW = 400 kHz
ILIM = 0V
IOUT(2A/div)
Time (1 ms/div)
VOUT
(500 mV/div)
PG(5V/div)
VIN = 12V
VOUT = 1.2V
fSW = 400 kHz
ILIM = high Z
IOUT(2A/div)
Time (1 ms/div)
VOUT (500 mV/div)
PG(5V/div)
I
OUT (2A/div)
Time (20 ms/div)
IOUT(2A/div)
VOUT
(500 mV/div)
PG(5V/div)
Time (200 ms/div)
MIC45404
DS20005478B-page 12 2015-2017 Microchip Technology Inc.
Note: Unless otherwise indicated, VIN = 12V; CVDDA= 2.2 µF, TA = +25°C.
FIGURE 2-30: Switching Waveforms
(IOUT = 0A).
FIGURE 2-31: Switching Waveforms
(IOUT = 5A).
FIGURE 2-32: Load Transient Response.
FIGURE 2-33: Line Transient Response.
VIN
AC-Coupled
(20 mV/div)
VOUT
AC-Coupled
(10 mV/div)
SW (5V/div)
Time (1 µs/div)
VIN = 12V
VOUT = 1.2V
IOUT = 0A
fSW = 400 kHz
VIN
AC-Coupled
(100 mV/div)
VOUT
AC-Coupled
(10 mV/div)
SW (5V/div)
Time (1 µs/div)
VIN = 12V
VOUT = 1.2V
IOUT = 5A
fSW = 400 kHz
IOUT
(2A/div)
VOUT
AC-Coupled
(100 mV/div)
PG (5V/div)
VIN = 12V
VOUT = 1.0V
RLOAD = 1  to 0.3
Time (100 µs/div)
VIN
(2V/div)
VOUT
AC-Coupled
(20 mV/div)
PG(5V/div)
Time (1 ms/div)
2015-2017 Microchip Technology Inc. DS20005478B-page 13
MIC45404
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
3.1 Output Sensing Pins (OUTSNS)
Connect these pins directly to the Buck Converter
output voltage. These pins are the top side terminal of
the internal feedback divider.
3.2 Precision Enable/Turn-On Delay
Input Pin (EN/DLY)
The EN/DLY pin is first compared against a 515 mV
threshold to turn on the on-board LDO regulator. The
EN/DLY pin is then compared against a 1.21V (typical)
threshold to initiate output power delivery. A 150 mV
typical hysteresis prevents chattering when power
delivery is started. A 2 µA (typical) current source pulls
up the EN/DLY pin. Turn-on delay can be achieved by
connecting a capacitor from EN/DLY to ground, while
using an open-drain output to drive the EN/DLY pin.
3.3 MOSFET Drivers Internal
Supply Pin (VDDP)
Internal supply rail for the MOSFET drivers, fed by the
VDDA pin. An internal resistor (10) between the V
DDP
and VDDA pins, and an internal decoupling capacitor
are provided in the module in order to implement an RC
filter for switching noise suppression.
3.4 Internal Regulator Output Pin
(VDDA)
Output of the internal linear regulator and internal
supply for analog control. A 1 µF minimum ceramic
capacitor should be connected from this pin to GND; a
2.2 µF nominal value is recommended.
TABLE 3-1: PIN FUNCTION TABLE
MIC45404 Symbol Pin Function
1, 54 OUTSNS Output Sensing Pin
2 EN/DLY Precision Enable/Turn-On Delay Input Pin
3 VDDA Internal LDO Output and Analog Supply Pin
4 VDDP MOSFET Drivers Internal Supply Pin
5, 6 GND_EXT Ground Extension Pins
7, 8 VIN Input Voltage Pins
9, 23, 24, 50, 51 GND Power Ground Pins
11, 12, 13, 14, 15, 16, 17, 18,
19, 20, 21
OUT Output Side Connection Pins
10, 22, 25, 40 KEEPOUT Depopulated Pin Positions
26, 27, 28, 29, 30, 31, 32, 33,
34, 35, 36, 37, 38, 39
LX Switch Node Pins
41, 42 BST Bootstrap Capacitor Pin
43 PG Power Good Output Pin
44 VOSET0 Output Voltage Selection Pins
45 VOSET1
46, 47 NC Not Connected Pins
48 ILIM Current Limit Selection Pin
49 FREQ Switching Frequency Selection Pin
52 AGND Analog Ground Pin
53 COMP Compensation Network Pin
55 GND_EP Ground Exposed Pad.
MIC45404
DS20005478B-page 14 2015-2017 Microchip Technology Inc.
3.5 Ground Extension Pins
(GND_EXT)
These pins are used for the bottom terminal connection
of the internal VIN and VDDP decoupling capacitors.
The GND_EXT pins should be connected to the GND
net, directly at the top layer, using a wide copper
connection.
3.6 Input Voltage Pins (VIN)
Input voltage for the Buck Converter power stage and
input of the internal linear regulator. These pins are the
drain terminal of the internal high-side N-channel
MOSFET. A 10 µF (minimum) ceramic capacitor should
be connected from VIN to GND, as close as possible to
the device.
3.7 Power Ground Pins (GND)
Connect the output capacitors to GND Pins 23 and 24,
as close as possible to the module.
Connect the input capacitors to GND Pin 9, as close as
possible to the module.
3.8 Output-Side Connection Pins
(OUT)
Output side connection of the internal inductor. The
output capacitors should be connected from this pin
group to GND (Pins 23 and 24), as close to the module
as possible.
3.9 Switch Node Pins (LX)
Switch Node: Drain (low-side MOSFET) and source
(high-side MOSFET) connection of the internal power
N-channel FETs. The internal inductor switched side
and the bootstrap capacitor are connected to LX.
Leave this pin floating.
3.10 Bootstrap Capacitor Pin (BST)
Connection to the internal bootstrap capacitor and
high-side power MOSFET drive circuitry. Leave this pin
floating.
3.11 Power Good Output Pin (PG)
When the output voltage is within 92.5% of the nominal
set point, this pin will go from logic low to logic high
through an external pull-up resistor. This pin is the drain
connection of an internal N-channel FET.
3.12 Output Voltage Selection Pins
(VOSET0 and VOSET1)
Three-state pin (low, high and High Z) for output volt-
age programming. Both VOSET0 and VOSET1 define
nine logic values, corresponding to nine output voltage
selections.
3.13 Not Connected Pins (NC)
These pins are not internally connected. Leave them
floating.
3.14 Current Limit Pin (ILIM)
This pin allows the selection of the current limit state:
low, high and High Z.
3.15 Switching Frequency Pin (FREQ)
This pin allows the selection of the frequency state: low,
high and High Z.
3.16 Analog Ground Pin (A
GND)
This pin is a quiet ground for the analog circuitry of the
internal regulator and a return terminal for the external
compensation network.
3.17 Compensation Network Pin
(COMP)
Connect a compensation network from this pin to
AGND.
3.18 GND Exposed Pad
Connect to ground plane with thermal vias.
2015-2017 Microchip Technology Inc. DS20005478B-page 15
MIC45404
4.0 FUNCTIONAL DESCRIPTION
The MIC45404 is a pin-programmable, 5A Valley
Current mode controlled power module, with an input
voltage range from 4.5V to 19V.
The MIC45404 requires a minimal amount of external
components. Only two supply decoupling capacitors
and a compensation network are external. The
flexibility in designing the external compensation
allows the user to optimize the design across the entire
input voltage and selectable output voltages range.
4.1 Theory of Operation
Valley Current mode control is a fixed frequency, lead-
ing-edge modulated Pulse-Width Modulation (PWM)
Current mode control. Differing from the Peak Current
mode, the Valley Current mode clock marks the turn-off
of the high-side switch. Upon this instant, the
MIC45404 low-side switch current level is compared
against the reference current signal from the error
amplifier. When the falling low-side switch current sig-
nal drops below the current reference signal, the
high-side switch is turned on. As a result, the inductor
valley current is regulated to a level dictated by the
output of the error amplifier.
The feedback loop includes an internal programmable
reference and output voltage sensing attenuator, thus
removing the need for external feedback components
and improving regulation accuracy. Output voltage feed-
back is achieved by connecting the OUTSNS pin directly
to the output. The high-performance transconductance
error amplifier drives an external compensation network
at the COMP pin. The COMP pin voltage represents the
reference current signal. This pin voltage is fed to the
Valley Current mode modulator, which also adds slope
compensation to ensure current loop stability.
Internal inductor, power MOSFETs and internal
bootstrap diode complete the power train.
Overcurrent protection and thermal shutdown protect
the MIC45404 from faults or abnormal operating
conditions.
4.2 Supply Rails (VIN, VDDA, VDDP)
and Internal LDO
VIN pins represent the power train input. These pins are
the drain connection of the internal high-side MOSFET
and should be bypassed to GND, at least with a X5R or
X7R 10 µF ceramic capacitor, placed as close as
possible to the module. Multiple capacitors are
recommended.
An internal LDO provides a clean supply (5.1V typical)
for the analog circuits at the V
DDA pin. The internal LDO
is also powered from VIN, as shown in the Functional
Diagram. The internal LDO is enabled when the
voltage at the EN/DLY pin exceeds about 0.51V, and
regulation takes place as soon as enough voltage has
been established between the VIN and VDDA pins. An
internal Undervoltage Lockout (UVLO) circuit monitors
the level of VDDA. The VDDA pin needs external bypass-
ing to GND by means of a 2.2 µF X5R or X7R ceramic
capacitor, placed as close as possible to the module.
VDDP is the power supply rail for the gate drivers and
bootstrap circuit. This pin is bypassed to GND_EXT by
means of an internal high-frequency ceramic capacitor.
For this reason, the GND_EXT pins should be routed
with a low-inductance path to the GND net. An internal
10 resistor is provided between VDDA and VDDP
,
allowing the implementation of a switching noise atten-
uation RC filter with the minimum amount of external
components. It is possible, although typically not
necessary, to lower the RC time constant by connecting
an external resistor between VDDA and V
DDP
.
If the input rail is within 4.5V to 5.5V, it is possible to
bypass the internal LDO by connecting VIN, VDDA and
VDDP together. Local decoupling of the VDDA
pin is still
recommended.
4.3 Pin-Strapping Programmability
(VOSET0, VOSET1, FREQ, ILIM)
The MIC45404 uses pin strapping to set the output volt-
age (VOSET0, VOSET1), switching frequency (FREQ)
and current limit (ILIM). No external passives are needed,
therefore, the external component count is minimized.
Each pin is a three-state input (connect to GND for LOW
logic level, connect to VDDA for HIGH logic level or leave
unconnected for High Z). The logic level of the pins is
read and frozen in the internal configuration logic
immediately after the VDDA rail comes up and becomes
stabilized. After this instant, any change of the input logic
level on the pins will have no effect until the V
DDA power
is cycled again. The values corresponding to each
particular pin strapping configuration are detailed in
Section 5.0 “Application Information”.
MIC45404
DS20005478B-page 16 2015-2017 Microchip Technology Inc.
4.4 Enable/Delay (EN/DLY)
The EN/DLY pin is a dual threshold pin that turns the
internal LDO on/off and starts/stops the power delivery
to the output, as shown in Figure 4-1.
FIGURE 4-1: EN/DLY Pin Functionality.
The threshold for LDO enable is 515 mV (typical) with
a hysteresis of approximately 30 mV. This hysteresis is
enough because at the time of LDO activation, there is
still no switching activity.
The threshold for power delivery is a precise 1.21V,
±70 mV. A 150 mV typical hysteresis prevents chattering
due to switching noise and/or slow edges.
A 2 µA typical pull-up current, with ±1 µA accuracy, per-
mits the implementation of a start-up delay by means of
an external capacitor. In this case, it is necessary to use
an open-drain driver to disable the MIC45404 while
maintaining the start-up delay function.
4.5 Power Good (PG)
The PG pin is an open-drain output that requires an
external pull-up resistor to a pull-up voltage (V
PU_PG),
lower than 5.5V, for being asserted to a logic HIGH
level. The PG pin is asserted with a typical delay of
0.45 ms when the output voltage (OUTSNS) reaches
92.5% of its target regulation voltage. This pin is
deasserted with a typical delay of 80 µs when the
output voltage falls below 90% of its target regulation
voltage. The PG falling delay acts as a deglitch timer
against very short spikes. The PG output is always
immediately deasserted when the EN/DLY pin is below
the power delivery enable threshold (EN_R/EN_F).
The pull-up resistor should be large enough to limit the
PG pin current to below 2 mA.
4.6 Inductor (LX, OUT) and Bootstrap
(BST) Pins
The internal inductor is connected across the LX and
OUT pins. The high-side MOSFET driver circuit is pow-
ered between BST and LX by means of an internal
capacitor that is replenished from rail VDDP during the
low-side MOSFET on time. The bootstrap diode is
internal.
4.7 Output Sensing (OUTSNS) and
Compensation (COMP) Pins
OUTSNS should be connected exactly to the desired
Point-of-Load (POL) regulation, avoiding parasitic
resistive drops. The impedance seen into the OUTSNS
pin is high (tens of k or more, depending on the
selected output voltage value), therefore, its loading
effect is typically negligible. OUTSNS is also used by
the slope compensation generator.
The COMP pin is the connection for the external com-
pensation network. COMP is driven by the output of the
transconductance error amplifier. Care must be taken
to return the compensation network ground directly to
AGND.
4.8 Soft Start
The MIC45404 internal reference is ramped up at a
0.42 V/ms rate. Note that this is the internal reference
soft start slew rate and that the actual slew rate seen at
the output should take into account the internal divider
attenuation, as detailed in the Section 5.0 “Application
Information”.
4.9 Switching Frequency (FREQ)
The MIC45404 features three different selectable
switching frequencies (400 kHz, 565 kHz and
790 kHz). Frequency selection is tied with a specific
output voltage selection, as described in Section 5.5
“Permissible MIC45404 Settings Combinations”.
4.10 Pre-Biased Output Start-up
The MIC45404 is designed to achieve safe start-up into
a pre-biased output without discharging the output
capacitors.
4.11 Thermal Shutdown
The MIC45404 has a thermal shutdown protection that
prevents operation at excessive temperature. The
thermal shutdown threshold is typically set at +160°C,
with a hysteresis of +25°C.
EN/DLY Enable Power
Comparator
EN_I
2 µA
AGND
EN_R
1.21V
VIN
Enable
Power
Delivery
150 mV
EN_LDO_R
515 mV
Enable LDO
Comparator
2015-2017 Microchip Technology Inc. DS20005478B-page 17
MIC45404
4.12 Overcurrent Protection (ILIM) and
Hiccup Mode Short-Circuit
Protection
The MIC45404 features instantaneous cycle-by-cycle
current limit with current sensing, both on the low-side
and high-side switches. It also offers a Hiccup mode for
prolonged overloads or short-circuit conditions.
The low-side cycle-by-cycle protection detects the cur-
rent level of the inductor current during the low-side
MOSFET on time. The high-side MOSFET turn-on is
inhibited as long as the low-side MOSFET current limit is
above the overcurrent threshold level. The inductor cur-
rent will continue decaying until the current falls below
the threshold, where the high-side MOSFET will be
enabled again, according to the duty cycle requirement
from the PWM modulator.
The low-side current limit has three different program-
mable levels (for 3A, 4A and 5A loads) in order to fit
different application requirements. Since the low-side
current limit acts on the valley current, the DC output
current level (IOUT), where the low-side cycle-by-cycle
current limit is engaged, will be higher than the current
limit value by an amount equal to ILPP/2, where ILPP
is the peak-to-peak inductor ripple current.
The high-side current limit is approximately
1.4-1.5 times greater than the low-side current limit
(typical values). The high-side cycle-by-cycle current
limit immediately truncates the high-side on time
without waiting for the off clocking event.
A Leading-Edge Blanking (LEB) timer (108 ns, typical)
is provided on the high-side cycle-by-cycle current limit
to mask the switching noise and to prevent falsely
triggering the protection. The high-side cycle-by-cycle
current limit action cannot take place before the LEB
timer expires.
Hiccup mode protection reduces power dissipation in
permanent short-circuit conditions. On each clock
cycle, where a low-side cycle-by-cycle current limit
event is detected, a 4-bit up/down counter is incre-
mented. On each clock cycle without a concurrent
low-side current limit event, the counter is decremented
or left at zero. The counter cannot wraparound below
‘0000’ and above ‘1111’. High-side current limit events
do not increment the counter. Only detections from
low-side current limit events trigger the counter.
If the counter reaches ‘1111’ (or 15 events), the high
and low-side MOSFETs become tri-stated, and power
delivery to the output is inhibited for the duration of
three times the soft start time. This digital integration
mechanism provides immunity to momentary overload-
ing of the output. After the wait time, the MIC45404
retries entering operation and initiates a new soft start
sequence.
MIC45404
DS20005478B-page 18 2015-2017 Microchip Technology Inc.
Figure 4-2 illustrates the Hiccup mode short-circuit
protection logic flow. Note that Hiccup mode
short-circuit protection is active at all times, including
the soft start ramp.
FIGURE 4-2: Hiccup Mode Short-Circuit Protection Logic.
START
CLEAR
LS OC EVENTS
COUNTER
CLOCK PULSE
(MARKING HS
TURN-OFF,
LS TURN-ON) IDLE LOOP
IN NORMAL
OPERATION
LS OC EVENT
DETECTED?
EVENT
COUNTER = 0
DECREMENT
EVENT
COUNTER
EVENT COUNTER
FULL?
INCREMENT
EVENT
COUNTER
INITIATE HICCUP
SEQUENCE
STOP SWITCHING
HS AND LS
CYCLE THREE TIMES
INTERNAL SOFT START
CAPACITOR
CLEAR
LS OC EVENTS
COUNTER
INITIATE SOFT START
ENABLE SWITCHING
YES
YES
YES
NO
NO
NO
2015-2017 Microchip Technology Inc. DS20005478B-page 19
MIC45404
5.0 APPLICATION INFORMATION
5.1 Programming Start-up Delay and
External UVLO
The EN/DLY pin allows programming an external
start-up delay. In this case, the driver for the EN/DLY
pin should be an open-drain/open-collector type, as
shown in Figure 5-1.
FIGURE 5-1: Programmable Start-Up Delay Function.
The start-up delay is the delay time from the off falling
edge to the assertion of the enable power delivery
signal. It can be calculated as shown in Equation 5-1:
EQUATION 5-1:
The EN/DLY pin can also be used to program a UVLO
threshold for power delivery by means of an external
resistor divider, as described in Figure 5-2.
FIGURE 5-2: Programmable External UVLO Function.
EN/DLY Enable Power
Comparator
EN_I
2 µA
AGND
EN_R
1.21V
VIN
Enable
Power
Delivery
150 mV
EN_LDO_R
515 mV
Enable LDO
Comparator
C
DLY
Off
tSU_DL Y
EN_R CDLY
EN_I
-----------------------------------=
Where:
EN_R = 1.21V
EN_I = 2 µA
CDLY = Delay programming external capacitor
EN/DLY Enable Power
Comparator
R2
R1
EN_I
2 µA
AGND
EN_R
1.21V
VIN
Enable
Power
Delivery
150 mV
EN_LDO_R
515 mV
Enable LDO
Comparator
MIC45404
DS20005478B-page 22 2015-2017 Microchip Technology Inc.
5.7 Input Capacitor Selection
Two main requirements determine the size and
characteristics of the input capacitor:
• Steady-State Ripple
• RMS Current
The Buck Converter input current is a pulse train with
very fast rising and falling times, so low-ESR ceramic
capacitors are recommended for input filtering because
of their good high-frequency characteristics.
By assuming an ideal input filter (which can be assimi-
lated to a DC input current feeding the filtered buck
power stage) and by neglecting the contribution of the
input capacitor ESR to the input ripple (which is typically
possible for ceramic input capacitors), the minimum
capacitance value, CIN(MIN), needed for a given input
peak-to-peak ripple voltage, V
r, IN, can be estimated as
shown in Equation 5-11:
EQUATION 5-11:
The RMS current, IIN,RMS, of the input capacitor is
estimated as in Equation 5-12:
EQUATION 5-12:
Note that, for a given output current, I
O, worst-case
values are obtained at D = 0.5.
Multiple input capacitors can be used to reduce input
ripple amplitude and/or individual capacitor RMS
current.
5.8 Compensation Design
As a simple first-order approximation, the Valley Current
mode controlled buck power stage can be modeled as a
voltage-controlled current source, feeding the output
capacitor and load. The inductor current state variable is
removed and the power stage transfer function from
COMP to the inductor current is modeled as a transcon-
ductance (GmPS). The simplified model of the control
loop is shown in Figure 5-3. The power stage trans-
conductance, GmPS, shows some dependence on
current levels and it is also somewhat affected by
process variations, therefore, some design margin is
recommended against the typical value, Gm
PS = 12.5A/V
(see Section 1.0 “Electrical Characteristics”).
FIGURE 5-3: Simplified Small Signal
Model of the Voltage Regulation Loop.
This simplified approach disregards all issues related
to the inner current loop, like its stability and bandwidth.
This approximation is good enough for most operating
scenarios, where the voltage loop bandwidth is not
pushed to aggressively high frequencies.
Based on the model shown in Figure 5-3, the
control-to-output transfer function is:
EQUATION 5-13:
The MIC45404 module uses a transconductance
(GmEA = 1.4 mA/V) error amplifier. Frequency compen-
sation is implemented with a Type-II network (RC1, CC1
and CC2) connected from the COMP to AGND. The
compensator transfer function consists of an integrator
for zero DC voltage regulation error, a zero to boost the
phase margin of the overall loop gain around the
crossover frequency and an additional pole that can
be used to cancel the output capacitor ESR zero, or to
further attenuate switching frequency ripple. In both
cases, the additional pole makes the regulation loop
less susceptible to switching frequency noise. The
additional pole is created by capacitor C
C2 (internally
provided, CC2 value is 47 pF). Equation 5-14 details the
compensator transfer function, HC(S) (from OUTSNS to
COMP).
CIN MIN 
IOD 1 D– 
Vr,IN f
S
----------------------------------------=
Where:
D is the duty cycle at the given operating point.
IIN,RMS IOD 1 D– 
=
GmPS
Gm Error
Amplifier
OUTSNS
COMP
R2
R1
REFDAC
VO Range CC2
C
C1
RC1
CoRL
ESR
Vo
VIN
Vc
IL
GmEA
GCO S 
VO S 
VC S 
------------- GmPS RL
1s
2fZ
-----------------+
 
 
1s
2fP
-----------------+
 
 
--------------------------------= =
Where fZ and fP = the frequencies associated with
the output capacitor ESR zero and with the load
pole, respectively:
fZ
1
2COESR
-------------------------------------=
fP
1
2COESR RL
+ 
-------------------------------------------------------=

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: MIC45404

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