Microchip MIC4103 Handleiding


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MIC4103/4104
100V Half-Bridge MOSFET Drivers with
3A/2A Sinking/Sourcing Current
General Description
T - -he MIC4103 and MIC4104 are high frequency, 100V half
bridge MOSFET drivers with faster turn off characteristics -
than the MIC4100 and MIC4101 drivers. They feature fast
24ns propagation delay times and 6ns driver fall times.
The low side and high side gate drivers are independently - -
controlled and matched to within 3ns (typical). The
MIC4103 has CMOS input thresholds and the MIC4104
has TTL input thresholds. The MIC4103/4 include a high-
voltage internal diode that charges the high side gate drive -
bootstrap capacitor.
A robust, high speed, and low power level shifter provides - -
clean level transitions to the high side output. The robust -
operation of the MIC4103/4 ensures the outputs are not
affected by supply glitches, HS ringing below ground, or
HS slewing with high-speed voltage transitions.
Undervoltage protection is provided on both the low-side
and high-side drivers.
The MIC4103 and MIC4104 are available in an 8- pin SOIC
package with an operating junction temperature range of
° ° 40 C to +125 C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Features
Asymmetrical, low impedance outputs drive 1000pF
load with 10ns rise times and 6ns fall times
Bootstrap supply maximum voltage to 118V DC
Supply voltage up to 16V
- -Drives high and low side N Channel MOSFETs with
independent inputs
CMOS input thresholds (MIC4103)
TTL input thresholds (MIC4104)
- On chip bootstrap diode
Fast 24ns propagation times
Low power consumption
Supply undervoltage protection
• Ω Typical 2.5 -pull up and 1.25 -pull down output driver
resistance
° ° 40 C to +125 C junction temperature range
Applications
- High voltage buck converters
- - Full and half bridge power topologies
Active clamp forward converter
Two switch forward topologies
Interface to digital controllers
Typical Application
100V Buck Regulator Solution
Micrel Inc. • 2180 Fortune Drive • Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • San - - http://www.micrel.com
November 12, 2014 Revision 3.0
Micrel, Inc.
MIC4103/4104
Ordering Information
Part Number Input Junction Temperature Range Package
MIC4103YM 40 CMOS ° 8- to +125°C Pin SOIC
MIC4104YM TTL 40° to +125°C 8- Pin SOIC
Pin Conguration
8- ( Pin SOIC M)
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1 VDD Positive Supply to lower gate drivers. Decouple this pin to VSS (Pin 7). Bootstrap diode connected
to HB (pin 2).
2 HB High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of
bootstrap capacitor to this pin. Bootstrap diode is on- chip.
3 -HO High Side Output. Connect to gate of High Side power MOSFET.-
4 HS High-Side Source connection. Connect to source of High Side power MOSFET. Connect negative -
side of bootstrap capacitor to this pin.
5 -HI High Side input.
6 -LI Low Side input.
7 VSS Chip negative supply, generally will be ground.
8 -LO Low Side Output. Connect to gate of Low-Side power MOSFET.
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MIC4103/4104
Absolute Maximum Ratings( )1
Supply Voltage (VDD, VHB – VHS) ..................... 0.3V to 18V
Input Voltages (VLI, VHI) ........................ 0.3V to V
DD + 0.3V
Voltage on LO (VLO) ............................. 0.3V to V
DD + 0.3V
Voltage on HO (VHO) ..................... VHS 0.3V to VHB + 0.3V
Voltage on HS (continuous) ............................. 1V to 110V
Voltage on HB .............................................................. 118V
Average Current in VDD to HB Diode ....................... 100mA
Junction Temperature (TJ) ........................ − ° °55 C to +150 C
Storage Temperature (Ts) ......................... − ° °60 C to +150 C
ESD Rating ................................................................. Note 3
Operating Ratings( )2
Supply Voltage (VDD) ........................................ +9V to +16V
Voltage on HS .................................................. 1V to 100V
Voltage on HS (repetitive transient) ................. 5V to 105V
HS Slew Rate ............................................................ 50V/ns
Voltage on HB and
VHS V............................................ HS + 8V to VHS + 16V
VDD .......................................... V
DD - 1V to VDD + 100V
Junction Temperature (TJ) ........................ 5 C 40°C to +12 °
Junction Thermal Resistance
-SOIC 8L (θJA) ................................................... 140°C/W
Electrical Characteristics( ) 4 5,
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA + = 25°C; unless noted. Bold values indicate40° ≤ °C TJ +125 C.
Symbol Parameter . . . Condition Min Typ Max Units
Supply Current
IDD VDD Quiescent Current LI = HI = 0V 40 150
200 µA
IDDO VDD Operating Current f = 500kHz 3.0 4.0 mA
IHB Total HB Quiescent Current LI = HI = 0V 25 150
200 µA
IHBO Total HB Operating Current f = 500kHz 1.5 2.5
3 mA
IHBS HB to V
SS Current, Quiescent VHS = VHB = 110V 0.05 1
30 µA
Input Pins: MIC4103 (CMOS Input)
VIL -Low Level Input Voltage Threshold 4
3 5.3 V
VIH
-High Level Input Voltage Threshold 5.7 7
8 V
VIHYS Input Voltage Hysteresis V 0.4
R
I -DInput Pull own Resistance 100 200 500 k Ω
Input Pins: MIC4104 (TTL Input)
VIL -Low Level Input Voltage Threshold
1.5 V
VIH
-High Level Input Voltage Threshold 1.5 2.2 V
R
I -DInput Pull own Resistance 100 200 500 k Ω
Undervoltage Protection
VDDR VDD Rising Threshold 6.5 7.4 8.0 V
VDDH VDD Threshold Hysteresis V 0.5
VHBR HB Rising Threshold 6.0 7.0 8.0 V
VHBH HB Threshold Hysteresis V 0.4
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5k in series with 100pF.
4. Specification for packaged product only
Electrical Characteristics(4 5, ) (Continued)
November 12, 2014 3 Revision 3.0
Micrel, Inc.
MIC4103/4104
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA + = 25°C; unless noted. Bold values indicate –40°C TJ +125°C.
Symbol
Parameter
Condition
Units
Bootstrap Diode
VDL -Low Current Forward Voltage IVDD-HB µA = 100 0.4 0.55
0.70 V
VDH
-High Current Forward Voltage IVDD-HB = 100mA 0.7 0.8
1.0 V
R
D Dynamic Resistance IVDD-HB = 100mA 1.0 1.5
2.0 Ω
LO Gate Driver
VOLL -Low Level Output Voltage I
LO = 160mA 0.18 0.3
0.4 V
VOHL -High Level Output Voltage ILO = 100mA, VOHL = VDD - VLO 0.25 0.3
0.45 V
IOHL Peak Sink Current VLO 3 A = 0V
IOLL Peak Source Current VLO 2 A = 12V
HO Gate Driver
VOLH -Low Level Output Voltage IHO
= 160mA 0.22 0.3
0.4 V
VOHH -High Level Output Voltage IHO
= 100mA, VOHH = VHB – VHO 0.25 0.3
0.45 V
IOHH
Peak Sink Current VHO 3 A = 0V
IOLH Peak Source Current VHO 2 A = 12V
Switching Specifications
tLPHL Lower Turn Off Propagation Delay -
(LI Falling to LO Falling) (MIC4103) 24 45 ns
tHPHL Upper Turn Off Propagation Delay -
(HI Falling to HO Falling) (MIC4103) 24 45 ns
tLPLH Lower Turn On Propagation- Delay
(LI Rising to LO Rising) (MIC4103) 24 45 ns
tHPLH Upper Turn On Propagation Delay -
(HI Rising to HO Rising) (MIC4103) 24 45 ns
tLPHL Lower Turn Off Propagation Delay -
(LI Falling to LO Falling) (MIC4104) 24 45 ns
tHPHL Upper Turn Off Propagation- Delay
(HI Falling to HO Falling) (MIC4104) 24 45 ns
tLPLH Lower Turn On Propagation Delay -
(LI Rising to LO Rising) (MIC4104) 24 45 ns
tHPLH Upper Turn On Propagation Delay -
(HI Rising to HO Rising) (MIC4104) 24 45 ns
tMON Delay Matching: Lower Turn-On and
Upper Turn- Off 3 8
10 ns
tMOFF Delay Matching: Lower Turn Off and -
Upper Turn- On 3 8
10 ns
tRC Output Rise Time CL = 1000pF 10 ns
tFC Output Fall Time C
L = 1000pF 6 ns
Electrical Characteristics(4 5, ) (Continued)
VDD = VHB = 12V; VSS = VHS = 0V; No load on LO or HO; TA + = 25°C; unless noted. Bold values indicate –40°C TJ +125°C.
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MIC4103/4104
Symbol Parameter . . . Condition Min Typ Max Units
Switching Specifications (Continued)
tR Output Rise Time (3V to 9V) CL µF = 0.1 0.4 0.6
0.8 µs
tF Output Fall Time (3V to 9V) C
L µF = 0.1 0.2 0.3
0.4 µs
tPW Minimum Input Pulse Width that
Changes the Output Note 6 50 ns
tBS Bootstrap Diode Turn- On or
Turn- Off Time 10 ns
Notes:
5. All voltages relative to Pin 7, VSS unless otherwise specified
6. Guaranteed by design. Not production tested.
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MIC4103/4104
Timing Diagrams
Note:
All propagation delays are measured from the 50% voltage level.
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MIC4103/4104
Typical Characteristics
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MIC4103/4104
Typical Characteristics (Continued)
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MIC4103/4104
Functional Diagram
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MIC4103/4104
Functional Description
The MIC4103 is a high voltage, non inverting, dual - -
MOSFET driver that is designed to independently drive
both high side and low Channel MOSFETs. The - - -side N
block diagram of the MIC4103 is shown in the Functional
Diagram.
Both drivers contain an input buffer with hysteresis, a
UVLO circuit and an output buffer. The high-side output
buffer includes a high speed level- -shifting circuit that is
referenced to the HS pin. An internal diode is used as
part of a bootstrap circuit to provide the drive voltage for
the high-side output.
Startup and UVLO
The UVLO circuit forces the driver output low until the
supply voltage exceeds the UVLO threshold. The low-
side UVLO circuit monitors the voltage between the VDD
and VSS pins. The high side UVLO circuit monitors the -
voltage between the HB and HS pins. Hysteresis in the
UVLO circuit prevents noise and finite circuit impedance
from causing chatter during turn-on.
Input Stage
The MIC4103 and MIC4104 have different input stages,
which lets these parts cover a wide range of driver
applications. Both the HI and LI pins are referenced to
the VSS pin.
The MIC4103 has a high impedance, CMOS compatible -
input threshold and is recommended for applications
where the input signal is noisy or where the input signal
swings the full range of voltage (from VDD to GND). There
is typically 400mV of hysteresis on the input pins
throughout the VDD range. The hysteresis improves noise
immunity and prevents input signals with slow rise times
from falsely triggering the output. The threshold voltage
of the MIC4103 varies proportionally with the VDD supply
voltage.
The amplitude of the input signal affects the VDD supply
current. VIN voltages that are a diode drop less than the
VDD supply voltage will cause an increase in the VDD pin
current. The graph in Figure 1 shows the typical
dependence between IVDD and VIN for VDD = 12V.
Figure 1. MIC4103 Supply Current vs. Input Voltage
The MIC4104 has a TTL compatible input range and is
recommended for use with inputs signals whose
amplitude is less than the supply voltage. The threshold
level is independent of the VDD supply voltage and there
is no dependence between IVDD and the input signal
amplitude with the MIC4104. This feature makes the
MIC4104 an excellent level translator that will drive high
threshold MOSFETs from a low voltage PWM IC.
Low- Side Driver
A block diagram of the low side driver is shown in - Figure
2. The low-side driver is designed to drive a ground (VSS
pin) referenced N-channel MOSFET. Low driver
impedances allow the external MOSFET to be turned on
and off quickly. The rail rail drive capability of the - -to
output ensures full enhancement of the external
M OSFET.
A high level applied to LI pin causes the upper driver FET
to turn on and VDD voltage is applied to the gate of the
external MOSFET. A low level on the LI pin turns off the
upper driver and turns on the low side driver to ground
the gate of the external MOSFET.
Figure 2 -Si. Low de Driver Block Diagram
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MIC4103/4104
High-Side Driver and Bootstrap Circuit
A block diagram of the high side driver and bootstrap -
circuit is shown in is driver is designed to drive Figure 3. Th
a floating N channel MOSFET, whose source terminal is -
referenced to the HS pin.
Figure 3 -. High Side Driver and Bootstrap Circuit Block
Diagram
A low-power, high-speed, level shifting circuit isolates the
low- -side (VSS pin) referenced circuitry from the high side
(HS pin) referenced driver. Power to the high side driver -
and UVLO circuit is supplied by the bootstrap circuit while
the voltage level of the HS pin is shifted high.
The bootstrap circuit consists of an internal diode and
external capacitor, CB. In a typical application, such as the
synchronous buck converter shown in , the HS pFigure 4 in
is at ground potential while the low side MOSFET is on. -
The internal diode allows capacitor CB to charge up to
VDD VD during this time (where VD is the forward voltage
drop of the internal diode). After the low side MOSFET is -
turned off and the HO pin turns on, the voltage across
capacitor CB is applied to the gate of the upper external
MOSFET. As the upper MOSFET turns on, voltage on the
HS pin rises with the source of the high side MOSFET until -
it reaches VIN . As the HS and HB pin rise, the internal
diode is reverse biased preventing capacitor CB from
discharging.
Figure 4 - . High Side Driver and Bootstrap Circuit
Power Dissipation Considerations
Power dissipation in the driver can be separated into three
areas:
Internal diode dissipation in the bootstrap circuit
Internal driver dissipation
Quiescent current dissipation used to supply the internal
logic and control functions.
Bootstrap Circuit Power Dissipation
Power dissipation of the internal bootstrap diode primarily
comes from the average charging current of the CB
capacitor times the forward voltage drop of the diode.
Secondary sources of diode power dissipation are the
reverse leakage current and reverse recovery effects of
the diode.
The average current drawn by repeated charging of the
high- : side MOSFET is calculated by Equation 1
IF(AVE) = QGATE × fS Eq. 1
Where:
QGATE = Total Gate charge at VHB
fS = Gate drive switching frequency
The average power dissipated by the forward voltage drop
of the diode equals as shown in Equation 2 :
FWD
DIODE
P
= IF(AVE) × VF Eq. 2
Where:
VF - = Diode forward voltage drop.
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MIC4103/4104
The value of VF should be taken at the peak current
through the however, this current is difficult to diode;
calculate because of differences in source impedances.
The peak current can either be measured or the value of
VF at the average current can be used and will yield a good
approximation of diode power dissipation.
The reverse leakage current of the internal bootstrap diode
is typically 11µA at a reverse voltage of 100V and 125°C.
Power dissipation due to reverse leakage is typically much
less than 1mW and can be ignored.
Reverse recovery time is the time required for the injected
minority carriers to be swept away from the depletion
region during turn off of the diode. Power dissipation due -
to reverse recovery can be calculated by computing the
average reverse current due to reverse recovery charge
times the reverse voltage across the diode.
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MIC4103/4104
Application Information
The average reverse current and power dissipation due to
reverse recovery can be estimated by:
IRR(AVE) = 0.5 × t × fS
RR
DIODE
P
= IRR(AVE) × VREF Eq. 3
Where:
IRRM = Peak reverse recovery current
The total diode power dissipation is:
DIODERRDIODEFWDDIODE
PPP TOTAL
+=
Eq. 4
An optional external bootstrap diode may be used instead
of the internal diode (Figure ). An external diode may be 5
useful if high gate charge MOSFETs are being driven and
the power dissipation of the internal diode is contributing to
excessive die temperatures. The voltage drop of the
external diode must be less than the internal diode for this
option to work. The reverse voltage across the diode will
be equal to the input voltage minus the VDD supply voltage.
A 100V Schottky diode will work for most 72V input
telecom applications. The above equations can be used to
calculate power dissipation in the external diode, however,
if the external diode has significant reverse leakage
current, the power dissipated in that diode due to reverse
leakage can be calculated as:
)D1(VIP REVRDIODEREV ××=
Eq. 5
Where:
IR = Reverse current flow at VREV and TJ
VREV
= Diode reverse voltage
D = Duty cycle = tON / fS
fS = Power supply switching frequency
The on time is the time the high side switch is conducting. - -
In most power supply topologies, the diode is reverse
biased during the switching cycle off- time.
Figure 5. Optional Bootstrap Diode
Gate Driver Power Dissipation
Power dissipation in the output driver stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 6 shows a simplified equivalent circuit of the
MIC4103 driving an external MOSFET.
Figure 6. MIC4103 Driving an External MOSFET
Dissipation during the External MOSFET Turn-On
Energy from capacitor CB is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The energy
delivered to the MOSFET is dissipated in the three
resistive components, RON, RG, and RG_FET. RON is the on
resistance of the upper driver MOSFET in the MIC4103.
RG is the series resistor (if any) between the driver IC and
the MOSFET. RG_FET is the gate resistance of the
MOSFET. RG_FET is usually listed in the power MOSFET’s
specifications. The ESR of capacitor CB and the resistance
of the connecting trace can be ignored since they are
much less than RON and RG_FET.
The effective capacitance of CGD and CGS is difficult to
calculate since they vary non linearly with I- D, VGS, and VDS.
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MIC4103/4104
Fortunately, most power MOSFET specifications include a
typical graph of total gate charge vs. VGS. Figure 7 shows
a typical gate charge curve for an arbitrary power
MOSFET. This chart shows that for a gate voltage of 10V,
the MOSFET requires about 23.5nC of charge. The energy
dissipated by the resistive components of the gate drive
circuit during on is calculated as:turn-
2
GSISS VC
2
1
E××=
Eq. 6
but,
Q = C × V
so,
GSG
VQ
2
1
E×
×=
Eq. 7
Where:
CISS is the total gate capacitance of the MOSFET
Figure 7. Typical Gate Charge vs. VGS
The same energy is dissipated by ROFF, RG, and RG_FET
when the driver IC turns the MOSFET off. Assuming RON is
approximately equal to ROFF, the total energy and power
dissipated by the resistive drive elements is:
EDRIVER = QG × VGS
and,
PDRIVER = QG × VGS × fS
W : here
EDRIVER = Energy dissipated per switching cycle.
PDRIVER = Power dissipated by switching the MOSFET
on and off.
QG = Total gate charge at VGS.
VGS = the gate- - to source voltage on the MOSFET.
fS = Switching frequency of the gate drive circuit.
The power dissipated inside the MIC4103/4 is equal to the
ratio of RON and ROFF Rto the external resistive losses in G
and RG_FET. Letting RON = ROFF, the power dissipated in the
MIC4103 due to driving the external MOSFET is:
FET_GGON
ON
DRIVERDISS RRR
R
PP DRIVE ++
=
Eq. 8
Supply Current Power Dissipation
Power is dissipated in the MIC4103 even if there is nothing
being driven. The supply current is drawn by the bias for
the internal circuitry, the level shifting circuitry, -and shoot
through current in the output drivers. The supply current is
proportional to operating frequency and the VDD and VHB
voltages. The typical characteristic graphs show how
supply current varies with switching frequency and supply
voltage.
The power dissipated by the MIC4103 due to supply
current is:
HBHBDDDDDISS
IVIVP
SUPPLY
×+×=
Eq. 9
Total Power Dissipation and Thermal Considerations
Total power dissipation in the MIC4103 or MIC4104 is
equal to the power dissipation caused by driving the
external MOSFETs, the supply current, and the internal
bootstrap diode.
TOTALDRIVESUPPLYTOTAL DIODEDISSDISSDISS PPPP ++=
Eq. 10
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MIC4103/4104
The die temperature may be calculated once the total
power dissipation is known.
JADISSAJ TOTAL
PTT θ×+=
Eq. 11
Where:
TA = Maximum ambient temperature.
TJ = Junction temperature (°C)
TOTAL
DISS
P
= Power dissipation of the MIC4103/4.
θJC - -= Thermal resistance from junction to ambient air
( °C/W)
Propagation Delay and Delay Matching and other
Timing Considerations
Propagation delay and signal timing is an important
consideration in a high performance power supply. The -
MIC4103 is designed not only to minimize propagation
delay but to minimize the mismatch in delay between the
high- - side and low side drivers.
Fast propagation delay between the input and output drive
waveform is desirable. It improves overcurrent protection
by decreasing the response time between the control
signal and the MOSFET gate drive. Minimizing
propagation delay also minimizes phase shift errors in
power supplies with wide bandwidth control loops.
Many power supply topologies use two switching
MOSFETs operating 180 out of phase from each other. °
These MOSFETs must not be on at the same time or a
short circuit will occur, causing high peak currents and
higher power dissipation in the MOSFETs. The MIC4103
and MIC4104 output gate drivers are not designed with
anti shoot- -through protection circuitry. The output drive
signals simply follow the inputs. The power supply design
must include timing delays (dead time) between the input -
signals to prevent shoot-through.
The MIC4103 and MIC4104 drivers specify delay
matching between the two drivers to help improve power
supply performance by reducing the amount of dead-time
required between the input signals.
Care must be taken to insure the input signal pulse width
is greater than the minimum specified pulse width. An
input signal that is less than the minimum pulse width may
result in no output pulse or an output pulse whose width is
significantly less than the input.
The maximum duty cycle (ratio of high side on- -time to
switching period) is controlled by the minimum pulse width
of the low side and by the time required for the CB
capacitor to charge during the off- time.
Adequate time must be allowed for the CB capacitor to
charge up before the high side driver is turned on.-
Decoupling and Bootstrap Capacitor Selection
Decouplin side g capacitors are required for both the low-
(VDD) and high side (HB) supply pins. These capacitors -
supply the charge necessary to drive the external
MOSFETs as well as minimize the voltage ripple on these
pins. The capacitor from HB to HS serves double duty by
providing decoupling for the high uitry as well as -side circ
providing current to the high side circuit while the high- -side
external MOSFET is on. ceramic capacitors are
recommended because of their low impedance and small
size. Z5U type ceramic capacitor dielectrics are not
recommended due to the large change in capacitance over
temperature and voltage. A minimum value of 0.1µf is
required for each of the capacitors, regardless of the
MOSFETs being driven. Larger MOSFETs may require
larger capacitance values for proper operation. The
voltage rating of the capacitors depends on the supply
voltage, ambient temperature, and the voltage derating
used for reliability. 25V rated X5R or X7R ceramic
capacitors are recommended for most applications. The
minimum capacitance value should be increased if low-
voltage capacitors are used since even good quality
dielectric capacitors, such as X5R, will lose 40% to 70% of
their capacitance value at the rated voltage.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the V pins. The bootstrap DD and VSS
capacitor (CB) for the HB supply pin must be located as
close as possible between the HB and HS pins. The trace
connections must be short, wide, and direct. The use of a
ground plane to minimize connection impedance is
recommended. Refer to Grounding, Component
Placement, and Circuit Layout section for more
information.
The voltage on the bootstrap capacitor drops each time it
delivers charge to turn on the MOSFET. The voltage drop
depends on the gate charge required by the MOSFET.
Most MOSFET specifications specify gate charge vs. VGS
voltage. Based on this information and a recommended
ΔVHB of less than 0.1V, the minimum value of bootstrap
capacitance is calculated as:
HB
GATE
B
V
Q
C
Eq. 12
Where:
QGATE = Total gate charge at VHB.
HB = Voltage drop at the HB pin.
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MIC4103/4104
The decoupling capacitor for the VDD input can be
calculated with the same formula; however, the two
capacitors are usually equal in value.
Grounding, Component Placement, and Circuit Layout
Nanosecond switching speeds and ampere peak currents
in and around the MIC4103 and MIC4104 drivers require
proper placement and trace routing of all components.
Improper placement may cause degraded noise immunity,
false switching, excessive ringing or circuit latch-up.
Figure 8 shows the critical current paths when the driver
outputs go high and turn on the external MOSFETs. It also
helps demonstrate the need for a low impedance ground
plane. Charge needed to turn on the MOSFET gates -
comes from the decoupling capacitors CVDD and CB.
Current in the low side gate driver flows from C- VDD through
the internal driver, into the MOSFET gate and out the
Source. The return connection back to the decoupling
capacitor is made through the ground plane. Any
inductance or resistance in the ground return path causes
a voltage spike or ringing to appear on the source of the
MOSFET. This voltage works against the gate drive
voltage and can either slow down or turn off the MOSFET
during the period where it should be turned on.
Current in the high side driver is sourced from capacitor C- B
and flows into the HB pin and out the HO pin, into the gate
of the high side MOSFET. The return path for the current
is from the source of the MOSFET and back to capacitor
CB. The high eturn path usually does not have -side circuit r
a low impedance ground plane so the trace connections in
this critical path should be short and wide to minimize
parasitic inductance.
As with the low-side circuit, impedance between the
MOSFET source and the decoupling capacitor causes
negative voltage feedback which fights the turn on of the -
MOSFET.
It is important to note that capacitor CB must be placed
close to the HB and HS pins. This capacitor not only
provides all the energy for turn on but it must also keep HB -
pin noise and ripple low for proper operation of the high-
side drive circuitry.
Figure 8. Turn On Current Paths-
Figure 9 shows the critical current paths when the driver
outputs go low and turn off the external MOSFETs. Short,
low impedance connections are important during turn-off
for the same reasons given in the turn -on explanation.
Remember that during turn off current flowing through the -
internal diode replenishes charge in the bootstrap
capacitor (CB).
Figure 9. Turn-O Current Paths
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MIC4103/4104
The following circuit guidelines should be adhered to for
optimum circuit performance:
1. The VDD and HB bypass capacitors must be placed
close to the supply and ground pins. It is critical that
the trace length between the high side decoupling
capacitor (CB) and the HB & HS pins be minimized to
reduce trace inductance.
2. A ground plane should be used to minimize parasitic
inductance and impedance of the return paths. The
MIC4103 is capable of greater than 2A peak currents
and any impedance between the MIC4103, the
decoupling capacitors, and the external MOSFET will
degrade the performance of the driver.
3. Trace out the high di/dt and dv/dt paths (as shown in
Figure 8 Figure 9 and ) and minimize trace length and
loop area for these connections. Minimizing these
parameters decreases the parasitic inductance and
the radiated EMI generated by fast rise and fall times.
Figure 10. Synchronous Buck Converter Power Stage
A typical layout of a synchronous buck converter power
stage ( ) is shown in Figure 10 Figure 11.
The circuit is configured as a synchronous buck power
stage. The high side MOSFET drain connects to the input -
supply voltage and the source connects to the switching
node. The low side MOSFET drain connects to the -
switching node and its source is connected to ground. The
buck converter output inductor (not shown) would connect
to the switching node. The high side drive trace, HO, is -
routed on top of its return trace, HS, to minimize loop area
and parasitic inductance. The low side drive trace LO is -
routed over the ground plane which minimizes the
impedance of that current path. The decoupling capacitors,
CB and CVDD are placed to minimize trace length between
the capacitors and their respective pins.
This close placement is necessary to efficiently charge
capacitor CB when the HS node is low. All traces are
0.025” wide or greater to reduce impedance. CIN is used to
decouple the high current path through the MOSFETs.
Figure 11. Typical Layout of a Synchronous Buck Converter
Power Stage
November 12, 2014 17 Revision 3.0
Micrel, Inc.
MIC4103/4104
Package Information and Recommended Landing Pattern( )7
8-Pin (M) SOIC
Note:
7. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
November 12, 2014 18 Revision 3.0
Micrel, Inc.
MIC4103/4104
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944 0800 FAX +1 (408) 474- -1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced
- -mixed signal, analog & power semiconductors; high
performance communication, clock
management,
MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs.
Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp
uter products.
Corporation headquarters and state
- - -of the art waf
er fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia.
Additionally, the Company maintains an extensive network
of distribut
ors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the inf
ormation furnished in this data
sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for
its use.
Micrel reserves the right to change circuitry
specifications and descriptions at any time without notice.
No license, whether express, implied, arising by estoppel or otherwise, to any intellectua
property rights
Eis granted by this document.
xcept as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including
liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
, or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a produc
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgica
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to full
indemnify Micrel
for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
November 12, 2014 19 Revision 3.0


Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: MIC4103

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