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 2016 Microchip Technology Inc. DS20005586B-page 1

MD1730

Features

• 8-Channel Ultrasound Continuous Waveform

(CW) Transmitter with Integrated Beamformer

• CW Output ±1V to ±6Vp-p with Low RON

• -160 dbc/Hz Ultra-Low Phase Noise at 1 kHz

Offset and 5 MHz

• 8-Bit Programmable Per-Channel Beamforming

Phase Delay

• 8-Bit Programmable Dividers for CW Frequency

with Input Clock Frequency up to 250 Mhz

• Input Clock Compatible with LVDS/SSTL or

Single-Ended LVCMOS

• LVCMOS 2.5V Logic for the Control I/O pins

• Fast SPI Interface Supports up to 200 MHz

• SPI Interface Supports Daisy Chaining and

Broadcasting Mode

Applications

• Medical Ultrasound Imaging System for

Cardiovascular Application

• Ultrasound Fetal Heart Monitoring Device

• Ultrasound Flow Meter

• Programmable Array Pattern Generator

General Description

The MD1730 is an 8-channel ultra-low phase noise CW

transmitter with integrated beamformer. It is designed

for medical ultrasound imaging systems requiring

high-performance CW Doppler mode. The MD1730

has a dedicated signal path designed to minimize

phase noise to the output. In addition, it has a

high-speed SPI interface that enables CW

beamforming features. The outputs of the MD1730 can

swing up to ±6V and each output has a separate

programmable phase delay. Additionally, by

programming the internal frequency divider register,

the MD1730 can output different CW frequencies from

a single clock source. For instance, when the input

clock frequency is 160 MHz and the frequency divider

is set to 16, an output CW frequency of 5 MHz can be

obtained with a phase delay step size of 6.25 ns, which

translates to an angular resolution of 11.25 degrees.

Package Type

CLKN

VLL

CBE1

SDO

CKB1

SPIB

CBE0

CKB0

GND

CLKP

GND

TXRW

VGP

MD1730

6x6x0.9 mm 36-lead VQFN*

* Includes Exposed Thermal Pad (EP); see Table 3-1.

VDD

SCK

CSN

SDI

11 1512 13 14 181716

36 35 3134 33 28293032

VGN

CNF

VCW-

CPF

CW+

CW2

CW3

CW0

CW1

VGN

CW4

CW5

CW6

CW7

CNF

VCW-

CPF

VCW+

8-Channel Ultra-Low Phase Noise

Continuous Waveform Transmitter with Beamformer

MD1730

DS20005586B-page 2  2016 Microchip Technology Inc.

Block Diagram

0 to +

VC W+

C W0

VP F

VNF

+10V

VG P

E N

+2.5V

VL L

TXR W

S P IB

S DI

C S N

S C K

C L K N

C L K P

LVDS / S S T L

C loc k Input

S P I

R egis ters

G ND

C W1

MD1730

Thermal

P ad

-10V

S UB

V L L

C L K

C K B 0

C W7

VP F

VNF

0 to -

VC W-

VCW +

VCW -

HIZ[7: 0]

C P F

VP F

VNF

C NF

S DO

MS B

C K B 1

C B E 1

V L L

C B E 0

+5V

VDD

VG N

C L K

P HD 7~0[7: 0] C WF D[7: 0]

P HD1[7: 0] C WF D[7: 0]

E NAE NA

C L K C L K

P HD7[7: 0] C WF D[7: 0]

E NA

C L K C L K

C L K

S C K

VCW +

VCW -

1uF

1uF 2.2uF

2.2uF

1uF

P HD0[7: 0] C WF D[7: 0]

E NA

C L K C L K

C W2

C W3

C W4

C W5

C W6

 2016 Microchip Technology Inc. DS20005586B-page 3

MD1730

MD1730 CW Output via HV2201 Application Block Diagram

+10V

+2 to +6V

VCW+

CW0

VPF

VNF

+2.5V

TXRW

SPIB

SDI

CSN

SCK

CLKN

CLKP

LVDS / SSLT

Clock Input

SPI

Registers

GND

CW1

MD1730

Thermal

Pad

-10V

SUB

VLL

CLK

CKB0

CW7

VPF

VNF

-2 to -6V

VCW-

VCW+

VCW-

HIZ[7:0]

CPF

VPF

VNF

CNF

SDO

MSB

CKB1

CBE1

VLL

CBE0

+5V

CLK

PHD7~0[7:0] CWFD[7:0]

PHD1[7:0] CWFD[7:0]

ENAENA

CLK CLK

PHD7[7:0] CWFD[7:0]

ENAENA

CLK CLK

PHD0[7:0] CWFD[7:0]

ENAENA

CLK CLK

CLK

SCK

VCW+

VCW-

XDCR

SW0

SW1

SW2

SW6

SW7

CLK

8-BIT

SHIFT

DIN

DOUT

LEVEL

SHIFTERS

OUTPUT

SWITCHES

VNN VPP CLR LE GND VDD

LATCHES

TX7

SEL

POS

NEG

B/CW

LVL[3:2]

POS[3:2]

NEG[3:2]

VDD2

High Speed

Gate Buers

VDD2

VDD1

VSS

VDD1

High Speed

Gate Buers

Control

Logic and

Level

Transla-

tion

GND

MD1715

1 of 2-ch

TC8020

6 of 12-FET

+10V

VDD2

+10V

VDD1

+10V

AVD D

+90V

SP1

+50V

SP2

-90V

SN1

-50V

DP1

DN1

DP2

DN2

SN2

SP3

SN3

DP3

DN3

GP1

GN1

GP2

GN2

GP3

GN3

OP1

ON1

OP2

ON2

OP3

ON3

-10V

VSS

-10V

AVSSPADGND PAD VSUB

TX0

VDD2

High Speed

Gate Buers

VDD2

VDD1

VSS

VDD1

High Speed

Gate Buers

Control

Logic and

Level

Transla-

tion

MD1715

1 of 2-ch

TC8020

6 of 12-FET

+10V

VDD2

+10V

VDD1

+10V

AVD D

+90V

SP1

+50V

SP2

-90V

SN1

-50V

DP1

DN1

DP2

DN2

SN2

SP3

SN3

DP3

DN3

GP1

GN1

GP2

GN2

GP3

GN3

OP1

ON1

OP2

ON2

OP3

ON3

-10V

VSS

-10V

AVSSPADGND PAD VSUB

HV2201

8-ch HV Analog Switch

SEL

POS

NEG

B/CW

LVL[1:0]

POS[1:0]

NEG[1:0]

GND

B/CW LE +3.3V-100V +100V

CW/ B

CW_START

FPGA

MD1730

DS20005586B-page 4  2016 Microchip Technology Inc.

NOTES:

 2016 Microchip Technology Inc. DS20005586B-page 5

MD1730

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Positive Logic Supply (VLL)........................................................................................................................ -0.5V to +3.0V

Positive Supply Voltage (V

DD ).................................................................................................................... -0.5V to +6.0V

Positive Supply Voltage (V

GP ).................................................................................................................. -0.5V to +13.5V

Negative Supply Voltage (VGN)................................................................................................................ +0.5V to -13.5V

CW Output Positive Supply Voltage (VCW+) ............................................................................................... -0.5V to +12V

CW Output Negative Supply Voltage (VCW-)............................................................................................... +0.5V to -12V

All Digital Inputs (VIN)................................................................................................................................. -0.5V to +3.0V

CW Outputs (VOUT)...................................................................................................................................... -12V to +12V

Operating Ambient Temperature ................................................................................................................. 0°C to +85°C

Maximum Junction Temperature ................................................................................................................. 0°C to +85°C

Storage Temperature ............................................................................................................................................ +125°C

Thermal Resistance Junction to Ambient (Ɵ

JA, JESD51-5)..................................................................................25°C/W

Thermal Resistance Junction to Bottom Cu Pad (Ɵ

JB, JESD51-5) ....................................................................6.4°C/W

Thermal Resistance Junction to Package Top (ƟJC, JESD51-5).......................................................................13.5°C/W

ESD Rating All Pins ............................................................................................................................................. ±1.0 kV

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in the

operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods

may affect device reliability.

TABLE 1-1: INPUT/OUTPUT PIN DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, VLL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Operating Supply

Logic Supply Voltage VLL 2.35 2.50 2.65 V (VGP+|VCW-|) ≥10V

(VGN+|VCW+|) ≥10V

= 0 to +85°C, Note 2

VDD Supply Voltage VDD 4.75 5.0 5.25 V

Positive Supply Voltage VGP 8.0 10 12 V

Negative Supply Voltage VGN -12 -10 -8.0 V

CW Output Positive Supply VCW+ 1.0 — 6.0 V

CW Output Negative Supply V

CW- -6.0 — -1.0 V

VLL Quiescent Current I

LLQ — 0.02 0.1 mA EN = 0, f

CLK = fSCK = 0

All logic input no transit

VDD Quiescent Current IDDQ — 0.15 0.2 mA

VGP Quiescent Current IGPQ — 1.0 2.0 µA

VGN Quiescent Current IGNQ — 33 45 µA

VCW+ Quiescent Current I

CW+Q — 26 45 µA

VCW- Quiescent Current I

CW-Q — 6 10 µA

VLL Enabled Current ILLEN — 6.0 9.0 mA EN = 1, f

SCK = 120 MHz

TXRW = 0, SDI = 0,

SDO no load.

VDD Enabled Current IDDEN — 0.2 0.3 mA

VGP Enabled Current IGPEN — 2.0 3.0 mA

VGN Enabled Current IGNEN — 2.0 3.0 mA

VCW+ Enabled Current I

CW+EN — 2.0 3.0 mA

VCW- Enabled Current I

CW-EN — 2.0 3.0 mA

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

MD1730

DS20005586B-page 6  2016 Microchip Technology Inc.

VLL Current at CW 5MHz ILL5 — 2.5 3.0 mA EN = 1, fCLK = 80 MHz,

TXRW = 1, CW 5 MHz,

no load 8-channel

VDD Current at CW 5MHz IDD5 — 1.0 2.0 mA

VGP Current at CW 5MHz IGP5 — 6.0 10 mA

VGN Current at CW 5MHz IGN5 — 12 18 mA

VCW+ Current at CW 5MHz ICW+5 — 26 35 mA

VCW- Current at CW 5MHz ICW-5 — 21 30 mA

SPI & Logic

Input Logic High Voltage VIH 0.8 VLL — VLL V 2.5V LVCMOS

Input Logic Low Voltage V

IL 0 — 0.2 VLL V

Input Logic High Current IIH — — 1.0 µA

Input Logic Low Current I

IL — — µA

SPI and Logic Input Capacitance C

IN — 4.5 — pF Note 1

Output Logic High Current I

OH — — mA 2.5V LVCMOS

Output Logic Low Current IOL — — mA

SDO Output Logic High Voltage VOH — — V with 5 pF load

SDO Output Logic Low Voltage V

OL — — 0.35 V

TABLE 1-2: SPI AND LOGIC AC ELECTRICAL SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Output Rise Time tr— 0.65 — ns 1.5 pF load, Note 1

Output Fall Time tf— 0.65 —

Output Rise Propagation Delay t

dr — 2.8 — ns CLK rise 50% to output

50%, after latency.

Note 1

Output Fall Propagation Delay tdf — 3.0 —

Delay Time Matching tdm — ±0.5 ±1.0 ns Channel to channel,

Note 1, fCLK = 80 MHz

SDI Valid to SCK, Setup Time t

10.6 1.0 — ns Note 1

SCK To SDI Data Hold Time t

22.0 — — ns

SCK High Time % of 1/fCLK t345 — 55 % Note 2

SCK Low Time % of 1/fCLK t445 — 55 %

CSN Hi-Time t52-cycle — — SCK Note 2

SCK Rise to CSN Rise t6— 2.0 — ns Note 1

CSN Low to SCK Rise t7— 0.8 — ns

SDO Valid from SCK Rise t8— 3.1 4.0 ns SPIB = 0, 1.5 pF Load,

Note 1

CSN Rise to SCK Rise t9— 2.0 — ns Note 1

CSN Rise to TXRW or SPIB Rise t10 9-cycle SCK Note 2

TXRW or SPIB Fall to CSN Fall t11 1-cycle

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

TABLE 1-1: INPUT/OUTPUT PIN DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

 2016 Microchip Technology Inc. DS20005586B-page 7

MD1730

SDO to SDI Valid Delay t12 — 2.3 3.0 ns SPIB = 1, 1.5 pF Load,

Note 1

TXRW Rise to CLKP Rise t13 — 2.5 — ns Note 1

Latency to CW Wave Rise t14 2-cycle CLK After TXRW = 1,

PHD=0, Note 2

Latency CSN Rise to TXRW Fall t15 2-cycle — — CLK Note 2

SCK Clock Frequency fSCK — — 200 MHz Note 1

EN Off Time tEN-Off — 20 30 ns Note 2

EN On Time tEN-On — 150 300 µs 2.0 µF on CPF/CNF,

Note 2

TABLE 1-3: CLOCK BUFFER OUTPUTS AC/DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Clock Output Frequency

Range

fCKB 40 160 250 MHz Note 1

Clock Output Duty Cycle D% 45 — 55 % Note 2

CKB0,1 Rise Time trb — 0.6 1.0 ns fCLK = 80 Mhz, 1.5 pF

load, Note 1

CKB0,1 Fall Time tfb — 0.5 1.0

Output Rise Propagation

Delay

tdrb — 2.0 3.0 ns CLK rise to CKB, 50%,

Note 1

Output Fall Propagation

Delay

tdfb — 2.0 3.0

CBE Enable Time tcbe — 2.1 3.0 CBE to CLK rise, 50%,

Note 1

CKB0,1 Output logic high VOHCKB — VLL — V Note 2

CKB0,1 Output Logic low VOLCKB — GND — V Note 2

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

TABLE 1-4: CW OUTPUTS DC/AC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

CW Output Peak to Peak Voltage VCWOUT -6.0 - +6.0 V

CW Output Rise Propagation Delay tdrCW — 4.0 6.0 ns TxCLK 50% to CWx

10%, after latency,

Note 1

CW Output Fall Propagation Delay tdfCW — 4.0 6.0

CW Output Maximum Current ICW± ±250 ±300 — mA VCW± = ±5.0V, 0.1Ω

load, Note 1

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

TABLE 1-2: SPI AND LOGIC AC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

MD1730

DS20005586B-page 8  2016 Microchip Technology Inc.

Static Output Resistance PFET RONCW — 7.5 12 ΩRON at VCW± = ±5.0V,

ICW± = ±100 mA load,

Note 1

Static Output Resistance NFET — 6.5 11

Change in RDS(ON) with

Temperature

∆RONCW — — 1.0 %/C VCW± = ±5.0V, Note 2

CW Phase Resolution REPhase — 1 — CLK Note 2

CW Phase Noise NPhase — -160 — dBC/

CW 5 MHz,

1 kHz Offset, Note 1

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

TABLE 1-4: CW OUTPUTS DC/AC ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

TABLE 1-5: LVDS / SSTL CLOCK INPUTS AC / DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

LL = +2.5V, VGP = +10V, VGN = -10V, VCW+ = +6.0V,

VCW- = -6.0V, VDD = +5V, TA= 25°C.

Parameters Sym. Min. Typ. Max. Units Conditions

CLKP/CLKN Clock Frequency fCLK 40 160 250 MHz Note 1

Clock Input Slew Rate tCSR 1.0 — — V/ns Note 2

Control/Data Input Slew Rate tDSR 1.0 — — V/ns

Single Ended Clock Input

SSTL Reference Voltage VREFS 1.13 1.25 1.38 V Note 1

DC Input Logic High VIH(DC) VREFS +0.15 — VLL +0.3 V Note 1

DC Input Logic Low VIL(DC) -0.3 — VREFS -0.15 V Note 1

AC Input Logic High VIH(AC) VREFS +0.31 — — V VREF = 0.5VLL, Slew

rate 1.0 V/ns, Note 1

AC Input Logic Low V

IL(AC) - — VREFS -0.31 V

Differential Clock Input

AC Differential Cross Point VX(AC) 0.5VLL -0.2 — 0.5VLL+0.2 V CLK and CLK, Note 1

DC Input Max Swing Voltage VSWING(DC) 0.3 — VLL +0.6 V Note 1

AC Differential Input Voltage VSWING(AC) 0.62 — VLL +0.6 V Note 1

DC Input Signal Voltage VIN(DC) -0.3 — VLL +0.3 V Note 1

CLKP/CLKN Slew Rate SLEW 1.0 — — V/ns Note 2

Note 1: Characterized only; not 100% tested in production.

2: Design Guidance Only (DGO).

 2016 Microchip Technology Inc. DS20005586B-page 9

MD1730

NOTES:

MD1730

DS20005586B-page 10  2016 Microchip Technology Inc.

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: IDD vs. Temperature.

FIGURE 2-2: IVGP vs. Temperature.

FIGURE 2-3: IVCW+ vs. Temperature.

FIGURE 2-4: IVLL vs. Temperature.

FIGURE 2-5: IVGN vs. Temperature.

FIGURE 2-6: IVCW- vs. Temperature.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VDD = 5.0V,

fCLK = 80 MHz,

fCW = 5 MHz,

8-ch, no-load

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VGP = 10V,

fCLK= 80 MHz,

fCW = 5 MHz,

8-ch, no-load

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VCW+ = 5V,

fCLK= 80 MHz,

fCW = 5 MHz,

8-ch, no-load

0.5

1.5

2.5

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VDD = 2.5V,

fCLK= 80 MHz,

fCW = 5 MHz,

8-ch, no-load

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VGN = -10V,

fCLK= 80 MHz,

fCW = 5 MHz,

8-ch, no-load

0 10 20 30 40 50 60 70 80 90 100

Current (mA)

Temperature (°C)

VCW- = -5V,

fCLK= 80 MHz,

fCW = 5 MHz,

8-ch, no-load

 2016 Microchip Technology Inc. DS20005586B-page 11

MD1730

FIGURE 2-7: IVDD vs. CW Output

Frequency.

FIGURE 2-8: IVCW+ vs. CW Output

Frequency.

FIGURE 2-9: IVCW- vs. CW Output

Frequency.

FIGURE 2-10: IVLL vs. CW Output

Frequency.

FIGURE 2-11: IVGN vs. CW Output

Frequency.

FIGURE 2-12: IVGP vs. CW Output

Frequency.

0.5

1.5

2.5

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

VDD = 5V,

8-ch, 220 pF,

1 kȍ

100

150

200

250

300

350

400

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

VCW+ = 5V,

8-ch, 220 pF,

1 kȍ

100

150

200

250

300

350

400

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

VCW- = -5V,

8-ch, 220 pF,

1 kȍ

0.5

1.5

2.5

3.5

4.5

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

VLL = 10V,

8-ch, 220 pF,

1 kȍ

-1

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

0 2 4 6 8 10 12

Current (mA)

CW Frequency (MHz)

VGP = 10V,

8-ch, 220 pF,

1 kȍ

MD1730

DS20005586B-page 12  2016 Microchip Technology Inc.

FIGURE 2-13: Typical CW Output Phase Noise Curves.

-180

-170

-160

-150

-140

-130

-120

-110

-100

0.01 0.1 1 10 100

Phase Noise (dBc/Hz)

Offset Frequency (kHz)

MD1730 CW Output Phase Noise at 5 MHz,

Offset 10 Hz to 100 kHz

Mixer + Lowpass + HP4195A with ATR -20 dB,

RBW 10 Hz

 2016 Microchip Technology Inc. DS20005586B-page 13

MD1730

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

6x6 VQFN Symbol Pin Function

1 EN Device Enable Input. When EN = 0, the SPI and the internal regulator are disabled. The

device is enabled when EN = 1. Note that the EN pin has no control over the clock

buffers, as the clock buffers have their dedicated enable pins.

2 CLKP Positive Input of the Internal System Clock and is compatible with LVDS/SSTL. For

LVCMOS 2.5V input refer to Figure 4-8.

3 CLKN Negative Input of the Internal System Clock and is compatible with LVDS/SSTL. For

LVCMOS 2.5V input refer to Figure 4-8.

4 VLL +2.5V Positive Voltage Power Supply, it requires a 1.0 µF decoupling capacitor to GND

5, 33 GND Ground, 0V

6 VDD +5V Positive Voltage Power Supply, it requires a 1.0 µF decoupling capacitor to GND

7 SCK Serial Peripheral Interface (SPI) clock input

8 CSN Serial Peripheral Interface (SPI) chip-select. CSN is an active-low signal.

9 SDI Serial Peripheral Interface (SPI) data input

10 SDO Serial Peripheral Interface (SPI) data output

11, 35 CBE0-1 The clock buffer enable pin. When CBEn = 0, the corresponding clock buffer is

disabled. The clock buffer is enabled otherwise.

12, 34 CKB0-1 2.5V Single-ended Clock Buffer output pins

13 TXRW CW Transmission Control pin. When TXRW = 0, the SPI is enabled for read/write.

When TXRW = 1, the SPI is disabled and the CW transmission is started.

14, 23 VGN -10V Negative Voltage Power Supply, it requires a 2.2 µF capacitor to GND. The V

supply is also the substrate and should be the most negative supply to the chip.

15, 31 CNF Negative Floating Supply Bypass Capacitor pin. Connects 1 µF/10V capacitor between

this pin and the VCW- pin.

16, 30 VCW- -1V to -6V Negative Voltage Power Supply for the CW output, it requires a 1.0 µF

decoupling capacitor per pin to GND

17, 29 CPF Positive Floating Supply Bypass Capacitor pin. Connects 1 µF/10V capacitor between

this pin and the VCW+ pin.

18, 28 VCW+ +1V to +6V Positive Voltage Power Supply for the CW output. It requires a 1.0 µF

decoupling capacitor per pin to GND.

19, 20, 21,

22, 24, 25,

26, 27

CW0-7 Channel 0-7 CW Waveform Output

32 VGP +10V Positive Voltage Power Supply, it requires a 2.2 µF decoupling capacitor to GND

36 SPIB SPI Broadcasting Mode pin. When SPIB = 1, the broadcast mode is enabled.

37 EP Exposed Thermal Pad (EP); must be connected to GND

MD1730

DS20005586B-page 14  2016 Microchip Technology Inc.

NOTES:

 2016 Microchip Technology Inc. DS20005586B-page 15

MD1730

4.0 DEVICE DESCRIPTION

4.1 Operation Description

The MD1730 is an 8-channel ultra-low phase noise

monolithic CW transmitter. It consists of an SPI

interface to program internal phase delay registers and

frequency dividers to facilitate CW beamforming. It

supports differential LVDS/SSTL and single-ended

2.5V LVCMOS clock inputs. The MD1730's output path

is designed to provide ultra-low phase noise and can

swing up to ±6V. The following sections provide a

detailed overview of MD1730's feature set and

operation.

4.2 Using The Built-in Clock Buffers

The MD1730 has two built-in single ended clock output

buffers. The MD1730 can accept LVDS, SSTL25 and

LVCMOS 2.5V clock at its input and provide a

single-ended output buffered clock. The clock buffers

are independent of the chip's main EN pin and each

output clock buffer can be enabled or disabled

separately using the CBE0 or CBE1 pin. The maximum

clock frequency of the buffers is 250 MHz. The output

timing diagram for the clock buffers is shown in

Figure 4-5. As shown in the diagram CKB0 and CKB1,

clock outputs are only dependent on CBE0 and CBE1

respectively. This feature makes it convenient to drive

the TX pulser retiming clock input, such as the HV7321.

Using the built in clock buffers will save the cost of

additional buffers, reduce PCB area, simplify the

system clock distribution design and improve power

savings as well.

4.3 SPI Registers Description

Data Bits Description

W/R The W/R is the read write control bit. When W/R = 1, the SPI writes the data provided at the

addressed register. When W/R = 0, the SPI reads the data stored from the appropriate register.

The read operation is disabled when SPIB = 1.

CWFD<7:0> The CWFD<7:0> register stores the divisor value for setting the CW output frequency. The CW

output frequency is set by using the equation (f

CW = fCLK/(2*CWFD)) except CWFD = 0. For

CWFD = 0 the CW output frequency is fCW = fCLK/2*512. The CW output frequency ranges from

(fCLK /512) ≤fCW ≤(fCLK /2). The register's initial value is 0.

PHDCH<7:0> PHDCH<7:0> sets the phase delay for each individual channel. The equation for the output delay

time is PHD<7:0>/fCLK + 2/fCLK once TXRW goes high. The register initial value is 0. Refer to

Figure 4-4 for further details.

HIZCH HIZCH bit enables the channel output when the corresponding bit is . The channel is disabled 0

and its’ output becomes high Z when the corresponding bit is 1. The default register value is 0.

Note: CH denotes channel number 0 to 7.

MD1730

DS20005586B-page 16  2016 Microchip Technology Inc.

4.4 Serial Peripheral Interface (SPI)

The MD1730’s SPI is used to program the phase delay

and frequency divider registers. The SPI supports

writing at speed up to 200 MHz and the MSB is shifted

in first. SPI interface supports two operating modes:

daisy chain mode and broadcasting mode.

When SPIB = 0, the MD1730 is in daisy chain mode. In

this mode, it supports both read and write operations.

When SPIB = 1 the chip enters the “Broadcasting”

mode. In this mode, the SDI data shifts into the shift

user can write the same register of different daisy

chained chips with the same value in a single write

transaction. However, when SPIB = 1 the read

operation is disabled. To verify the written data for each

chip, the user can revert SPIB = 0 and perform a

normal read operation.

4.4.1 SPI WRITE OPERATION EXAMPLES

The following is a 1-byte writing example for the

D<7:0> = 01010101 when SPIB = TXRW = 0.

1. The Write operation starts with setting CSN to

low.

2. The SCK clock is used to shift in the following

SDI data:

W/R SPI Register ADD<3:0> Write or Read Data <7:0>

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 = Write

0 = Read

MSB first.

(See

Section 4.3

and

Section 4.4)

0 0 0 0 Channel 0 phase delay PHD0<7:0>

0 0 0 1 Channel 1 phase delay PHD1<7:0>

0 0 1 0 Channel 2 phase delay PHD2<7:0>

0 0 1 1 Channel 3 phase delay PHD3<7:0>

0 1 0 0 Channel 4 phase delay PHD4<7:0>

0 1 0 1 Channel 5 phase delay PHD5<7:0>

0 1 1 0 Channel 6 phase delay PHD6<7:0>

0 1 1 1 Channel 7 phase delay PHD7<7:0>

1 0 0 0 HIZ7 HIZ6 HIZ5 HIZ4 HIZ3 HIZ2 HIZ1 HIZ0

1 0 0 1 CW frequency divisor number CWFD<7:0>

Note: Power-On or EN = 0 sets all the registers to 0.

TABLE 4-1: PHD<7:0> PHASE DELAY TIME REGISTER DESCRIPTION

PHD<7:0> Delay Time to Start Transmitting

00000000 0/fCLK (Power-on default)

00000001 1/fCLK

00000010 2/fCLK

......... ........

11111110 254/fCLK

11111111 255/fCLK

TABLE 4-2: CWFD<7:0> CW FREQUENCY DIVIDER REGISTER DESCRIPTION

CWFD[7:0] Transmit CW Frequency fCW

00000000 fCLK/512 (Power-on default)

00000001 fCLK/2

00000010 fCLK/4

00000011 fCLK/6

......... ........

11111110 fCLK/508

11111111 fCLK/510

Note: The selected CW frequency is same for all the CW0~7 outputs: f

CW = fCLK/2*CWFD. The CW frequency

applies to all channels.

 2016 Microchip Technology Inc. DS20005586B-page 17

MD1730

D12 = 1, W/R bit set equal to high for write

operation.

ADD<11:8> = 0011b, address for channel-3’s

phase delay register.

D<7:0> = 01010101b, data to be written into

channel-3’s phase delay register.

The SDI data is shifted in at the rising edge of

SCK.

3. Once the complete data has been shifted in, the

CSN should be taken high to finish the writing

operation. The SDI data is latched into

channel-3’s phase delay register on the rising

edge of the CSN signal. CSN has to be kept high

for a minimum of 2-SCK cycles for the data to be

written into the appropriate register.

In the case of eight chips daisy chained together as

shown in Figure 4-3, there should be 13 x 8 = 104

cycles of SCK before the CSN is taken high.

The MD1730 can also be used in the Broadcasting

mode to write several daisy chained chips with the

same data. The Broadcasting mode can be used to

reduce the time required to write the SPI if several

MD1730 chips need the same data. The following is a

1-byte writing example for the register at the address

location ADD = 0011b with data D<7:0> =01010101b

while the MD1730 is set to broadcasting mode.

1. The write operation starts with setting CSN to

low with TXRW = 0 and SPIB = 1.

2. The SCK clock is used to shift in the following

SDI data to the first MD1730 chip:

D12 = 1, W/R bit set equal to high for write

operation.

ADD<11:8> = 0011b, address for the

channel-3’s phase delay register.

D<7:0> = 01010101, data to be written into the

channel-3’s phase delay register.

The SDI data is shifted in at the rising edge of

SCK.

In Broadcasting mode, the same set of data

shifted into the first chip’s SDI is sent to all the

MD1730 chips along the daisy chain. As shown

is Figure 4-3 when SPIB = 1 an internal switch

connects the SDI and SDO directly.

3. Once the complete data has been shifted in, the

CSN should be taken high to finish the writing

operation. The SDI data is latched into each

chip’s channel-3 phase delay register on the

rising edge of the CSN signal. CSN has to be

kept high for a minimum of 2-SCK cycles for the

data to be written into the appropriate register.

4.4.2 SPI READ OPERATION EXAMPLES

The following is a 2-byte reading example from the

1. The read operation starts with setting CSN to

low.

2. The SCK clock is used to shift in the following

SDI data:

D12 = 0, W/R bit set equal to high for read

operation.

ADD<11:8> = 0011b, address for channel-3’s

phase delay register.

D<7:0> = X, for a Read operation the data field

is don’t’ care.

The SDI data is shifted in at the rising edge of

SCK.

3. Once the complete data has been shifted into

the SPI the CSN is taken high. While CSN is

high the MD1730 fetches the data located at

ADD<11:9> = 0011b and places it in its internal

shift register.

4. Once the complete data has been shifted in, the

CSN should be taken high to finish the reading

operation. While CSN is high the MD1730

fetches the data located at ADD<11:9> = 0011b

and places it in its internal shift register. CSN

has to be kept high for a minimum of 2-SCK

cycles for the data to be fetched and placed into

the internal shift register.

5. The CSN is taken low and during the next 13

SCK clock cycles, the fetched data in the

internal shift register is clocked out on the rising

edge of SCK from the SDO of the MD1730.

MD1730

DS20005586B-page 18  2016 Microchip Technology Inc.

FIGURE 4-1: SPI Register Read/Write Timing with SPIB = 0, TXRW = 0.

FIGURE 4-2: SPI Register Broadcasting Write Timing with SPIB = 1, TXRW = 0.

Note: When in SPIB = 1 mode, the SPI register READ operations are not available.

D12 D0

D1D11

SCK

SDI

CSN

SDO

t3 t4

t5t7

SPIB

t10t11

TXRW

D12 D0

D1D11

SCK

SDI

CSN

SDO

t3 t4

t5t7

t12

SPIB

t10t11

TXRW

D12 D0

D1D11

 2016 Microchip Technology Inc. DS20005586B-page 19

MD1730

FIGURE 4-3: Multiple MD1730 Devices SPI Daisy Chain Connections.

4.5 CW0~7 Output Timing

The CW output waveform transmission timing is crucial

to an ultrasound imaging system. Any small timing

variations on the output can degrade the phase noise

performance. The MD1730’s internal circuitry is

designed to ensure ultra-low phase noise. Figure 4-4

shows an example of the output waveform timing

diagram. The chip is enabled by taking the EN pin high.

Then using the SPI, channel-0’s and channel-1’s phase

delay registers (PHD0<7:0> and PHD1<7:0>) are

programmed with delays of 2 and 3 respectively. The

rest of the channels are set to a high impedance state

by programming the HIZ<7:0> register with data

11111100b. Furthermore, the frequency divider

SPI operation the transmission starts by asserting

TXRW high. The phase delay counter starts counting

down after a two CLK cycle latency. This is illustrated in

Figure 4-4 for channel 0 and channel 1. In channel 0’s

case, the phase delay starts counting down from 2 to 0

after the latency and once the delay reaches 0 on the

next rising edge of CLK, the positive output appears on

the pin CW0. Based on the value of the CWFD<7:0>

the negative supply rail. Subsequently, after 4-CLK

cycles at the negative rail, the output switches back

again to the positive supply rail, completing one full CW

output wave cycle. This process continues until the

TXRW pin deasserts low, which shuts the transmission

off and forces the channel into a high impedance state.

This same procedure applies to channel 1, which is

also depicted in Figure 4-4.

FIGURE 4-4: CW0~7 Output Timing Diagram.

SDI SDO

SCK CSN

TXRW

13bit Shift Reg.

SPIB

Q12

0'

U2U8

TXRW

SCK

CSN

SDI

FPGA

SDO

SPIB

0'

SDI SDO

SCK CSN

13bit Shift Reg.

SPIB

Q12

0'

SDI SDO

SCK CSN

13bit Shift Reg.

SPIB

Q12

CW0

VCW+

tdrCW tdfCW

VCW-

t13

CLKP

Hi Z

CW end

tdrCW

CW = HiZCH

(fCLK)

TXRW

PHD0 7:0 !

(Phase Delay

Time for Ch0)

TXRW

(if PHD0=2) 0

EN EN=1

tEN_ON

t14

(3-cycle CLK)

PHD1 7:0 !

(Phase Delay

Time for Ch1)

(if PHD1=3) 12

CW1

VCW+

VCW-

Hi Z CW = HiZCH

tdrCW

tdfCW

tdrCW

-1

PHD 7:0 Start !

Count Down

(if CWFD[7:0]=4)

MD1730

DS20005586B-page 20  2016 Microchip Technology Inc.

FIGURE 4-5: Clock Buffers CKB0/1 Output Timing Diagram.

4.6 MD1730 Working with Two HV7321

The diagrams shown in Figure 4-6 and Figure 4-7

illustrate the MD1730 driving two HV7321s.

When the HV7321 is operated in the specific mode,

CW MODE = 1, along with the MD1730, the following

steps should be taken to ensure the combination

settings work correctly:

6. Apply all power supply rails to both chips and set

HV7321’s OEN = REN = PWS = 1 along with

MD1730’s EN = 1 to enable both chips. Set all

other control logic pins to zero.

7. Adjust the VCW+ and VCW- power supplies to

the required peak-to-peak voltage levels for CW

output transmission. Please note that a higher

peak-to-peak transmission voltage will result in

the MD1730 dissipating more power. The power

dissipation on the MD1730 is proportional to the

square of the peak-to-peak voltage.

8. Assert HV7321’s MODE pin high.

9. Program the MD1730 with the desired CW

frequency divider and delay settings for CW

transmission.

10. To place a channel in receive mode, set the

corresponding pins SEL, NEG, POS = 011b on

the HV7321. To place a channel to CW Transmit

mode, set the corresponding pins SEL, NEG,

POS to any other combination other than 011b

on HV7321. This will put that channel of the

HV7321 high voltage Tx output in High Z mode,

but turn the channel’s CWSW on.

In the case user wants a channel not in High Z or CW

Transmit mode, then similarly, to set the channel of

HV7321 to High Z and also set the MD1730’s

corresponding bit in the HIZ register to 1.

11. Once the system is ready to perform CW

Doppler measurement, assert TXRW high to

start the CW transmission on the selected

channels.

CKB0

tdrb tdfb

CLKP

(fCLK)

CKB1

CBE0

CBE1

trb trb

tcbe

 2016 Microchip Technology Inc. DS20005586B-page 21

MD1730

FIGURE 4-6: MD1730 Works with Two HV7321 4-Channel ±80V 2.6A 5-Level Ultrasound Pulsers.

C W -

-1 to -6V

G ND T her.

PAD

-10V

S UB

G N

C NF

E N

C W 0

VNF

C L KP

C L KN

S DO

S DI

C S N

S P I

S C K

C W 3

VP F

C W

F re. Dvdr

& P hase

Delay

C W 2

C W 1

T X RW

HIZ[ 7:0]

VLL

C L K

C B E 1

C K B0

C h0

S P IB

LV DS CL K

C B E 0 ,1

VLL

C B E 0

C K B1

U1 MD1730

V C W +

V C W -

+10V

G P

+2.5V

+1 to +6V

C W +

+5V

C P F

C h7

C W 4

C W 7

C W 6

C W 5

VNF

VP F

V C W +

V C W -

C h1~6

0 to+80V

V P F 1

VNN1

V P P 1

R G ND

T X 0

-0 to-80V

V P P 0

VNN0

0 to-80V

0 to+80V

1 of 4 C hannels

+5V

Decode

Level

S hift

C W IN0

NE G 0

S E L0

NE G 3

S E L3

C W IN3 U2 HV 7321

G ND

OT P N

+2.5V

P W S

P O S 3

VS UB

S UB

MODE

R E N

C L K

P O S 0

T X 1-3

R X1-3

R x0

R X0

V P F 0

V N F 0

V N F 1

R G ND

R T ZS W

C W S W

T R S W

R XDMP

T R S W

+10V

G P

-10V

OE N

G N

C W IN2

C W IN1

T x F P G A I /O s

Oth er

ICs

C T R N [3 :0 ]

OT P

DT [63:0]

0 to+80V

V P F 1

VNN1

V P P 1

R G ND

T X 0

-0 to-80V

V P P 0

VNN0

0 to-80V

0 to+80V

1 of 4 C hannels

+5V

Decode

Level

S hift

C W IN0

NE G 0

S E L0

NE G 3

S E L3

C W IN3 U3 HV 7321

G ND

OT P N

+2.5V

P W S

P O S 3

VS UB

S UB

MODE

R E N

C L K

P O S 0

T X 1-3

R X1-3

R x4

R X0

V P F 0

V N F 0

V N F 1

R G ND

R T ZS W

C W S W

T R S W

R XDMP

T R S W

+10V

G P

-10V

OE N

G N

C W IN2

C W IN1

+2.5V

Oth er

ICs

Oth er

ICs

MD1730 & 2x HV7321 Diagram

MD1730

DS20005586B-page 22  2016 Microchip Technology Inc.

FIGURE 4-7: MD1730 Working with Two HV7321 Pulsers Pinout and Package.

4.7 CW Transmission Clock

The input clock of the MD1730, used for CW

transmission, can be connected either differentially or

single-ended. Figure 4-8 shows the LVDS differential

implementation for the transmission clock. Here the

CLKP and the CLKN pins are directly driven by a LVDS

clock buffer. It is highly recommended that a

multiple-output LVDS clock buffer IC is used, such as

the SY89832U, and that a 100Ω termination resistor is

placed very close to the CLKP and CLKN pins. For

successful transmission of the LVDS signal over

differential traces, the following guidelines should be

followed while laying out the PCB board:

• To ensure minimal reflections and to maintain the

receiver’s common-mode noise rejection, keep

the differential traces as short as possible

between the clock buffer IC and the CLKP/CLKN

pins of the MD1730.

• To reduce skew, the electrical lengths between

differential LVDS traces should be identical. The

arrival of one differential signal before the other

will create a phase difference between the signal

pairs, which would create clock skew and impair

the system performance.

• Minimize the number of vias or other

discontinuities in the signal path. To avoid

discontinuities, arcs or 45-degree traces are

recommended instead of 90-degree turns.

• Any parasitic loading, such as capacitance, must

be present in equal amounts on each differential

line.

Figure 4-9 illustrates the two cases for the MD1730

used in a single-ended configuration. In these cases,

one of the clock input pins, CLKP or CLKN, is

connected to the VLL/2 voltage level and bypassed to

ground with a 0.1 uF bypass capacitor. Each bypass

capacitor must be placed very close to the MD1730.

The other clock input pin connects to the main clock

line. The PCB traces on the clock line must be

designed for a 50Ω impedance with respect to the PCB

ground place. Also, the clock pin must be terminated

with a small 50Ω SMT resistor.

Generally, the LVCMOS input configuration provides

better CW phase noise performance due to its higher

amplitude swing as compared to the LVDS

configuration. However, if the user needs a very high

frequency clock transmission, such as 160 MHz-

240 MHz range for a higher phase delay resolution,

then LVDS should be used because it provides a better

PCB clock trace distribution.

CPF1

VPP1

TX3

RXO3

RGND

RXO1

TX1

CPOS

CNEG

T X2

RXO2

RGND

RXO3

T X3

VPP1

CPF1

CWIN0

SEL1

NEG1

POS1

CWIN1

SEL2

NEG2

POS2

CWIN2

SEL3

REN

VLL

GND

CLK

PWS

OEN

POS0

NEG0

SEL0

MODE

VD D1

GDN

VGN

VPP0

CPF0

CNF0

VN N0

VN N2

VN N1

CNF1

NEG3

POS3

CWIN3

OTP1

VD D1

GND

VGP

VPP0

CFP0

VN F0

VN N0

VN N2

VN N1

CNF 1

CPF1

VPP1

T X3

RXO3

RGND

RXO1

TX1

CPOS

CNEG

TX2

RXO2

RGND

RXO3

TX3

VPP1

CPF1

CWIN0

SEL1

NEG1

POS1

CWIN1

SEL2

NEG2

POS2

CWIN2

SEL3

REN

VLL

GND

CLK

PWS

OEN

POS0

NEG0

SEL0

MODE

VD D1

GDN

VGN

VPP0

CPF0

CNF0

VN N0

VN N2

VN N1

CNF1

NEG3

POS 3

CWIN3

OTP1

VD D1

GND

VGP

VPP 0

CFP0

VN F0

VN N0

VN N2

VN N1

CNF 1

,sϳϯϮϭ

9x9mm

QFN-64

,sϳϯϮϭ

9x9mm

QFN-64

To Probe & Rx LNA

CW 0

CK B0

CW 2

CW 3

CW 4

CW 5

CW 6

CK B1

VD D

VC W+

CP F

VCW-

CN F

VC W+

CP F

VC W-

CN F

GN D

CLKW

CLKE

CSE

SC K

SD I

SD O

CB E1

VG PVG N

DϭϳϯϬ

6x6mm

QFN-36

TXRW

CW 1

CW 7

VG N

VLL

CB E0

SP IB

GN D

 2016 Microchip Technology Inc. DS20005586B-page 23

MD1730

FIGURE 4-8: LVDS Differential Transmission Clock.

FIGURE 4-9: LVCMOS Single-Ended Transmission Clock.

100

VCC

0'

10' 0'

TXRW TXRW

TXRW

EN ENEN

CLKP CLKN CLKP CLKN CLKP CLKN

Differ tial LVDSHQ  

Clock Line-Pair

CLK Buffer

2.5V

VLL

2.5V

VLL

2.5V

VLL

2.5V

Clock

Source

(from FPGA)

... ...

100 100

SY89832U

GND

GND GND

GND

2.5V

CLK0

U10'

TXRWEN

0'

PL133-47

CLK Buffer

TXRW TXRW

TXRW

EN EN

0'

CLKP CLKNCLKP CLKN CLKP CLKN

1.25V

0.1 F 0.1 F 0.1 F

Single-Ended

LVCMOS Clock Line

VLL

2.5V

VLL VLL

2.5V 2.5V

80-150MHz

Clock OSC.

(from FPGA)

REF CLK1

CLK3

GND 33ohm

2.5V

CLK0

U10'

TXRWEN

U4

0'

PL133-47

CLK Buffer

TXRW TXRW

TXRW

EN EN

0'

CLKP CLKNCLKP CLKN CLKP CLKN

1.25V

0.1 F 0.1 F 0.1 F

Single-Ended

LVCMOS Clock Line

VLL

2.5V

VLL VLL

2.5V 2.5V

80-150MHz

Clock OSC.

(from FPGA)

REF CLK1

CLK3

GND 33ohm

GND GND GND

MD1730

DS20005586B-page 24  2016 Microchip Technology Inc.

NOTES:

 2016 Microchip Technology Inc. DS20005586B-page 25

MD1730

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC® designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

36-Lead VQFN (6x6x0.9 mm) Example

XXXXXXXX

YYWWNNN

PIN 1 PIN 1

MD1730

1624256

MD1730

DS20005586B-page 26  2016 Microchip Technology Inc.

0.10 C

0.10 C A B

0.05 C

(DATUM B)

(DATUM A)

NOTE 1

TOP VIEW

SIDE VIEW

BOTTOM VIEW

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

NOTE 1

0.10 C A B

0.10 C

0.08 C

Microchip Technology Drawing C04-272B-M2 Sheet 1 of 2

36X

(A3)

L36X b

36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

SEATING

PLANE

 2016 Microchip Technology Inc. DS20005586B-page 27

MD1730

Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

Number of Terminals

Overall Height

Terminal Width

Overall Width

Overall Length

Terminal Length

Exposed Pad Width

Exposed Pad Length

Terminal Thickness

Pitch

Standoff

Units

Dimension Limits

0.50 BSC

0.20 REF

3.60

0.50

0.18

0.80

0.00

0.25

6.00 BSC

0.60

3.70

0.90

0.02

6.00 BSC

MILLIMETERS

MIN NOM

3.80

0.75

0.30

1.00

0.05

MAX

K 0.550.45 -

REF: Reference Dimension, usually without tolerance, for information purposes only.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Pin 1 visual index feature may vary, but must be located within the hatched area.

Package is saw singulated

Dimensioning and tolerancing per ASME Y14.5M

Terminal-to-Exposed-Pad

36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x1.0mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

MD1730

DS20005586B-page 28  2016 Microchip Technology Inc.

RECOMMENDED LAND PATTERN

Dimension Limits

Units

Optional Center Pad Width

Contact Pad Spacing

Optional Center Pad Length

Contact Pitch

3.80

MILLIMETERS

0.50 BSC

MIN

MAX

5.60

Contact Pad Length (X36)

Contact Pad Width (X36)

1.10

0.30

Microchip Technology Drawing C04-2272B-M2

NOM

SILK SCREEN

C1Contact Pad Spacing 5.60

Thermal Via Diameter V

Thermal Via Pitch EV

0.30

1.00

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Notes:

Dimensioning and tolerancing per ASME Y14.5M

For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Note:

ØV

36-Terminal Very Thin Plastic Quad Flatpack No-Lead (M2) - 6x6x0.9 mm Body [VQFN]

SMSC Legacy "Sawn Quad Flatpack No-Lead [SQFN]"

Contact Pad to Center Pad (X36) G1 0.35

Space Between Contact Pads (X32) G2 0.20

 2016 Microchip Technology Inc. DS20005586B-page 29

MD1730

APPENDIX A: REVISION HISTORY

Revision B (November 2016)

The following is the list of modifications:

• Updated Section “Product Identification

System”.

• Minor typographical corrections.

Revision A (September 2016)

• Original Release of this Document.

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	MD1730

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