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2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 1
MCP6546/6R/6U/7/8/9
Features
• Low Quiescent Current: 600 nA/Comparator (typical)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• Open-Drain Output: VOUT 10V
•Propagation Delay: 4 µs (typical, 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Single Available in SOT-23-5, SC-70-5* Packages
• Available in Single, Dual and Quad
• Chip Select (CS) with MCP6548
• Low Switching Current
• Internal Hysteresis: 3.3 mV (typical)
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typical Applications
• Laptop Computers
• Mobile Phones
• Metering Systems
• Handheld Electronics
• RC Timers
• Alarm and Monitoring Circuits
• Windowed Comparators
• Multivibrators
Related Devices
• CMOS/TTL-Compatible Output: MCP6541/2/3/4
Description
The Microchip MCP6546/6R/6U/7/8/9 family of com-
parators, is offered in single (MCP6546, MCP6546R,
MCP6546U), single with Chip Select (CS) (MCP6548),
dual (MCP6547) and quad (MCP6549) configurations.
The outputs are open-drain and are capable of driving
heavy DC or capacitive loads.
These comparators are optimized for low-power,
single-supply application with greater than rail-to-rail
input operation. The output limits supply current surges
and dynamic power consumption while switching. The
open-drain output of the MCP6546/6R/6U/7/8/9 family
can be used as a level-shifter for up to 10V using a pull-
up resistor. It can also be used as a wired-OR logic.
The internal input hysteresis eliminates output switch-
ing due to internal noise voltage, reducing current draw.
These comparators operate with a single-supply
voltage as low as 1.6V and draw a quiescent current of
less than 1 µA/comparator.
The related Microchip MCP6541/2/3/4 family of com-
parators has a push-pull output that supports rail-to-rail
output swing and interfaces with CMOS/TTL logic.
Note that SC-70-5 E-Temp parts are not available at
this release of the data sheet.
The MCP6546U SOT-23-5 is E-Temp only.
Package Types
VIN+
VIN–
MCP6546
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
PDIP, SOIC, MSOP
4
1
2
3
-
+
5
SOT-23-5
VDD
OUT
VIN+
VSS
VIN–
MCP6546R MCP6547
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
-
OUTA
+-
+
VDD
OUTB
VINB–
VINB+
VIN+
VIN–
MCP6548
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
CSNC
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6549
VINA+
VINA–
VSS
1
2
3
4
14
13
12
11
-
OUTA
+-
+
VDD
OUTD
VIND–
VIND+
10
9
8
5
6
7OUTB
VINB–
VINB+ VINC+
VINC–
OUTC
+- -
+
PDIP, SOIC, TSSOP
4
1
2
3
-
+
5
SC-70-5, SOT23-5
VSS
OUT
VIN+
VDD
VIN–
MCP6546
4
1
2
3
5
SC-70-5, SOT-23-5
VSS
VIN+
VIN–
VDD
OUT
MCP6546U
-
+
Open-Drain Output Sub-Microamp Comparators
MCP6546/6R/6U/7/8/9
DS20001714H-page 2 2002-2022
Microchip Technology Inc. and its subsidiaries
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Open-Drain Output.............................................. V
SS + 10.5V
Analog Input (VIN+, VIN-)††............. VSS - 1.0V to VDD + 1.0V
All Other Inputs and Outputs .......... V
SS - 0.3V to VDD + 0.3V
Difference Input Voltage ....................................... |V
DD - VSS|
Output Short-Circuit Current ................................Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature (TS).............................-65°C to +150°C
Maximum Junction Temperature (T
J)..........................+150°C
ESD Protection on all Pins:
(HBM;MM) .....................................2 kV;200V (MCP6546U)
(HBM;MM) ................................ 4 kV; 200V (all other parts)
† Notice: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those indicated
in the operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V
DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,
VIN– = VSS, RPU = 2.74 k to VPU = VDD (Refer to ).Figure 1-3
Parameters Sym Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.6 — 5.5 V VPU V DD
Quiescent Current per
Comparator
IQ0.3 0.6 1 µA IOUT = 0
Input
Input Voltage Range VCMR VSS0.3 — VDD+0.3 V
Common-mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 5.3V
Common-mode Rejection Ratio CMRR 50 65 — dB VDD = 5V, VCM = 2.5V to 5.3V
Common-mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 2.5V
Power Supply Rejection Ratio PSRR 63 80 — dB VCM = V
SS
Input Offset Voltage VOS -7.0 ±1.5 +7.0 mV VCM = V
SS ( )Note 1
Drift with Temperature VOS/ TA— ±3 — µV/°C TA = -40°C to +125°C, VCM = VSS
Input Hysteresis Voltage VHYST 1.5 3.3 6.5 mV VCM = V
SS ( )Note 1
Linear Temp. Co. TC1— 6.7 — µV/°C TA = -40°C to +125°C, VCM = VSS
( )Note 2
Quadratic Temp. Co. TC2— -0.035 — µV/°C2TA = -40°C to +125°C, VCM = VSS
( )Note 2
Input Bias Current IB— 1 — pA VCM = VSS
At Temperature (I-Temp parts) IB— 25 100 pA TA
= +85°C, VCM = VSS ( )Note 3
At Temperature (E-Temp parts) IB— 1200 5000 pA TA
= +125°C, VCM = VSS
( )Note 3
Input Offset Current IOS — ±1 — pA VCM = VSS
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at differential temperatures is estimated using:
VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
3: Input bias current at temperature is not tested for the SC-70-5 package.
4: Do not short the output above V
SS
+ 10V. Limit the output current to Absolute Maximum Rating of 30 mA.
The minimum V
PU test limit was VDD before Dec. 2004 (week code 52).
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 3
MCP6546/6R/6U/7/8/9
Common-mode Input Impedance ZCM — 1013||4 — ||pF
Differential Input Impedance ZDIFF — 1013||2 — ||pF
Open-Drain Output
Output Pull-Up Voltage V
PU 1.6 — 10 V ( )Note 4
High-Level Output Current IOH -100 — — nA VDD = 1.6V to 5.5V, VPU = 10V
( )Note 4
Low-Level Output Voltage VOL VSS — VSS+0.2 V IOUT = 2 mA, VPU = VDD = 5V
Short-Circuit Current ISC — ±1.5 — mA VPU = VDD = 1.6V ( )Note 4
I
SC – 30 — mA VPU = VDD = 5.5V ( )Note 4
Output Pin Capacitance C
OUT — 8 — pF
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V
DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,
Step = 200 mV, Overdrive = 100 mV, R
PU = 2.74 k to VPU = VDD, and CL = 36 pF
(Refer to and ).Figure 1-2 Figure 1-3
Parameters Sym Min Typ Max Units Conditions
Fall Time tF— 0.7 — µs ( )Note 1
Propagation Delay (High-to-Low) tPHL — 4.0 8.0 µs
Propagation Delay (Low-to-High) tPLH — 3.0 8.0 µs ( )Note 1
Propagation Delay Skew tPDS — -1.0 — µs and( Note 1 )Note 2
Maximum Toggle Frequency fMAX — 225 — kHz VDD = 1.6V
fMAX — 165 — kHz VDD = 5.5V
Input Noise Voltage Eni — 200 — µVP-P 10 Hz to 100 kHz
Note 1: tR and tPLH depend on the load (R
L and CL); these specifications are valid for the indicated load only.
2: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, V
DD = +1.6V to +5.5V, VSS = GND, TA = 25°C, VIN+ = VDD/2,
VIN– = VSS, RPU = 2.74 k to VPU = VDD (Refer to ).Figure 1-3
Parameters Sym Min Typ Max Units Conditions
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at differential temperatures is estimated using:
VHYST (TA) = VHYST + (TA -25°C) TC1 + (TA - 25°C)2TC2.
3: Input bias current at temperature is not tested for the SC-70-5 package.
4: Do not short the output above V
SS + 10V. Limit the output current to Absolute Maximum Rating of 30 mA.
The minimum VPU test limit was VDD before Dec. 2004 (week code 52).
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 5
MCP6546/6R/6U/7/8/9
1.1 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
FIGURE 1-3: AC and DC Test Circuit for
the Open-Drain Output Comparators.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, V
DD = +1.6V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C
Operating Temperature Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC-70 JA — 331 — °C/W
Thermal Resistance, 5L-SOT-23 JA — 220.7 — °C/W
Thermal Resistance, 8L-MSOP JA — 211 — °C/W
Thermal Resistance, 8L-PDIP JA — 89.3 — °C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W
Thermal Resistance, 14L-PDIP JA — 70 — °C/W
Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note: The MCP6546/6R/6U/7/8/9 I-Temp family operates over this extended temperature range, but with reduced
performance. In any case, the Junction Temperature (T
J) must not exceed the absolute maximum
specification of +150°C.
VDD
VSS = 0V
200 k
200 k
100 k
VOUT
VIN = VSS
36 pF
MCP654X RPU =
VPU = VDD
(2 mA)/ VDD
MCP6546/6R/6U/7/8/9
DS20001714H-page 6 2002-2022
Microchip Technology Inc. and its subsidiaries
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RPU = 2.74 k to V PU = VDD, and CL = 36 pF.
FIGURE 2-1: Input Offset Voltage at
VCM = VSS.
FIGURE 2-2: Input Offset Voltage Drift at
VCM = VSS.
FIGURE 2-3: The MCP6546/6R/6U/7/8/9
Comparators Show No Phase Reversal.
FIGURE 2-4: Input Hysteresis Voltage at
VCM = VSS.
FIGURE 2-5: Input Hysteresis Voltage
Linear Temp. Co. (TC1) at VCM = VSS.
FIGURE 2-6: Input Hysteresis Voltage
Quadratic Temp. Co. (TC 2
) at VCM = VSS.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
Input Offset Voltage (mV)
Percentage of Occurrences
1200 Samples
VCM = VSS
0%
2%
4%
6%
8%
10%
12%
14%
16%
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1200 Samples
VCM = V
SS
TA
= -40°C to +125°C
-1
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7 8 9 10
Time (1 ms/div)
Inverting Input, Output
Voltage (V)
VOUT
VIN–
VDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Hysteresis Voltage (mV)
Percentage of Occurrences
1200 Samples
VCM = V
SS
0%
5%
10%
15%
20%
25%
4.6
5.0
5.4
5.8
6.2
6.6
7.0
7.4
7.8
8.2
8.6
9.0
9.4
Input Hysteresis Voltage –
Linear Temp. Co.; TC1 (µV/°C)
Percentage of Occurrences
596 Samples
VCM = V
SS
TA
= -40°C to +125°C
VDD
= 1.6VV DD
= 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-0.060
-0.056
-0.052
-0.048
-0.044
-0.040
-0.036
-0.032
-0.028
-0.024
-0.020
-0.016
Input Hysteresis Voltage –
Quadratic Temp. Co.; TC2 (µV/°C
2)
Percentage of Occurrences
596 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 5.5V
V
DD = 1.6V
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 7
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature at VCM = VSS.
FIGURE 2-8: Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 1.6V.
FIGURE 2-9: Input Offset Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
FIGURE 2-10: Input Hysteresis Voltage vs.
Ambient Temperature at VCM = VSS.
FIGURE 2-11: Input Hysteresis Voltage vs.
Common-mode Input Voltage at VDD = 1.6V.
FIGURE 2-12: Input Hysteresis Voltage vs.
Common-mode Input Voltage at VDD = 5.5V.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Offset Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 1.6V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 5.5V
TA = +85°C
TA = +125°C
T
A
= -40°C
TA
= +25°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Hysteresis Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
TA = +25°C
TA = -40°C
TA = +125°C
TA = +85°C
VDD = 1.6V
TA
= +125°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
VDD = 5.5V TA = +125°C
T
A = +85°C
T
A = +25°C
T
A = -40°C
MCP6546/6R/6U/7/8/9
DS20001714H-page 8 2002-2022
Microchip Technology Inc. and its subsidiaries
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-13: CMRR,PSRR vs. Ambient
Temperature.
FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15: Quiescent Current vs.
Common-mode Input Voltage at VDD = 1.6V.
FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common-mode Input Voltage.
FIGURE 2-17: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-18: Quiescent Current vs.
Common-mode Input Voltage at VDD = 5.5V.
55
60
65
70
75
80
85
90
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
Input Referred
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
CMRR, V IN
+ = -0.3 to 5.3V, VDD = 5.0V
0.1
1
10
100
1000
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
IB
| IOS |
VDD = 5.5V
VCM = VDD
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
Quiescent Current
per Comparator (µA)
VDD = 1.6V
Sweep VIN +, VIN– = VDD /2
Sweep V IN–, VIN
+ = VDD/2
IQ
does not include pull-up resistor current
0.1
1
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(A)
VDD = 5.5V
100f
100p
1p
10p
1n
10n
IB, TA = +125°C
IB, T A
= +85°C
IOS, TA = +125°C
IOS, TA = +85°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
per Comparator (µA)
TA = +125°C
TA = +85°C
TA = +25°C
T
A = -40°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Quiescent Current
per Comparator (µA)
VDD
= 5.5V
Sweep VIN+, VIN– = VDD
/2
Sweep VIN–, VIN+ = VDD/2
IQ
does not include pull-up resistor current
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 9
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-19: Supply Current vs. Pull Up -
Voltage.
FIGURE 2-20: Supply Current vs. Toggle
Frequency.
FIGURE 2-21: Output Voltage Headroom
vs. Output Current at VDD = 1.6V.
FIGURE 2-22: Supply Current vs. Pull Up -
to Supply Voltage Difference.
FIGURE 2-23: Output Short Circuit Current
Magnitude vs. Power Supply Voltage.
FIGURE 2-24: Output Voltage Headroom
vs. Output Current at VDD = 5.5V.
0.1
1
10
0 1 2 3 4 5 6 7 8 9 10 11
Pull-Up Voltage, V PU (V)
Supply Current
per Comparator (µA)
VDD
= 2.1V
VDD
= 2.6V
VDD
= 3.6V
VDD
= 4.6V
VDD
= 5.6V
IDD spike near VPU = 1.3V
VDD
= 1.6V
0.1
1
10
0.1 1 10 100
Toggle Frequency (kHz)
Supply Current
per Comparator (µA)
V
DD = 5.5V
V
DD = 1.6V
100 mV Overdrive
VCM = VDD/2
IDD does not include
pull-up resistor current
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Output Current (mA)
Output Voltage Headroom (V)
VDD = 1.6V
VOL–VSS:
TA
= +125°C
TA
= +85°C
TA
= +25°C
TA
= -40°C
0.1
1
10
-4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9
Pull-up to Supply Voltage Difference,
VPU – VDD (V)
Supply Current
per Comparator (µA)
VDD = 5.6V
VDD = 4.6V
VDD = 3.6V
VDD = 2.6V
VPU = 1.6V to 10.5V
VDD = 1.6V
VDD = 2.1V
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA = -40°C
TA
= +25°C
TA
= +85°C
TA
= +125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
Output Current (mA)
Output Voltage Headroom (V)
VDD = 5.5V
T
A = +125°C
T
A = +85°C
T
A = +25°C
T
A = -40°C
VOL
– VSS
:
MCP6546/6R/6U/7/8/9
DS20001714H-page 10 2002-2022
Microchip Technology Inc. and its subsidiaries
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-25: High-to-Low Propagation
Delay.
FIGURE 2-26: Propagation Delay Skew.
FIGURE 2-27: Propagation Delay vs.
Power Supply Voltage.
FIGURE 2-28: Low-to-High Propagation
Delay.
FIGURE 2-29: Propagation Delay vs.
Ambient Temperature.
FIGURE 2-30: Propagation Delay vs. Input
Overdrive.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
0 1 2 3 4 5 6 7 8
High-to-Low Propagation Delay (µs)
Percentage of Occurrences
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5VVDD = 1.6V
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
Propagation Delay Skew (µs)
Percentage of Occurrences
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Propagation Delay (µs)
VCM
= V DD
/2
tPHL
10 mV Overdrive
100 mV Overdrive tPLH
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
50%
55%
60%
65%
0 1 2 3 4 5 6 7 8
Low-to-High Propagation Delay (µs)
Percentage of Occurrences
408 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5V
VDD = 1.6V
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD/2
tPHL
tPLH
VDD = 5.5V
VDD = 1.6V
1
10
100
1 10 100 1000
Input Overdrive (mV)
Propagation Delay (µs)
VCM = VDD
/2
tPLH
V
DD = 5.5V
tPHL
VDD = 1.6V
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 11
MCP6546/6R/6U/7/8/9
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-31: Propagation Delay vs.
Common-mode Input Voltage at VDD = 1.6V.
FIGURE 2-32: Propagation Delay vs.
Pull up Resistor.-
FIGURE 2-33: Propagation Delay vs.
Pull up Voltage.-
FIGURE 2-34: Propagation Delay vs.
Common-mode Input Voltage at VDD = 5.5V.
FIGURE 2-35: Propagation Delay vs. Load
Capacitance.
FIGURE 2-36: Output Leakage Current
(CS = VDD) vs. Output Voltage (MCP6548 only).
0
1
2
3
4
5
6
7
8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 1.6V
100 mV Overdrive
tPLH
tPHL
0
1
2
3
4
5
6
7
8
0 10 20 30 40 50 60 70 80 90 100
Pull-up Resistor, RPU (k )
:
:
:
::
Propagation Delay (µs)
VCM
= VDD/2
VIN
+ = VCM VDD
= 5.5V
VIN
– = 100 mV Overdrive
tPHL
tPLH
VDD
= 1.6V
0
1
2
3
4
5
6
7
8
0 1 2 3 4 5 6 7 8 9 10 11
Pull-up Voltage (V)
Propagation Delay (µs)
VCM = VDD
/2
VIN
+ = VCM
tPHL
VIN
– = 100 mV Overdrive
VDD = 5.5V
VDD = 1.6V tPLH
0
1
2
3
4
5
6
7
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 5.5V
100 mV Overdrive
tPHL
tPLH
0
20
40
60
80
100
120
140
160
180
200
0 10 20 30 40 50 60 70 80 90
Load Capacitance (nF)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD
/2 tPLH
tPHL
VDD = 1.6V
VDD = 5.5V
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
01234567891011
Output Voltage (V)
Output Leakage Current (A)
TA = +85°C
CS = VDD
VIN+ = V
DD/2
VIN– = VSS
TA = +125°C
TA = +25°C
10n
1n
100p
10p
1p
100f
MCP6546/6R/6U/7/8/9
DS20001714H-page 12 2002-2022
Microchip Technology Inc. and its subsidiaries
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA= +25°C, VIN+=VDD/2, VIN– = GND,
RPU = 2.74 k to VPU = VDD, and CL= 36 pF.
FIGURE 2-37: Supply Current (Shoot-
through Current) vs. Chip Select (CS) Voltage at
VDD = 1.6V (MCP6548 only).
FIGURE 2-38: Supply Current (Charging
Current) vs. Chip Select (CS) Pulse at
VDD = 1.6V (MCP6548 only).
FIGURE 2-39: Chip Select (CS) Step
Response (MCP6548 only).
FIGURE 2-40: Supply Current (Shoot-
through Current) vs. Chip Select (CS) Voltage at
VDD = 5.5V (MCP6548 only).
FIGURE 2-41: Supply Current (Charging
Current) vs. Chip Select (CS) Pulse at
VDD = 5.5V (MCP6548 only).
FIGURE 2-42: Input Bias Current vs. Input
Voltage.
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
f
Comparator
Turns On
VDD = 1.6V
CS Hysteresis
CS
High-to-Low
CS
Low-to-High
1m
1µ
10µ
100n
1n
10n
100p
10p
100µ
0
5
10
15
20
30
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Time (1 ms/div)
Supply Current (µA)
0.0
1.6
Output Voltage,
Chip Select Voltage (V),
Start-up
IDD
Charging output
capacitance
VDD = 1.6V
VOUT
CS
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 1 2 3 4 5 6 7 8 9 10
Time (ms)
Chip Select, Output Voltage
(V)
VOUT
VDD = 5.5V
CS
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
f
Comparator
Turns On
VDD
= 5.5V
1m
1µ
10µ
100n
1n
10n
100p
10p
CS
Low-to-High
CS
Hysteresis
CS
High-to-Low
100µ
0
20
40
60
80
100
120
140
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)
Supply Current
per Comparator (µA)
0
3
6
Output Voltage,
Chip Select Voltage (V)
Start-up IDD
Charging output
capacitance
VDD
= 5.5V
VOUT
CS
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 13
MCP6546/6R/6U/7/8/9
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
3.1 Analog Inputs
The comparator noninverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2 CS Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.3 Digital Outputs
The comparator outputs are CMOS, open-drain digital
outputs. They are designed to make level shifting and
wired-OR easy to implement.
3.4 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (V
SS). For
normal operation, the other pins are at voltages
between VSS and VDD, except the output pins which
can be as high as 10V above V
SS.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These pins can
share a bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
TABLE 3-1: PIN FUNCTION TABLE
MCP6546
MCP6546
MCP6546R
MCP6546U
MCP6547
MCP6548
MCP6549
Symbol Description
PDIP,
SOIC,
MSOP
SC-70,
SOT-23
SOT-
23-5
SC-70,
SOT-
23-5
PDIP,
SOIC,
MSOP
PDIP,
SOIC,
MSOP
PDIP,
SOIC,
TSSOP
6 1 1 4 1 6 1 OUT, OUTA Digital Output (Comparator A)
2443222VIN–, VINA– Inverting Input (Comparator A)
3331333VIN+, VINA+ Noninverting Input (Comparator A)
7525874 VDD Positive Power Supply
— — — — 5 — 5 VINB+ Noninverting Input (Comparator B)
— — — — 6 — 6 VINB– Inverting Input (Comparator B)
— — — — 7 — 7 OUTB Digital Output (Comparator B)
— — — — — — 8 OUTC Digital Output (Comparator C)
—————— 9 VINC– Inverting Input (Comparator C)
——————10 VINC+ Noninverting Input (Comparator C)
42524411 V
SS Negative Power Supply
——————12 VIND+ Noninverting Input (Comparator D)
——————13 VIND– Inverting Input (Comparator D)
— — — — — — 14 OUTD Digital Output (Comparator D)
— — — — — 8 — CS Chip Select
1, 5, 8 — — — — 1, 5 — NC No Internal Connection
MCP6546/6R/6U/7/8/9
DS20001714H-page 14 2002-2022
Microchip Technology Inc. and its subsidiaries
4.0 APPLICATION INFORMATION
The MCP6546/6R/6U/7/8/9 family of push-pull output
comparators are fabricated on Microchip’s state-of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low-power consumption.
4.1 Comparator Inputs
4.1.1 PHASE REVERSAL
The MCP6546/6R/6U/7/8/9 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. shows an input voltageFigure 2-3
exceeding both supplies with no resulting phase
inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in . This structure was chosen toFigure 4-1
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pin. Diodes D
1 and D2 prevent the input
pin (VIN+ and VIN–) from going too far above VDD.
When implemented as shown, resistors R1
and R2 also
limit the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the Common-mode voltage (V
CM) is below
ground (VSS); see . Applications that areFigure 2-42
high-impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input voltages and the other at high input voltages.
With this topology, the input voltage is 0.3V above V
DD
and 0.3V below VSS. The input offset voltage is
measured at both VSS - 0.3V and VDD+ 0.3V to ensure
proper operation.
The MCP6546/6R/6U/7/8/9 family has internally set
hysteresis that is small enough to maintain input offset
accuracy (<7 mV), and large enough to eliminate
output chattering caused by the comparator’s own
input noise voltage (200 µVP-P). illustratesFigure 4-3
this capability.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN
+
VSS
Input
Stage
Bond
Pad VIN–
V1
MCP6G0X
R1
VDD
D1
R1
VSS – (minimum expected V1)
2 mA
VOUT
V2
R2R3
D2
+
–
R2
VSS – (minimum expected V2)
2 mA
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 15
MCP6546/6R/6U/7/8/9
FIGURE 4-3: The MCP6546/6R/6U/7/8/9
Comparators’ Internal Hysteresis Eliminates
Output Chatter Caused by Input Noise Voltage.
4.2 Open-Drain Output
The open-drain output is designed to make level-
shifting and wired-OR logic easy to implement. The
output can go as high as 10V for 9V battery-powered
applications. The output stage minimizes switching cur-
rent (shoot-through current from supply-to-supply)
when the output changes state. See ,Figure 2-15
Figure 2-18 Figure 2-37 Figure 2-41 and through for
more information.
4.3 MCP6548 Chip Select (CS)
The MCP6548 is a single comparator with a Chip
Select (CS) pin. When CS is pulled high, the total
current consumption drops to 20 pA (typical). 1 pA
(typical) flows through the CS pin, 1 pA (typical) flows
through the output pin and 18 pA (typical) flows through
the VDD pin, as shown in . When thisFigure 1-1
happens, the comparator output is put into a high-
impedance state. By pulling CS low, the comparator is
enabled. If the CS pin is left floating, the comparator will
not operate properly. shows the outputFigure 1-1
voltage and supply current response to a CS pulse.
The internal CS circuitry is designed to minimize
glitches when cycling the CS pin. This helps conserve
power, which is especially important in battery-powered
applications.
4.4 Externally Set Hysteresis
Greater flexibility in selecting hysteresis, or input trip
points, is achieved by using external resistors.
Input offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other, thus reducing dynamic supply current. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
4.4.1 INVERTING CIRCUIT
Figure 4-4 shows an inverting circuit for a single-supply
application using three resistors, besides the pull-up
resistor. The resulting hysteresis diagram is shown in
Figure 4-5.
FIGURE 4-4: Inverting Circuit with
Hysteresis.
FIGURE 4-5: Hysteresis Diagram for the
Inverting Circuit.
0
1
2
3
4
5
Time (100 ms/div)
Output Voltage (V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
Input Voltage (10 mV/div)
VOUT
VIN–
VDD = 5.0V
Hysteresis
VIN
VOUT
MCP654X
VDD
R2
RF
R3
VPU
RPU
VDD IOL
IRF
IPU
VOUT
High-to-LowLow-to-High
VOH
VOL
VSS
VSS VDD
VTLH VTHL
VIN
VPU
VTLH = trip voltage from low to high
VTHL = trip voltage from high to low
MCP6546/6R/6U/7/8/9
DS20001714H-page 16 2002-2022
Microchip Technology Inc. and its subsidiaries
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in , RFigure 4-4 2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD as shown in .Figure 4-6
FIGURE 4-6: Thevenin Equivalent Circuit.
EQUATION 4-1:
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
Figure 2-21 Figure 2-24 and can be used to determine
typical values for VOL. This voltage is dependent on the
output current IOL as shown in . This currentFigure 4-4
can be determined using the equation below:
EQUATION 4-3:
VOH can be calculated using the equation below:
EQUATION 4-4:
As explained in , itSection 4.1 “Comparator Inputs”
is important to keep the noninverting input below
VDD+0.3V when VPU > VDD.
4.5 Supply Bypass
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge-rate performance.
4.6 Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-27).
The supply current increases with increasing toggle
frequency ( ), especially with higherFigure 2-30
capacitive loads.
4.7 Battery Life
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) too frequently, in order to
conserve power. Capacitive loads will draw additional
power at start-up.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP6546/6R/6U/7/8/9 family’s bias current at
25°C (1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
V23
VOUT
MCP654X
VPU
R23 RF
+
-RPU
R23
R2R3
R2R3
+
-------------------=
V23
R3
R2R3
+
------------------- VD D
=
VT HL VP U
R23
R23 RFRP U
+ +
----------------------------------------
 
 
V
23
RFRP U
+
R23 RFRP U
+ +
---------------------------------------
 
 
+=
VT LH VO L
R23
R23 RF
+
-----------------------
 
 
V
23
RF
R23 RF
+
----------------------
 
 
+=
VTLH
= trip voltage from low to high
VTHL
= trip voltage from high to low
IO L I
P U IR F
+=
IO L
V
P U VO L
–
RP U
--------------------------
 
V23 VO L
–
R23 RF
+
------------------------
 
 
+=
VO H VP U V23
– R23 RF
+
R23 RFRP U
+ +
---------------------------------------
 
 
=
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 17
MCP6546/6R/6U/7/8/9
FIGURE 4-7: Example Guard Ring Layout
for Inverting Circuit.
For the Inverting Configuration ( andFigure 4-4
Figure 4-7):
a) Connect the guard ring to the noninverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
pad, without touching the guard ring.
4.9 Unused Comparators
An unused amplifier in a quad package (MCP6549)
should be configured as shown in . ThisFigure 4-8
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see andFigure 2-15
Figure 2-18).
FIGURE 4-8: Unused Comparators.
4.10 Typical Applications
4.10.1 PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it reaches the comparator. shows anFigure 4-9
example of this approach.
FIGURE 4-9: Precise Inverting
Comparator.
4.10.2 WINDOWED COMPARATOR
Figure 4-10 shows one approach to designing a
windowed comparator. The wired-OR connection
produces a high output (logic 1) when the input voltage
is between VRB and VRT (where VRT > VRB).
FIGURE 4-10: Windowed Comparator.
Guard Ring
VSS
VIN- VIN+
¼ MCP6549
VDD
–
+
VREF
VDD
VDD
R1R2VOUT
VIN
VREF
VPU
RPU
MCP6546
MCP6041
VRT
1/2
VRB
VIN
VPU
RPU
VOUT
MCP6547
1/2
MCP6547
MCP6546/6R/6U/7/8/9
DS20001714H-page 18 2002-2022
Microchip Technology Inc. and its subsidiaries
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
5-Lead SC-70 ( )MCP6546, MCP6546U
Device I-Temp
Code
E-Temp
Code
MCP6546 ACNN Note 2
MCP6546U BBNN Note 2
Note 1: I-Temp parts prior to March 2005 are
marked “ACN”
2: SC-70-5 E-Temp parts not available at
this release of the data sheet.
Example: (I-temp)
AC25
5-Lead SOT-23 (MCP6546, MCP6546R, MCP6546U) Example: (I-temp)
Device I-Temp
Code
E-Temp
Code
MCP6546 ACNN GWNN
MCP6546R AHNN GXNN
MCP6546U — AWNN
Note: Applies to 5-Lead SOT-23
AC25
8-Lead PDIP (300 mil) (MCP6546, MCP6547, MCP6548, MCP6549) Examples:
OR
MCP6546
I/P^^256
1148
3
e
MCP6546
I/P256
1148
8-Lead SOIC (150 mil) (MCP6546, MCP6547, MCP6548, MCP6549)
OR
MCP6547 MCP6547
I/SN1148
256 256
S N ^^1148
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 19
MCP6546/6R/6U/7/8/9
Package Marking Information (Continued)
8-Lead MSOP (MCP6546, MCP6547, MCP6548) Example:
6546I
148256
14-Lead PDIP (300 mil) Example:(MCP6549)
OR
OR
MCP6549-I/P
1148256
1148256
1148256
MCP6549-E/P
3
e
I/P^^
3
e
MCP6549
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP6546/6R/6U/7/8/9
DS20001714H-page 24 2002-2022
Microchip Technology Inc. and its subsidiaries
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2002-2022
Microchip Technology Inc. and its subsidiaries
DS20001714H-page 27
MCP6546/6R/6U/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6546/6R/6U/7/8/9
DS20001714H-page 34 2002-2022
Microchip Technology Inc. and its subsidiaries
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: MCP6548

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