Microchip KSZ9893 Handleiding

Microchip Niet gecategoriseerd KSZ9893

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 2018 Microchip Technology Inc. DS00002756A-page 1
1.0 INTRODUCTION
This document provides a hardware design checklist for KSZ9893RNX. These checklist items should be followed when
utilizing the KSZ9893RNX in a new board design.
A summary of the hardware design checklist items is provided in Section 12.0, "Hardware Checklist Summary," on
page 30 . Detailed information on each checklist item can be found in the following corresponding sections:
• Package and Pin Considerations on page 2
• Reference Clock Circuits and Connections on page 3
• Power/Ground Connections on page 4
• ISET Resistor on page 5
• Ethernet PHY Ports on page 5
• Management Bus Selection on page 12
• MAC Port 3 – Digital Data Bus Interfaces on page 15
• LED Indicator Pins on page 27
• Miscellaneous on page 29
A listing of available KSZ9893RNX hardware design collaterals can be found in Section 11.0, "Reference Materials," on
page 29 .
KSZ9893RNX
Hardware Design Checklist
KSZ9893RNX
DS00002756A-page 2  2018 Microchip Technology Inc.
2.0 PACKAGE AND PIN CONSIDERATIONS
2.1 Package Orientation and Pin Numbering
Check to ensure the package orientation and pin numbering with respect to top view of package are in the counterclock-
wise direction. Refer to the KSZ9893RNX Data Sheet for additional information.
2.2 Pin Type
Check the pin-outs of the KSZ9893RNX device to ensure all pin types and directions match the KSZ9893RNX Data
Sheet and the interfacing devices are confi or bidirectional pin types for schegured with corresponding input, output, -
matic design rule error checking.
It is important to always check the pin types in the data sheet of the connecting pins between two devices to ensure the
adjoining pins are not both inputs and not both outputs. Do not rely on just the pin name of the bus interface between
two connecting devices. The same pin name may be defined as an input or an output depending on the interface per-
spective. This is especially for the RGMII, RMII, and MII pins, as defined from the PHY perspective or MAC perspective.
2.3 Configuration Strap Pins
The KSZ9893RNX utilizes configuration strap pins to configure the device for different modes. These strap pins are con-
figured by using internal and external pull-up/pull-down resistors to create a High or Low state on the pins which are
sampled at the end of a device power-up or software reset cycle. They are also latched when powering-up from a hard-
ware or software power-down or Hardware Reset state (rising edge of RESET_N).
In some systems, for example, the connecting MAC input pins may drive high during power-up or reset and conse-
quently cause the multiplexed strap-in pins on the RGMII/RMII/MII signals to be latched high instead of low. In this case,
it is recommended to add 1K pull-downs to these strap-in pins to ensure they latch low.
Check to ensure proper external pull-ups or pull-downs, as needed, are installed for all the strap pins as defined in the
KSZ9893RNX Data Sheet.
 2018 Microchip Technology Inc. DS00002756A-page 3
KSZ9893RNX
3.0 REFERENCE CLOCK CIRCUITS AND CONNECTIONS
A crystal or external clock source can be used to generate the 25 MHz reference clock for the device.
3.1 Crystal Circuit
The following notes for the crystal circuit refer to Figure 3-1:
• A 25.000 MHz (±50 ppm) crystal is recommended. Refer to the latest version of the KSZ9893RNX Data Sheet.
•XI (pin 58) is the crystal circuit input. This pin connects to one side of the crystal as well as a capacitor to ground.
•XO (pin 57) is the clock circuit output. This pin connects to the other side of the crystal and also connects to a
capacitor to ground.
• The external capacitor value for the crystal can vary and depends on the CL specifications of the selected crystal
and the stray capacitance of the PCB traces.
• The selected crystal and PCB design and layout contribute to the performance of the crystal circuit. Once the
board is brought up and is operational, a check for frequency accuracy and stability across the system operating
conditions is recommended.
FIGURE 3-1: CRYSTAL CIRCUIT
25MHzCrystal
±50ppm
C1
C2
XI
XO
58
57
3.2 External Clock Source/Oscillator Circuit
The following notes for the external clock/oscillator circuit refer to Figure 3-2:
• An external 25.000 MHz (±50 ppm) clock source, such as an oscillator, with a Total Period Jitter (peak-to-peak) of
less than 100 ps is recommended. Refer to the latest version of the KSZ9893RNX Data Sheet.
•XI (pin 58) is the input for the external clock source. A 22-ohm-to-50-ohm series source termination at the clock
output pin is recommended.
•XO (pin 57) is a no connect.
• The external clock source should reference the AVDDH voltage level supplied to the KSZ9893RNX device.
FIGURE 3-2:
XI
XO
NC
25 MHzOscillator
±50ppm
AVDDH = 3.3Vor2.5V
58
57
AVDDH
EXTERNAL CLOCK SOURCE/OSCILLATOR CIRCUIT

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: KSZ9893

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