Microchip HV2721 Handleiding

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2019 Microchip Technology Inc. DS20006082A-page 1
HV2621/HV2721/HV2722
Features
• 300V,16-Channel High-Voltage Analog Switch
• 3.3V or 5.0V CMOS Input Logic Level
• 33 MHz Data Shift Clock Frequency
• Very Low Quiescent Current (10 µA)
• Low Parasitic Capacitance
• DC to 50 MHz Analog Small-Signal Frequency
• -60 dB Typical Off Isolation at 5.0 MHz
• Excellent Noise Immunity
• Cascadable Serial Data Register with Latches
• Flexible Operating Supply Voltage
• Integrated Bleed Resistors on the Outputs (both
sides for HV2721, one side only for HV2722)
Applications
• Medical Ultrasound Imaging
• Nondestructive Testing (NDT) Metal Flaw
Detection
• Multi-Layer Printed Circuit Board (PCB) Tester
• Piezoelectric Transducer Drivers
• Inkjet Printer Head
• Optical MEMS Module
General Description
The HV2621/HV2721/HV2722 devices are 300V,
low-charge injection, 16-channel, high-voltage analog
switches. These devices are designed for use in
applications requiring high-voltage switching
controlled by low-voltage control signals, such as
medical ultrasound imaging, piezoelectric transducer
drivers. HV2621/HV2721 are almost identical to
HV2601/2701 but have larger signal range. If the
VPP/VNN = ±150V, HV2621/HV2721/HV2722 can pass
the analog signal up to ±135V.
The HV2721 has integrated bleed resistors on both
sides of the switches. HV2722 has integrated bleed
resistors on one side, SWxA only. HV2621 has no
bleed resistors. The bleed resistor eliminates voltage
build-up on capacitive loads such as piezoelectric
transducers.
Input data are shifted into a 16-bit shift register that
can then be retained in a 16-bit latch. To change all the
switch state at the same time, the latch enable bar
should be left high until all bits are clocked in. The
input data are clocked in at the rising edge of the
clock. After all bits are clocked in to the shift register, a
negative pulse of the latch enable bar changes all the
switch ON/OFF states defined by input data at the
same time. Using the HVCMOS technology, these
devices combine 300V high-voltage bilateral DMOS
switches and low-power CMOS logic to provide
efficient control of high-voltage analog signals.
These devices are suitable for various combinations of
high-voltage supplies, e.g., VPP/VNN: +60V/-240V,
+150V/-150V, and +260V/-40V.
Package Types
1
64
HV2621/HV2721/HV2722
9x9x1.0mm QFN
(TOP VIEW)
300V, Low-Charge Injection, 16-Channel,
High-Voltage Analog Switch
HV2621/HV2721/HV2722
DS20006082A-page 2 2019 Microchip Technology Inc.
Block Diagram
VNNCLR
CLK
DIN
GND
VDD
DOUT
Bleed
Resistors
RGNDLE
Latches
16-Bit
Shift
Register
Level
Shifter
Output
Switches
SW0A
SW0B
D
LE
CLR
SW1A
SW1B
D
LE
CLR
SW2A
SW2B
D
LE
CLR
SW14A
SW14B
D
LE
CLR
SW15A
SW15B
D
LE
CLR
HV2721 has bleed resistors at SWxA and SWxB
HV2722 has bleed resistors at SWxA only
VPP
2019 Microchip Technology Inc. DS20006082A-page 3
HV2621/HV2721/HV2722
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Logic Supply Voltage (VDD).......................................................................................................................... -0.5V to 6.5V
Differential Supply Voltage (V
PP-VNN).......................................................................................................................330V
Positive Supply Voltage (VPP).............................................................................................................-0.5V to V
NN+300V
Negative Supply Voltage (VNN)................................................................................................................. -300V to +0.5V
Logic Input Voltage (VIN).....................................................................................................................-0.5V to V
DD +0.3V
Analog Signal Range (V
SIG)............................................................................................................................ V
NN to VPP
Peak Analog Signal Current/Channel (I
PK) ...................................................................................................................3A
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (NOTES 1,,)2 3
Parameter Sym. Min. Typ. Max. Units Conditions
Logic Supply Voltage VDD 3 — 5.5 V
Differential Supply Voltage VPP-VNN 60 — 300 V
Positive Supply Voltage V
PP 60 — 260 V
Negative Supply Voltage VNN -240 — 0 V
High-Level Input Voltage VIH 0.9VDD — VDD V
Low-Level Input Voltage V
IL 0 — 0.1VDD V
Analog Signal Voltage Peak-to-Peak VSIG VNN+15 — VPP-15 V
Note 1: Recommended power up sequence is VDD, VPP and VNN. Power down is in reverse order.
2: VSIG must be VNN
≤ V SIG ≤ VPP or floating during power up/down transition.
3: Rise and fall times of power supplies, V
DD, VPP and VNN should be greater than 1.0 ms.
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
PP = +150V, VNN = -150V, VDD = 5.0V, TA= 25°C. Boldface specifications apply over
the full operating temperature range.
Parameter Sym. Min. Typ. Max. Units Conditions/Comments
Small Signal Switch On-Resistance RONS
— 26 48 ΩISIG
= 5 mA VPP = +60V,
VNN
= -240V
— 22 32 ΩISIG
= 150 mA
— 22 30 ΩISIG
= 5 mA VPP = +150V,
VNN
= -150V
— 18 27 ΩISIG
= 150 mA
— 20 30 ΩISIG
= 5 mA VPP = +260V,
VNN
= -40V
— 16 27 ΩISIG
= 150 mA
Small Signal Switch On-Resistance
Matching ∆RONS — 5 20 %ISIG
= 5 mA, VPP = +150V,
VNN
= -150V
Large Signal Switch On-Resistance RONL — 17 — ΩVSIG
= V PP-15V, ISIG =1A
Value of Output Bleed Resistor
(HV2721/HV2722 Only) RINT 30 50 70 kΩOutput switch to RGND,
IRINT = 0.5 mA
Switch Off Leakage per Switch ISOL — 1 15 μAVSIG
= V PP-15V, VNN+15V.
See Figure 3-1
DC Offset Switch Off
VOS
— 1 10
mV
RLOAD = 35 kΩ (HV2621), 70 kΩ
(HV2722), No load (HV2721), see
Figure 3-2
DC Offset Switch On — 1 10
HV2621/HV2721/HV2722
DS20006082A-page 4 2019 Microchip Technology Inc.
Quiescent VPP Supply Current IPPQ — 10 50 μAAll switches off
Quiescent VNN Supply Current INNQ — 10 50 μA
Quiescent VPP Supply Current IPPQ — 10 50 μAAll switches on, ISW = 5.0 mA
Quiescent VNN Supply Current INNQ — 10 50 μA
Switch Output Peak Current ISW 2.0 3.0 — A VSIG duty cycle <0.1% (Note 1)
Output Switching Frequency fSW — — 50 kHz Duty cycle = 50% (Note 1)
Average VPP Supply Current I
PP
— — 3mA VPP = +60V,
VNN = -240V All output
switches are
turning on and off
at 10 kHz with no
load
— — 4mA VPP = +150V,
VNN = -150V
—
——6mA VPP = +260V,
VNN = -40V
Average VNN Supply Current INN
— — 3mA VPP = +60V,
VNN = -240V All output
switches are
turning on and off
at 10 kHz with no
load
— — 4mA VPP = +150V,
VNN = -150V
—
——6mA VPP = +260V,
VNN = -40V
Average VDD Supply Current IDD — — 4mA fCLK = 5 MHz, fDIN= 2.5 MHz
Quiescent VDD Supply Current IDDQ — — 10 μA All logic inputs are static
Data Out Source Current ISOR 8— — mA VOUT = VDD -0.7V
Data Out Sink Current ISINK 12 — — mA VOUT = 0.7V
Logic Input Capacitance CIN — — 10 pF Note 2
Note 1: Specification is obtained by characterization and is not 100% tested.
2: Design guidance only.
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VPP = +150V, VNN = -150V, VDD = 5.0V, tR= tF≤5.0 ns, 50% duty cycle, CLOAD = 20 pF,
TA= 25°C, Boldface specifications apply over the full operating temperature range.
Sym. Sym. Min. Typ. Max. Units Conditions/Comments
Setup Time before LE rises tSD 25 — — ns Note 1
Time Width of LE tWLE
56 — — ns VDD = 3.3V (Note 1)
12 — — ns VDD = 5.0V (Note 1)
Clock Delay Time to Data Out tDO
- — 45 ns VDD = 3.3V
- — 25 ns VDD = 5.0V
Time Width of CLR tWCLR 55 — — ns Note 1
Setup Time Data to Clock tSU
7— — ns VDD = 3.3V (Note 1)
7— — ns VDD = 5.0V (Note 1)
Hold Time Data from Clock tH
4— — ns VDD = 3.3V (Note 1)
3.5 ns VDD = 5.0V (Note 1)
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, VPP = +150V, VNN = -150V, V
DD = 5.0V, TA= 25°C. Boldface specifications apply over
the full operating temperature range.
Parameter Sym. Min. Typ. Max. Units Conditions/Comments
2019 Microchip Technology Inc. DS20006082A-page 5
HV2621/HV2721/HV2722
Clock Frequency fCLK
— — 16 MHz VDD = 3.3V (Note 1)
— — 33 MHz VDD = 5.0V (Note 1)
Clock Rise and Fall Time tR, tF— — 50 ns Note 1
Turn-On Time tON — — 6μsVSIG = VPP-15V, RLOAD = 20 kΩ
See Figure 3-3
Turn-Off Time tOFF — — 6
Maximum VSIG Slew Rate dV/dt
— — 20
V/ns
VPP = +60V, V
NN = -240V (Note 1)
— — 20 VPP = +150V, V
NN = -150V ( )Note 1
— — 20 VPP = +260V, V
NN = -40V (Note 1)
Off Isolation KO
— -55 -50
dB
f = 5.0 MHz,1.0 kΩ//15 pF load
See Figure 3-4 ( )Note 1
— -60 -58 f = 5.0 MHz, 50Ω load
See Figure 3-4 ( )Note 1
Switch Crosstalk KCR — -70 -60 dB f = 5.0 MHz, 50Ω load
See Figure 3-5 ( )Note 1
Output Switch Isolation Diode
Current IID — — 200 mA 300 ns pulse width, 2.0% duty cycle,
See Figure 3-6 ( )Note 1
Off Capacitance SW to GND CSG(OFF) — 10 — pF VSIG = 50 mV@1MHz, no load
( )Note 1
On Capacitance SW to GND CSG(ON) — 18 —
Output Voltage Spike at SWA,
SWB
+V
SPK — — 250
mV
VPP = +60V, V
NN = -240V,
RLOAD = 50Ω, see Figure 3-7 (Note 1)
-VSPK -250 — —
+V
SPK — — 250 VPP = +150V, V
NN = -150V,
RLOAD = 50Ω, see Figure 3-7 (Note 1)
-VSPK -250 — —
+V
SPK — — 250 VPP = +260V, V
NN = -40V,
RLOAD = 50Ω, see Figure 3-7 (Note 1)
-VSPK -250 — —
Charge Injection QC
— 1000 —
pC
VPP = +60V, V
NN = -240V,
VSIG = 0V, see Figure 3-8 (Note 1)
— 770 — VPP = +150V, V
NN = -150V,
VSIG = 0V, see Figure 3-8 (Note 1)
— 360 — VPP = +260V, V
NN = -40V,
VSIG=0V, see Figure 3-8 (Note 1)
Note 1: Specification is obtained by characterization and is not 100% tested.
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, VPP = +150V, VNN = -150V, VDD = 5.0V, tR= tF≤5.0 ns, 50% duty cycle, CLOAD = 20 pF,
TA= 25°C, Boldface specifications apply over the full operating temperature range.
Sym. Sym. Min. Typ. Max. Units Conditions/Comments
TEMPERATURE SPECIFICATION
Parameters Sym Min Typ Max Units Conditions
Temperature Range
Operating Temperature Range TA0 — +70 °C
Storage Temperature Range TS-65 — +150 °C
Maximum Junction Temperature TJ— — +125 °C
Package Thermal Resistance
Thermal Resistance, 64L QFN ΘJA — 21 — °C/W
HV2621/HV2721/HV2722
DS20006082A-page 6 2019 Microchip Technology Inc.
TABLE 1-1: TRUTH TABLE (NOTES 1, , , , , )23456
D0 D1 ... D7 D8 ... D15 LE CLR SW0 SW1 ... SW7 SW8 ... SW15
L —
...
— —
...
— L L OFF —
...
— —
...
—
H — — — — L L ON — — — —
— L — — — L L — OFF — — —
— H — — — L L — ON — — —
— — — — — L L — — — — —
— — — — — L L — — — — —
— — L — — L L — — OFF — —
— — H — — L L — — ON — —
— — — L — L L — — — OFF —
— — — H — L L — — — ON —
— — — — — L L — — — — —
— — — — — L L — — — — —
— — — — L L L — — — — OFF
— — — — H L L — — — — ON
X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X H ALL SWITCHES OFF
Note 1: The 16 switches operate independently.
2: Serial data is clocked in on the L to H transition of the CLK.
3: All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the shift registers
data flow through the latch.
4: DOUT is high when data in the register 15 is high.
5: Shift register clocking has no effect on the switch states if LE is high.
6: The CLR clear input overrides all the inputs.
2019 Microchip Technology Inc. DS20006082A-page 7
HV2621/HV2721/HV2722
1.1 Typical Timing Diagrams
Figure 1-1 shows the timing of the AC characteristic
parameters graphically.
FIGURE 1-1: Logic Input Timing Diagram.
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DS20006082A-page 8 2019 Microchip Technology Inc.
2.0 PIN DESCRIPTION
This section details the pin description for 64-lead QFN
package (Figure 2-1).The descriptions of the pins are
listed in Table 2-1.
FIGURE 2-1: 64-Lead QFN Package - Top View.
TABLE 2-1: PIN FUNCTION TABLE
Pin
Number
Symbol
Description
HV2621 HV2721/
HV2722
1 SW5A SW5A Analog Switch 5 Terminal A
2 NC NC No Connection
3 SW4B SW4B Analog Switch 4 Terminal B
4 SW4A SW4A Analog Switch 4 Terminal A
5 NC NC No Connection
6 SW3B SW3B Analog Switch 3 Terminal B
7 SW3A SW3A Analog Switch 3 Terminal A
8 NC NC No Connection
9 SW2B SW2B Analog Switch 2 Terminal B
10 SW2A SW2A Analog Switch 2 Terminal A
11 NC NC No Connection
1
64
NC
NC
VPP
GND
VDD
DIN
CLK
LE
CLR
SW11A
NC
NC
SW11B
SW12A
SW12B
SW13A
SW13B
SW14A
SW14B
SW15A
SW5B
SW6A
SW6B
SW7A
SW7B
NC
SW8A
SW8B
SW9A
SW9B
SW10A
SW10B
NC
NC
SW4B
SW4A
SW3B
SW3A
SW2B
SW2A
SW1B
SW1A
SW0B
NC
NC
SW0A
NC
NC
VNN
DOUT
SW15B
NC
NC
NC/RGND
NC
SW5A
NC
NC
TOP VIEW
NC
VPP
VNN
NC
NC
NC
2019 Microchip Technology Inc. DS20006082A-page 9
HV2621/HV2721/HV2722
12 SW1B SW1B Analog Switch 1 Terminal B
13 SW1A SW1A Analog Switch 1 Terminal A
14 NC NC No Connection
15 SW0B SW0B Analog Switch 0 Terminal B
16 SW0A SW0A Analog Switch 0 Terminal A
17 VNN VNN Negative Supply Voltage
18 NC NC No Connection
19 VPP VPP Positive Supply Voltage
20 NC NC No Connection
21 CLR CLR Latch Clear Logic Input
22 LE LE Latch Enable Logic Input
23 GND GND Ground
24 VDD VDD Logic Supply Voltage
25 DIN DIN Data In Logic Input
26 CLK CLK Clock Logic Input for Shift Register
27 DOUT DOUT Data Out Logic Output
28 NC NC No Connection
29 VPP VPP Positive Supply Voltage
30 NC NC No Connection
31 VNN VNN Negative Supply Voltage
32 NC NC No Connection
33 NC RGND No Connection/Ground for Bleed Resistor
34 NC NC No Connection
35 SW15B SW15B Analog Switch 15 Terminal B
36 SW15A SW15A Analog switch 15 Terminal A
37 NC NC No Connection
38 SW14B SW14B Analog Switch 14 Terminal B
39 SW14A SW14A Analog Switch 14 Terminal A
40 NC NC No Connection
41 SW13B SW13B Analog Switch 13 Terminal B
42 SW13A SW13A Analog switch 13 Terminal A
43 NC NC No Connection
44 SW12B SW12B Analog Switch 12 Terminal B
45 SW12A SW12A Analog Switch 12 Terminal A
46 NC NC No Connection
47 SW11B SW11B Analog Switch 11 Terminal B
48 SW11A SW11A Analog Switch 11 Terminal A
49 SW10B SW10B Analog Switch 10 Terminal B
50 SW10A SW10A Analog Switch 10 Terminal A
51 NC NC No Connection
52 SW9B SW9B Analog Switch 9 Terminal B
53 SW9A SW9A Analog Switch 9 Terminal A
54 NC NC No Connection
Pin
Number
Symbol
Description
HV2621 HV2721/
HV2722
HV2621/HV2721/HV2722
DS20006082A-page 10 2019 Microchip Technology Inc.
55 SW8B SW8B Analog Switch 8 Terminal B
56 SW8A SW8A Analog Switch 8 Terminal A
57 NC NC No Connection
58 SW7B SW7B Analog Switch 7 Terminal B
59 SW7A SW7A Analog Switch 7 terminal A
60 NC NC No Connection
61 SW6B SW6B Analog Switch 6 Terminal B
62 SW6A SW6A Analog Switch 6 Terminal A
63 NC NC No Connection
64 SW5B SW5B Analog Switch 5 Terminal B
VSUB (Thermal Pad) The central thermal pad on the bottom of package must be connected to
VNN externally
Pin
Number
Symbol
Description
HV2621 HV2721/
HV2722
2019 Microchip Technology Inc. DS20006082A-page 11
HV2621/HV2721/HV2722
3.0 TEST CIRCUIT EXAMPLES
This section details a few example of test circuits.
FIGURE 3-1: Switch Off Leakage per
Switch.
FIGURE 3-2: DC Offset Switch On/Off.
FIGURE 3-3: TON/TOFF Test Circuit.
FIGURE 3-4: Off Isolation.
FIGURE 3-5: Switch Crosstalk.
I
FIGURE 3-6: Isolation Diode Current.
VPP -1V
RGND
Open
V
PP
5V
V
NN
VPP
VNN
VDD
Open
ISOL
GND
RGND
V
PP
5V
V
NN
VPP
VNN
VDD
GND
V
OUT
R
LOAD
RGND
5V
GND
V
PP
-1V
0kΩ
V
OUT
R
LOAD
V
PP
V
NN
VPP
VNN
VDD
RGND
VIN = 10V
P-P
@5MHz
NC
5V
GND
50Ω
50Ω
V
PP
V
NN
VPP
VNN
VDD
KCR = 20Log
VOUT
VIN
RGND
IID
5V
GND
VNN
VSIG
V
PP
VNN
VPP
VNN
VDD
HV2621/HV2721/HV2722
DS20006082A-page 12 2019 Microchip Technology Inc.
FIGURE 3-7: Output Voltage Spike. FIGURE 3-8: Charge Injection.
RGND
5V
GND
VOUT
1kΩ
RLOAD 50Ω
+V SPK
–VSPK
VPP
VNN
VPP
VNN
VDD
RGND
Q = 1000pF x ΔV
OUT
5V
GND
V
PP
V
NN
VPP
VNN
VDD
V
OUT
ΔV
OUT
1000pF
V
SIG
2019 Microchip Technology Inc. DS20006082A-page 13
HV2621/HV2721/HV2722
4.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, VPP = +150V, VNN = -150V, VDD = 5.0V, TA= 25°C.
FIGURE 4-1: IPP/INN vs. Switching
Frequency.
FIGURE 4-2: IPPQ/INNQ vs. Temperature.
FIGURE 4-3: IDDQ vs. Temperature.
FIGURE 4-4: TON/TOFF vs. Temperature.
FIGURE 4-5: IDD vs. CLK Frequency.
FIGURE 4-6: KO vs. Frequency with 50Ω
Load.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
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DS20006082A-page 14 2019 Microchip Technology Inc.
5.0 DETAILED DESCRIPTION AND
APPLICATION INFORMATION
5.1 Device Overview
The HV2621/HV2721/HV2722 are 300V, low-charge
injection, 16-channel, high-voltage analog switches.
The high-voltage analog switches are used for
multiplexing a piezoelectric transducer array in a
probe to multiple channel transmitters (Tx) arrays in a
medical ultrasound system.
The HV2621/HV2721/HV2722 are distinguished by
bleed resistors that eliminate voltage build-up in
capacitance load such as piezoelectric transducers.
These devices can pass ±135V high-voltage large
signal with VPP/VNN = ±150V. These devices have
typical 18Ω on-resistance and 50 MHz bandwidth for
small-signals.
Figure 5-1 shows a typical medical ultrasound image
system consisting 64-channels of transmit pulsers,
64-channels of receivers (LNA and ADC) and
64-channels of T/R switches connecting to 192 ele-
ments of an ultrasound probe via a HV2XXX
high-voltage analog switch array.
FIGURE 5-1: Typical Medical Ultrasound Imaging System.
5.2 Logic Input Timing
The HV2621/HV2721/HV2722 have digital serial
interface consisting of Data In (DIN), Clock (CLK), Data
Out (DOUT), Latch Enable (LE), and Clear (CLR) to
control 16 switches individually. The digital circuits are
supplied by VDD. The serial clock frequency is up to
33 MHz.
The switch state configuration data is shifted into the
shift registers at the rising edge (low-to-high transition)
of the clock. The switch configuration bit of SW15 is
shifted in first and the configuration bit of SW0 is
shifted in last. To change all the switch states at the
same time, the Latch Enable Input (LE) should remain
high while the 16-bit Data In signal is shifted into the
16-bit register. After the valid 16-bit data completes
shifting into the shift registers, the high-to-low transi-
tion of the LE signal transfers the contents of the shift
registers into the latches. Finally, setting the LE high
again, allows all the latches to keep the current state
while new data can now be shifted into the shift
registers without disturbing the latches.
It is recommended to change all the latch states at the
same time through this method to avoid possible clock
feed through noise (see Figure 5-2 for details).
When the CLR input is set high, it resets the data of all
16 latches to low. Consequently, all the high-voltage
switches are set to OFF state. However, the CLR
signal does not affect the contents of the shift register,
so the shift register can operate regardless of the CLR
signal. Therefore, when the CLR input is low, the shift
register still retains the previous data.
Tx
Rx
Tx
Rx
Tx
Rx
FPGA Ctrl Logic
CPU MEMORY
E1
E65
E192
E128
VIDEO
E129
E2
E66
E130
E64
CH1
CH2
CH64
ADC
ADC
ADC
HV 2XXX SW Array
PZT Array
Tx / Rx Array
T/R
Switch
T/R
Switch
T/R
Switch
2019 Microchip Technology Inc. DS20006082A-page 15
HV2621/HV2721/HV2722
FIGURE 5-2: Latch Enable Timing Diagram.
5.3 Multiple Devices Connection
The digital serial interface of the HV2621/
HV2721/HV2722 allows multiple devices to make a
daisy-chain together. In this configuration, DOUT of a
device is connected to the DIN of the subsequent
device, and so forth. The last D
OUT of the
daisy-chained HV2621/HV2721/HV2722 can be either
floating or fed back to an FPGA to check the previously
stored data in the shift registers.
To control all the high-voltage analog switch states in
daisy-chained N devices, N-times 16 clocks and
N-times 16 bits of data are shifted into shift registers,
while LE remains high and CLR remains low. After all
the data finishes shifting in, one single negative pulse
of LE transfers the data from all the shift registers to all
the latches simultaneously. Consequently, all N-times
16 high-voltage analog switches change states
simultaneously.
5.4 Power Up/Down Sequence and
Decoupling Capacitor
The recommended power up sequence is VDD, VPP
and VNN. The power down sequence is in reverse
order. We also recommend the rise time and fall time
of power supplies are greater than 1 msec. During the
power up/down period, all the analog switch inputs
should be within between VPP and VNN or floating.
It is recommended that 0.1 µF or larger ceramic
decoupling capacitors, with the appropriate voltage
ratings, be connected between GND and other
supplies (VPP
, VNN and VDD). These decoupling
capacitors should be placed as close as possible to
the device.
W:/(
W6'
W+
W68
W'2
'1 '1 '1 '1'
1
'1 '1 '1 '1'1'1
6KLIW5HJLVWHU'DWDIURP3UHYLRXV'DWD,QSXWVDUH6KLIWHG2XW
&/.
'287
/(
',1
HV2621/HV2721/HV2722
DS20006082A-page 16 2019 Microchip Technology Inc.
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
3
e
3
e
64-Pin QFN (9 x 9 mm) Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
PIN 1
PIN 1
HV2621
1826256
3
e
2019 Microchip Technology Inc. DS20006082A-page 17
HV2621/HV2721/HV2722
B
A
0.25 C
0.25 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
1
2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-149D [R4X] Sheet 1 of 2
2X
64X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
9.00
9.00
D2
E2
e
e
2
64X b
K
L
A
(A3)
A1
HV2621/HV2721/HV2722
DS20006082A-page 18 2019 Microchip Technology Inc.
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
0.500.30 0.40Contact Length L
Contact-to-Exposed Pad K -0.20 -
Overall Height
Overall Length
Exposed Pad Width
Contact Thickness
Number of Pins
Contact Width
Exposed Pad Length
Overall Width
Standoff
Pitch
E2
D2
b
D
A3
E
A1
7.257.05 7.15
9.00 BSC
0.25
7.157.05
0.18
7.25
0.30
0.02
9.00 BSC
0.20 REF
0.00 0.05
Dimension Limits
e
A
N
Units
MAXMIN NOM
0.50 BSC
0.90
64
0.80 1.00
MILLIMETERS
Microchip Technology Drawing C04-149D [R4X] Sheet 2 of 2
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
2019 Microchip Technology Inc. DS20006082A-page 19
HV2621/HV2721/HV2722
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
7.25
7.25
MILLIMETERS
0.50 BSC
MIN
E
MAX
9.00
Contact Pad Length (X64)
Contact Pad Width (X64)
Y1
X1
0.95
0.30
Microchip Technology Drawing C04-149C [R4X]
NOM
1
2
20
C1Contact Pad Spacing 9.00
Contact Pad to Center Pad (X64) G1 0.40
Thermal Via Diameter V
Thermal Via Pitch EV
0.33
1.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Y1
C1
C2
Y2
E
E
2
X1
Y1
G2
EV
EV
Spacing Between Contact Pads (X60) G2 0.20
G1
ØV
SILK SCREEN
64-Lead Very Thin Plastic Quad Flat, No Lead Package (R4X) – 9x9x0.9 mm Body [VQFN]
With 7.15 x 7.15 Exposed Pad [Also called QFN]
HV2621/HV2721/HV2722
DS20006082A-page 20 2019 Microchip Technology Inc.
NOTES:
HV2621/HV2721/HV2722
DS20006082A-page 22 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006082A-page 23
HV2621/HV2721/HV2722
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. /XX
Package
Device
Device: HV2621: 300V, Low-Charge Injection 16-Channel High-
Voltage Analog Switch
HV2721: 300V, Low-Charge Injection 16-Channel High-
Voltage Analog Switch with Bleed Resistor at Both
Sides of Switch
HV2722: 300V, Low-Charge Injection 16-Channel High-
Voltage Analog Switch with Bleed Resistor at One
Side of Switch
Package: R4X= Very Thin Plastic Quad Flat Pack, No Lead Package
– 9x9x0.9 mm Body, 64-Lead (QFN)
Examples:
a) HV2621/R4X: 16-Channel High-Voltage Analog
Switch, 64-lead QFN
HV2621/HV2721/HV2722
DS20006082A-page 24 2019 Microchip Technology Inc.
NOTES:
2019 Microchip Technology Inc. DS20006082A-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-5019-1
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are co g the code protection features ofmmitted to continuously improvin our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
DS20006082A-page 26 2019 Microchip Technology Inc.
AMERICAS
Corporate Office
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Worldwide Sales and Service
05/14/19

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: HV2721

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