Microchip dsPIC33/PIC24FRM Handleiding

Microchip Niet gecategoriseerd dsPIC33/PIC24FRM

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 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 1
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CAN FD Message Frames................................................................................................ 5
3.0 Control Registers .............................................................................................................. 9
4.0 Modes of Operation ........................................................................................................ 53
5.0 Configuration................................................................................................................... 59
6.0 Message Transmission ................................................................................................... 72
7.0 Transmit Event FIFO – TEF ............................................................................................ 81
8.0 Message Filtering............................................................................................................ 86
9.0 Message Reception ........................................................................................................ 91
10.0 FIFO Behavior................................................................................................................. 97
11.0 Timestamping................................................................................................................ 108
12.0 Interrupts....................................................................................................................... 109
13.0 Error Handling............................................................................................................... 116
14.0 Related Application Notes............................................................................................. 118
15.0 Revision History ............................................................................................................ 119
CAN Flexible Data-Rate (FD) Protocol Module
dsPIC33/PIC24 Family Reference Manual
DS70005340C-page 2 2018-2022 Microchip Technology Inc.and its subsidiaries
1.0 INTRODUCTION
CAN Flexible Data-Rate (FD) addresses the increasing demand for bandwidth on CAN buses.
The two major enhancements over CAN 2.0B consist of:
• Increased data field of up to 64 data bytes (from a maximum eight data bytes for CAN 2.0B)
• Option to switch to faster bit rate after the arbitration field
Figure 1-1 shows the possible increase in net bit rate due to the higher Data Bit Rate (DBR) and
increased data bytes per frame.
Figure 1-1: Net CAN FD Bit Rate
The CAN FD protocol is defined to allow CAN 2.0 messages and CAN FD messages to coexist
on the same bus. This does not imply that non-CAN FD controllers can be mixed with CAN FD
controllers on the same bus. Non-CAN FD controllers will generate error frames while receiving
a CAN FD message.
1.1 Features
The CAN FD module has the following features:
General
• Nominal (Arbitration) Bit Rate up to 1 Mbps
• Data Bit Rate up to 8 Mbps
• CAN FD Controller modes:
- Mixed CAN 2.0B and CAN FD mode
- CAN 2.0B mode
• Conforms to ISO11898-1:2015
Message FIFOs
• 31 FIFOs Configurable as Transmit or Receive FIFOs
• One Transmit Queue (TXQ)
• Transmit Event FIFO (TEF) with 32-Bit Timestamp
Message Transmission
• Message Transmission Prioritization:
- Based on priority bit field and/or
- Message with lowest ID gets transmitted first using the TXQ
• Programmable Automatic Retransmission Attempts: Unlimited, Three Attempts or Disabled
Frame ID: 11-Bit, Bit Rate Arbitration: 1 Mbit
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 3
CAN FD Protocol Module
Message Reception
• 32 Flexible Filter and Mask Objects
• Each Object can be Configured to Filter either:
- Standard ID and first 18 data bits or
- Extended ID
• 32-Bit Timestamp
• The CAN FD Bit Stream Processor (BSP) implements the Medium Access Control (MAC)
of the CAN FD protocol described in ISO11898-1:2015. It serializes and deserializes the bit
stream, encodes and decodes the CAN FD frames, manages the medium access,
Acknowledges frames, and detects and signals errors.
• The TX handler prioritizes the messages that are requested for transmission by the
transmit FIFOs. It uses the RAM interface to fetch the transmit data from RAM and provides
it to the BSP for transmission.
• The BSP provides received messages to the RX handler. The RX handler uses an
acceptance filter to filter the messages that shall be stored in the receive FIFOs. It uses the
RAM interface to store received data into RAM.
• Each FIFO can be configured either as a transmit or receive FIFO. The FIFO control keeps
track of the FIFO head and tail, and calculates the user address. In a TX FIFO, the user
address points to the address in RAM where the data for the next transmit message is
stored. In an RX FIFO, the user address points to the address in RAM where the data of the
next receive message will be read. The user notifies the FIFO that a message is written to
or read from RAM by incrementing the head/tail of the FIFO.
• The TXQ is a special transmit FIFO that transmits the messages based on the ID of the
messages stored in the queue.
• The TEF stores the message IDs of the transmitted messages.
• A free-running Time Base Counter (TBC) is used to timestamp received messages.
Messages in the TEF can also be timestamped.
• The CAN FD controller module generates interrupts when new messages are received or
when messages are transmitted successfully.

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: dsPIC33/PIC24FRM

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