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2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 1
This section of the manual contains the following major topics:
1.0 Introduction ....................................................................................................................... 2
2.0 CAN FD Message Frames................................................................................................ 5
3.0 Control Registers .............................................................................................................. 9
4.0 Modes of Operation ........................................................................................................ 53
5.0 Configuration................................................................................................................... 59
6.0 Message Transmission ................................................................................................... 72
7.0 Transmit Event FIFO – TEF ............................................................................................ 81
8.0 Message Filtering............................................................................................................ 86
9.0 Message Reception ........................................................................................................ 91
10.0 FIFO Behavior................................................................................................................. 97
11.0 Timestamping................................................................................................................ 108
12.0 Interrupts....................................................................................................................... 109
13.0 Error Handling............................................................................................................... 116
14.0 Related Application Notes............................................................................................. 118
15.0 Revision History ............................................................................................................ 119
CAN Flexible Data-Rate (FD) Protocol Module
dsPIC33/PIC24 Family Reference Manual
DS70005340C-page 2 2018-2022 Microchip Technology Inc.and its subsidiaries
1.0 INTRODUCTION
CAN Flexible Data-Rate (FD) addresses the increasing demand for bandwidth on CAN buses.
The two major enhancements over CAN 2.0B consist of:
• Increased data field of up to 64 data bytes (from a maximum eight data bytes for CAN 2.0B)
• Option to switch to faster bit rate after the arbitration field
Figure 1-1 shows the possible increase in net bit rate due to the higher Data Bit Rate (DBR) and
increased data bytes per frame.
Figure 1-1: Net CAN FD Bit Rate
The CAN FD protocol is defined to allow CAN 2.0 messages and CAN FD messages to coexist
on the same bus. This does not imply that non-CAN FD controllers can be mixed with CAN FD
controllers on the same bus. Non-CAN FD controllers will generate error frames while receiving
a CAN FD message.
1.1 Features
The CAN FD module has the following features:
General
• Nominal (Arbitration) Bit Rate up to 1 Mbps
• Data Bit Rate up to 8 Mbps
• CAN FD Controller modes:
- Mixed CAN 2.0B and CAN FD mode
- CAN 2.0B mode
• Conforms to ISO11898-1:2015
Message FIFOs
• 31 FIFOs Configurable as Transmit or Receive FIFOs
• One Transmit Queue (TXQ)
• Transmit Event FIFO (TEF) with 32-Bit Timestamp
Message Transmission
• Message Transmission Prioritization:
- Based on priority bit field and/or
- Message with lowest ID gets transmitted first using the TXQ
• Programmable Automatic Retransmission Attempts: Unlimited, Three Attempts or Disabled
Frame ID: 11-Bit, Bit Rate Arbitration: 1 Mbit
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 3
CAN FD Protocol Module
Message Reception
• 32 Flexible Filter and Mask Objects
• Each Object can be Configured to Filter either:
- Standard ID and first 18 data bits or
- Extended ID
• 32-Bit Timestamp
• The CAN FD Bit Stream Processor (BSP) implements the Medium Access Control (MAC)
of the CAN FD protocol described in ISO11898-1:2015. It serializes and deserializes the bit
stream, encodes and decodes the CAN FD frames, manages the medium access,
Acknowledges frames, and detects and signals errors.
• The TX handler prioritizes the messages that are requested for transmission by the
transmit FIFOs. It uses the RAM interface to fetch the transmit data from RAM and provides
it to the BSP for transmission.
• The BSP provides received messages to the RX handler. The RX handler uses an
acceptance filter to filter the messages that shall be stored in the receive FIFOs. It uses the
RAM interface to store received data into RAM.
• Each FIFO can be configured either as a transmit or receive FIFO. The FIFO control keeps
track of the FIFO head and tail, and calculates the user address. In a TX FIFO, the user
address points to the address in RAM where the data for the next transmit message is
stored. In an RX FIFO, the user address points to the address in RAM where the data of the
next receive message will be read. The user notifies the FIFO that a message is written to
or read from RAM by incrementing the head/tail of the FIFO.
• The TXQ is a special transmit FIFO that transmits the messages based on the ID of the
messages stored in the queue.
• The TEF stores the message IDs of the transmitted messages.
• A free-running Time Base Counter (TBC) is used to timestamp received messages.
Messages in the TEF can also be timestamped.
• The CAN FD controller module generates interrupts when new messages are received or
when messages are transmitted successfully.
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 5
CAN FD Protocol Module
2.0 CAN FD MESSAGE FRAMES
The ISO11898-1:2015 describes the different CAN message frames in detail. Figure 2-1
through explain and summarize the construction of the messages and fields.Figure 2-6
There are four different CAN data/remote frames (see Figure 2-2):
• Classic CAN 2.0 frame using Standard IDCAN Base Frame:
• CAN FD frame using Standard IDCAN FD Base Frame:
• Classic CAN 2.0 frame using Extended IDCAN Extended Frame:
• CAN FD frame using Extended IDCAN FD Extended Frame:
There are no remote frames in CAN FD frames; therefore, the RTR bit is replaced with the RRS
bit (see ). The RRS bit in the CAN FD base frame can be used to extend the SID toFigure 2-2
12 bits. When enabled, it is referred to as SID11; it is the Least Significant bit (LSb) of SID[11:0].
Figure 2-3 specifies the control field of the different CAN messages. Before CAN FD was added
to the ISO11898-1:2015, the FDF bit was a reserved bit. Now the FDF bit selects between
Classic and CAN FD formats.
The BRS bit selects if the bit rate should be switched in the data phase of CAN FD frames.
Figure 2-6 illustrates the error and overload frames. These special frames do not change.
2.1 ISO vs. Non-ISO CRC
To support the system validation of non-ISO CRC ECUs, the CAN FD controller module sup-
ports both ISO CRC (according to ISO11898-1:2015) and non-ISO CRC (see andFigure 2-4
Figure 2-5). The CRC field is selectable using the ISOCRCEN bit (CxCONL[5]). The ISO CRC
field contains the stuff count. This count was not included in the original CAN FD specification; it
was added to fix a minor issue in the error detection of the original specification.
CAN FD frames use two different lengths of CRC: 17-bit for up to 16 data bytes and 21-bit for
20 or more data bytes. Technically, there are a total of six different CAN data/remote frames in
the CAN FD.
Figure 2-1: General Data Frame
Note: If an error is detected during the data phase of a CAN FD frame, the bit rate will be
switched back to the Nominal Bit Rate (NBR). Error frames are always transmitted
at the arbitration bit rate.
IFS
(= 3b)
SOF
(1b) ARBITRATION (12/32b) CTRL (6/8/9b) DATA
(0 to 64 bytes)
CRC (16/18/22b)
CRC (16/22/26b) ACK (2b) EOF (7b) IFS
(= 3b)
DATA FRAME
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DS70005340C-page 6 2018-2022 Microchip Technology Inc.and its subsidiaries
Figure 2-2: Arbitration Field
Figure 2-3: Control Field
Figure 2-4: ISO CRC Field
ARBITRATION (12/32b)
SID[10:0] RTR
SID[10:0] RRS
SID11
EID[28:18] SRR IDE EID[17:0] RTR
EID[28:18] SRR IDE EID[17:0] RRS
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CTRL (6/8/9b)
IDE FDF
IDE ESI
FDF DLC[3:0]
FDF ESI DLC[3:0]
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
DLC[3:0]
FDF BRS DLC[3:0]
r0
res BRS
res
CRC (16/22/26b)
CRC (15b)
CRC (15b)
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CRC
CRC (17/21b)
BRS
DEL
CRC
DEL
STUFF
CNT (4b)
CRC
DEL
STUFF
CNT (4b)
CRC
DEL
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 7
CAN FD Protocol Module
Figure 2-5: Non-ISO CRC Field
Figure 2-6: Error and Overload Frame
CRC (16/18/22b)
CRC (15b)
CRC (15b)
CAN Base
CAN FD Base
CAN Ext.
CAN FD Ext.
CRC
CRC (17/21b)
CRC (17/21b)
DEL
CRC
DEL
CRC
DEL
CRC
DEL
ANYWHERE WITHIN DATA FRAME ERRFLAG (6b) ERRDEL (8b) IFS (= 3b) or OVL
EOF or ERRDEL or OVLDEL OVLFLAG (6b) OVLDEL (8b) IFS (= 3b) or OVL
ERROR
OVERLOAD
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DS70005340C-page 8 2018-2022 Microchip Technology Inc.and its subsidiaries
2.1.1 DLC ENCODING
The Data Length Code (DLC) specifies the number of data bytes a message frame contains.
Table 2-1 illustrates the encoding.
Table 2-1: DLC Encoding
Frame DLC Number of Data Bytes
CAN 2.0 and CAN FD 0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
CAN 2.0 9-15 8
CAN FD 9 12
10 16
11 20
12 24
13 32
14 48
15 64
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 9
CAN FD Protocol Module
3.0 CONTROL REGISTERS
CAN FD operations are controlled using the following Special Function Registers (SFRs). The
following registers are described later in this section:
• : CxCONLRegister 3-1
• : CxCONHRegister 3-2
• : CxNBTCFGLRegister 3-3
• : CxNBTCFGHRegister 3-4
• : CxDBTCFGLRegister 3-5
• : CxDBTCFGHRegister 3-6
• : CxTDCLRegister 3-7
• : CxTDCHRegister 3-8
• : CxTBCLRegister 3-9
• : CxTBCHRegister 3-10
•Register 3-11: CxTSCONL
• : CxTSCONHRegister 3-12
• : CxVECLRegister 3-13
• : CxVECHRegister 3-14
• : CxINTLRegister 3-15
• : CxINTHRegister 3-16
• : CxRXIFLRegister 3-17
• : CxRXIFHRegister 3-18
• : CxRXOVIFLRegister 3-19
• : CxRXOVIFHRegister 3-20
• : CxTXIFLRegister 3-21
• : CxTXIFHRegister 3-22
• : CxTXATIFLRegister 3-23
• : CxTXATIFHRegister 3-24
• : CxTXREQLRegister 3-25
• : CxTXREQHRegister 3-26
• : CxFIFOBALRegister 3-27
• : CxFIFOBAHRegister 3-28
• : CxTXQCONLRegister 3-29
• : CxTXQCONHRegister 3-30
• : CxTXQSTARegister 3-31
• : CxFIFOCONxLRegister 3-32
• : CxFIFOCONxHRegister 3-33
• : CxFIFOSTAxRegister 3-34
• : CxTEFCONLRegister 3-35
• : CxTEFCONHRegister 3-36
• : CxTEFSTARegister 3-37
• : CxFIFOUAxLRegister 3-38
• : CxFIFOUAxHRegister 3-39
• : CxTEFUALRegister 3-40
• : CxTEFUAHRegister 3-41
• : CxTXQUALRegister 3-42
• : CxTXQUAHRegister 3-43
• : CxTRECLRegister 3-44
• : CxTRECHRegister 3-45
• : CxBDIAG0LRegister 3-46
• : CxBDIAG0HRegister 3-47
• : CxBDIAG1LRegister 3-48
• : CxBDIAG1HRegister 3-49
• : CxFLTCONxLRegister 3-50
• : CxFLTCONxHRegister 3-51
• : CxFLTOBJxLRegister 3-52
• : CxFLTOBJxHRegister 3-53
• : CxMASKxLRegister 3-54
• : CxMASKxHRegister 3-55
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 11
CAN FD Protocol Module
bit 4-0 DeviceNet™ Filter Bit Number bitsDNCNT[4:0]:
10011-11111 = Invalid selection (compares up to 18 bits of data with EIDx)
10010 = Compares up to Data Byte 2, bit 6 with EID17
...
00001 = Compares up to Data Byte 0, bit 7 with EID0
00000 = Does not compare data bytes
Register 3-1: CxCONL: CAN Control Register Low (Continued)
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
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DS70005340C-page 12 2018-2022 Microchip Technology Inc.and its subsidiaries
Register 3-2: CxCONH: CAN Control Register High
R/W-0 R/W-0 R/W-0 R/W-0 S/HC-0 R/W-1 R/W-0 R/W-0
TXBWS3 TXBWS2 TXBWS1 TXBWS0 ABAT REQOP2 REQOP1 REQOP0
bit 15 bit 8
R-1 R-0 R-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
OPMOD2 OPMOD1 OPMOD0 TXQEN ( )1STEF ( )1SERRLOM ( )1ESIGM( )1RTXAT( )1
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Transmit Bandwidth Sharing bitsTXBWS[3:0]:
1111-1100 = 4096
1011 = 2048
1010 = 1024
1001 = 512
1000 = 256
0111 = 128
0110 = 64
0101 = 32
0100 = 16
0011 = 8
0010 = 4
0001 = 2
0000 = No delay
bit 11 ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 10-8 Request Operation Mode bitsREQOP[2:0]:
111 = Sets Restricted Operation mode
110 = Sets Normal CAN 2.0 mode; error frames on CAN FD frames
101 = Sets External Loopback mode
100 = Sets Configuration mode
011 = Sets Listen Only mode
010 = Sets Internal Loopback mode
001 = Sets Disable mode
000 = Sets Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
bit 7-5 Operation Mode Status bitsOPMOD[2:0]:
111 = Module is in Restricted Operation mode
110 = Module is in Normal CAN 2.0 mode; error frames on CAN FD frames
101 = Module is in External Loopback mode
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Internal Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
bit 4 TXQEN: Enable Transmit Queue bit ( )1
1 = Enables TXQ and reserves space in RAM
0 = Does not reserve space in RAM for TXQ
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 13
CAN FD Protocol Module
bit 3 Store in Transmit Event FIFO bitSTEF: ( )1
1 = Saves transmitted messages in TEF
0 = Does not save transmitted messages in TEF
bit 2 Transition to Listen Only Mode on System Error bitSERRLOM: ( )1
1 = Transitions to Listen Only mode
0 = Transitions to Restricted Operation mode
bit 1 Transmit ESI in Gateway Mode bitESIGM: ( )1
1 = ESI is transmitted as recessive when the ESI of message is high or CAN controller is error passive
0 = ESI reflects error status of the CAN controller
bit 0 RTXAT: Restrict Retransmission Attempts bit ( )1
1 = Restricted retransmission attempts, uses TXAT[1:0] (CxFIFOCONxH[6:5])
0 = Unlimited number of retransmission attempts, TXAT[1:0] bits will be ignored
Register 3-2: CxCONH: CAN Control Register High (Continued)
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
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DS70005340C-page 14 2018-2022 Microchip Technology Inc.and its subsidiaries
Register 3-3: CxNBTCFGL: CAN Nominal Bit Time Configuration Register Low ( )1
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
— TSEG2[6:0]
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1
— SJW[6:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Read as ‘ ’Unimplemented: 0
bit 14-8 Time Segment 2 bits (Phase Segment 2)TSEG2[6:0]:
111 1111 = Length is 128 x T Q
...
000 0000 = Length is 1 x T Q
bit 7 Read as ‘ ’Unimplemented: 0
bit 6-0 Synchronization Jump Width bitsSJW[6:0]:
111 1111 = Length is 128 x TQ
...
000 0000 = Length is 1 x T Q
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 15
CAN FD Protocol Module
Register 3-4: CxNBTCFGH: CAN Nominal Bit Time Configuration Register High( )1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BRP[7:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
TSEG1[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Baud Rate Prescaler bitsBRP[7:0]:
1111 1111 = T Q CAN = 256/F
...
0000 0000 = T Q CAN = 1/F
bit 7-0 Time Segment 1 bits (Propagation Segment + Phase Segment 1)TSEG1[7:0]:
1111 1111 = Length is 256 x T Q
...
0000 0000 = Length is 1 x T Q
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
Register 3-5: CxDBTCFGL: CAN Data Bit Time Configuration Register Low( )1
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — — TSEG2[3:0]
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — — SJW[3:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Read as ‘ ’Unimplemented: 0
bit 11-8 Time Segment 2 bits (Phase Segment 2)TSEG2[3:0]:
1111 = Length is 16 x T Q
...
0000 = Length is 1 x T Q
bit 7-4 Read as ‘ ’Unimplemented: 0
bit 3-0 Synchronization Jump Width bitsSJW[3:0]:
1111 = Length is 16 x T Q
...
0000 = Length is 1 x T Q
Note 1: This register can only be modified in Configuration mode (OPMOD[2:0] = ).100
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DS70005340C-page 16 2018-2022 Microchip Technology Inc.and its subsidiaries
Register 3-6: CxDBTCFGH: CAN Data Bit Time Configuration Register High ( )1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BRP[7:0]
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
— — — TSEG1[4:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Baud Rate Prescaler bitsBRP[7:0]:
1111 1111 = T Q CAN = 256/F
...
0000 0000 = T Q CAN = 1/F
bit 7-5 Read as ‘ ’Unimplemented: 0
bit 4-0 Time Segment 1 bits (Propagation Segment + Phase Segment 1)TSEG1[4:0]:
1 1111 = Length is 32 x T Q
...
0 0000 = Length is 1 x T Q
Note 1: This register can only be modified in Configuration mode (OPMOD[2:0] = ).100
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 17
CAN FD Protocol Module
Register 3-7: CxTDCL: CAN Transmitter Delay Compensation Register Low ( )1
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
— TDCO[6:0]
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TDCV[5:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Read as ‘ ’Unimplemented: 0
bit 14-8 Transmitter Delay Compensation Offset bits (Secondary Sample Point (SSP))TDCO[6:0]:
111 1111 = -64 x T CAN
...
011 1111 = 63 x T CAN
...
000 0000 = 0 x T CAN
bit 7-6 Read as ‘ ’Unimplemented: 0
bit 5-0 Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP))TDCV[5:0]:
11 1111 = 63 x TCAN
...
00 0000 = 0 x T CAN
Note 1: This register can only be modified in Configuration mode (OPMOD[2:0] = ).100
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Register 3-8: CxTDCH: CAN Transmitter Delay Compensation Register High ( )1
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — EDGFLTEN SID11EN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
— — — — — — TDCMOD1 TDCMOD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Read as ‘ ’Unimplemented: 0
bit 9 EDGFLTEN: Enable Edge Filtering During Bus Integration State bit
1 = Edge filtering is enabled according to ISO11898-1:2015
0 = Edge filtering is disabled
bit 8 SID11EN: Enable 12-Bit SID in CAN FD Base Format Messages bit
1 = RRS is used as SID11 in CAN FD base format messages: SID[11:0] = {SID[10:0], SID11}
0 = Does not use RRS; SID[10:0]
bit 7-2 Read as ‘ ’Unimplemented: 0
bit 1-0 Transmitter Delay Compensation mode bits (Secondary Sample Point (SSP))TDCMOD[1:0]:
10-11 = Auto: Measures delay and adds TDCO
01 = Manual: Does not measure, uses TDCV[5:0] + TDCO[6:0] from register
00 = Disables
Note 1: This register can only be modified in Configuration mode (OPMOD[2:0] = ).100
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Register 3-11: CxTSCONL: CAN Timestamp Control Register Low
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — TBCPRE[9:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TBCPRE[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Read as ‘ ’Unimplemented: 0
bit 9-0 CAN Time Base Counter Prescaler bitsTBCPRE[9:0]:
1023 = TBC increments every 1024 clocks
...
0 = TBC increments every 1 clock
Register 3-12: CxTSCONH: CAN Timestamp Control Register High
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TSRES TSEOF TBCEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Read as ‘ ’Unimplemented: 0
bit 2 TSRES: Timestamp Reset bit (CAN FD frames only)
1 = At sample point of the bit following the FDF bit
0 = At sample point of Start-of-Frame (SOF)
bit 1 TSEOF: Timesstamp End-of-Frame (EOF) bit
1 = Timestamp when frame is taken valid (11898-1 10.7):
- RX no error until last, but one bit of EOF
- TX no error until the end of EOF
0 = Timestamp at “beginning” of frame:
- Classical Frame: At sample point of SOF
- FD Frame: see TSRES bit
bit 0 TBCEN: Time Base Counter (TBC) Enable bit
1 = Enables TBC
0 = Stops and resets TBC
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CAN FD Protocol Module
Register 3-13: CxVECL: CAN Interrupt Code Register Low
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT[4:0]
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— ICODE[6:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Read as ‘ ’Unimplemented: 0
bit 12-8 Filter Hit Number bitsFILHIT[4:0]:
11111 = Filter 31
11110 = Filter 30
...
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘ ’0
bit 6-0 Interrupt Flag Code bitsICODE[6:0]:
1001011-1111111 = Reserved
1001010 = Transmit attempt interrupt (any bit in CxTXATIF is set)
1001001 = Transmit event FIFO interrupt (any bit in CxTEFSTA is set)
1001000 = Invalid message occurred (IVMIF/IE)
1000111 = CAN module mode change occurred (MODIF/IE)
1000110 = CAN timer overflow (TBCIF/IE)
1000101 = RX/TX MAB overflow/underflow (RX: Message received before previous message was
saved to memory; TX: Can’t feed TX MAB fast enough to transmit consistent data)
(SERRIF/IE)
1000100 = Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
1000011 = Receive FIFO overflow interrupt (any bit in CxRXOVIF is set)
1000010 = Wake-up interrupt (WAKIF/WAKIE)
1000001 = Error interrupt (CERRIF/IE)
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (TFIF31 or RFIF31 is set)
...
0000001 = FIFO 1 Interrupt (TFIF1 or RFIF1 is set)
0000000 = FIFO 0 Interrupt (TFIF0 is set)
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DS70005340C-page 22 2018-2022 Microchip Technology Inc.and its subsidiaries
Register 3-14: CxVECH: CAN Interrupt Code Register High
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— RXCODE[6:0]
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
— TXCODE[6:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Read as ‘ ’Unimplemented: 0
bit 14-8 Receive Interrupt Flag Code bitsRXCODE[6:0]:
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (RFIF[31] is set)
...
0000010 = FIFO 2 interrupt (RFIF[2] is set)
0000001 = FIFO 1 interrupt (RFIF[1] is set)
0000000 = Reserved; FIFO 0 cannot receive
bit 7 Unimplemented: Read as ‘ ’0
bit 6-0 Transmit Interrupt Flag Code bitsTXCODE[6:0]:
1000001-1111111 = Reserved
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO 31 interrupt (TFIF[31] is set)
...
0000001 = FIFO 1 interrupt (TFIF[1] is set)
0000000 = FIFO 0 interrupt (TFIF[0] is set)
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Register 3-16: CxINTH: CAN Interrupt Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
IVMIE WAKIE CERRIE SERRIE RXOVIE TXATIE — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TEFIE MODIE TBCIE RXIE TXIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Invalid Message Interrupt Enable bitIVMIE:
1 = Invalid message interrupt is enabled
0 = Invalid message interrupt is disabled
bit 14 WAKIE: Bus Wake-up Activity Interrupt Enable bit
1 = Wake-up activity interrupt is enabled
0 = Wake-up activity interrupt is disabled
bit 13 CAN Bus Error Interrupt Enable bitCERRIE:
1 = CAN bus error interrupt is enabled
0 = CAN bus error interrupt is disabled
bit 12 System Error Interrupt Enable bitSERRIE:
1 = System error interrupt is enabled
0 = System error interrupt is disabled
bit 11 Receive Buffer Overflow Interrupt Enable bitRXOVIE:
1 = Receive buffer overflow interrupt is enabled
0 = Receive buffer overflow interrupt is disabled
bit 10 TXATIE: Transmit Attempt Interrupt Enable bit
1 = Transmit attempt interrupt is enabled
0 = Transmit attempt interrupt is disabled
bit 9-5 Read as ‘ ’Unimplemented: 0
bit 4 Transmit Event FIFO Interrupt Enable bitTEFIE:
1 = Transmit event FIFO interrupt is enabled
0 = Transmit event FIFO interrupt is disabled
bit 3 Mode Change Interrupt Enable bitMODIE:
1 = Mode change interrupt is enabled
0 = Mode change interrupt is disabled
bit 2 TBCIE: CAN Timer Interrupt Enable bit
1 = CAN timer interrupt is enabled
0 = CAN timer interrupt is disabled
bit 1 Receive Object Interrupt Enable bitRXIE:
1 = Receive object interrupt is enabled
0 = Receive object interrupt is disabled
bit 0 Transmit Object Interrupt Enable bitTXIE:
1 = Transmit object interrupt is enabled
0 = Transmit object interrupt is disabled
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 25
CAN FD Protocol Module
Register 3-17: CxRXIFL: CAN Receive Interrupt Status Register Low ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFIF[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0
RFIF[7:1] —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 Receive FIFO Interrupt Pending bitsRFIF[15:1]:
1 = One or more enabled receive FIFO interrupts are pending
0 = No enabled receive FIFO interrupts are pending
bit 0 Unimplemented: Read as ‘ ’0
Note 1: CxRXIFL: FIFO: RFIFx = ‘or’ of enabled RX FIFO flags (flags need to be cleared in the FIFO register).
Register 3-18: CxRXIFH: CAN Receive Interrupt Status Register High ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFIF[31:24]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFIF[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Receive FIFO Interrupt Pending bitsRFIF[31:16]:
1 = One or more enabled receive FIFO interrupts are pending
0 = No enabled receive FIFO interrupts are pending
Note 1: CxRXIFH: FIFO: RFIFx = ‘or’ of enabled RX FIFO flags (flags need to be cleared in the FIFO register).
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Register 3-19: CxRXOVIFL: CAN Receive Overflow Interrupt Status Register Low ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFOVIF[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0
RFOVIF[7:1] —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 Receive FIFO Overflow Interrupt Pending bitsRFOVIF[15:1]:
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 Unimplemented: Read as ‘ ’0
Note 1: CxRXOVIFL: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register).
Register 3-20: CxRXOVIFH: CAN Receive Overflow Interrupt Status Register High ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFOVIF[31:24]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
RFOVIF[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Receive FIFO Overflow Interrupt Pending bitsRFOVIF[31:16]:
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: CxRXOVIFH: FIFO: RFOVIFx (flag needs to be cleared in the FIFO register).
 2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 27
CAN FD Protocol Module
Register 3-21: CxTXIFL: CAN Transmit Interrupt Status Register Low ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFIF[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFIF[7:0]( )2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Transmit FIFO/TXQ Interrupt Pending bitsTFIF[15:0]: ( )2
1 = One or more enabled transmit FIFO/TXQ interrupts are pending
0 = No enabled transmit FIFO/TXQ interrupts are pending
Note 1: CxTXIFL: FIFO: TFIFx = ‘or’ of the enabled TX FIFO flags (flags need to be cleared in the FIFO register).
2: TFIF0 is for the TXQ.
Register 3-22: CxTXIFH: CAN Transmit Interrupt Status Register High ( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFIF[31:24]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFIF[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Transmit FIFO/TXQ Interrupt Pending bitsTFIF[31:16]:
1 = One or more enabled transmit FIFO/TXQ interrupts are pending
0 = No enabled transmit FIFO/TXQ interrupts are pending
Note 1: CxTXIFH: FIFO: TFIFx = ‘or’ of the enabled TX FIFO flags (flags need to be cleared in the FIFO register).
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Register 3-23: CxTXATIFL: CAN Transmit Attempt Interrupt Status Register Low( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF[15:8]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF[7:0]( )2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TFATIF[15:0]: Transmit FIFO/TXQ Attempt Interrupt Pending bits
( )2
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: CxTXATIFL: FIFO: TFATIFx (flag needs to be cleared in the FIFO register).
2: TFATIF0 is for the TXQ.
Register 3-24: CxTXATIFH: CAN Transmit Attempt Interrupt Status Register High( )1
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF[31:24]
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TFATIF[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TFATIF[31:16]: Transmit FIFO/TXQ Attempt Interrupt Pending bits
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: CxTXATIFH: FIFO: TFATIFx (flag needs to be cleared in the FIFO register).
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 29
CAN FD Protocol Module
Register 3-25: CxTXREQL: CAN Transmit Request Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXREQ[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXREQ[7:1] TXREQ0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 Message Send Request bitsTXREQ[15:0]:
TXEN = 1 (object configured as a transmit object):
Setting this bit to ‘ ’ requests sending a message. The bit will automatically clear when the message(s)1
queued in the object is (are) successfully sent. This bit can NOT be used for aborting a transmission.
TXEN = 0 (object configured as a receive object):
This bit has no effect.
bit 0 Transmit Queue Message Send Request bitTXREQ0:
Setting this bit to ‘ ’ requests sending a message. The bit will automatically clear when the message(s)1
queued in the object is (are) successfully sent. This bit can NOT be used for aborting a transmission.
Register 3-26: CxTXREQH: CAN Transmit Request Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXREQ[31:24]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXREQ[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Message Send Request bitsTXREQ[31:16]:
TXEN = 1 (object configured as a transmit object):
Setting this bit to ‘ ’ requests sending a message. The bit will automatically clear when the message(s)1
queued in the object is (are) successfully sent. This bit can NOT be used for aborting a transmission.
TXEN = 0 (object configured as a receive object):
This bit has no effect.
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Register 3-27: CxFIFOBAL: CAN Message Memory Base Address Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIFOBA[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0( )1U-0( )1
FIFOBA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Message Memory Base Address bitsFIFOBA[15:0]:
Defines the base address for the transmit event FIFO followed by the message objects.
Note 1: Bits[1:0] are forced to '0' to be 32-bit word aligned.
Register 3-28: CxFIFOBAH: CAN Message Memory Base Address Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIFOBA[31:24]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FIFOBA[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Message Memory Base Address bitsFIFOBA[31:16]:
Defines the base address for the transmit event FIFO followed by the message objects.
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 31
CAN FD Protocol Module
Register 3-29: CxTXQCONL: CAN Transmit Queue Control Register Low
U-0 U-0 U-0 U-0 U-0 S/HC-1 R/W/HC-0 S/HC-0
— — — — — FRESET TXREQ UINC
bit 15 bit 8
R-1 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0
TXEN( )1— — TXATIE — TXQEIE — TXQNIE
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Read as ‘ ’Unimplemented: 0
bit 10 FRESET: FIFO Reset bit
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; user should poll
whether this bit is clear before taking any action
0 = No effect
bit 9 TXREQ: Message Send Request bit
1 = Requests sending a message; the bit will automatically clear when all the messages queued in
the TXQ are successfully sent
0 0 = Clearing the bit to ‘ ’ while set (‘ ’) will request a message abort1
bit 8 Increment Head/Tail bitUINC:
When this bit is set, the FIFO head will increment by a single message.
bit 7 TXEN: TX Enable bit( )1
1 = Transmit Message Queue. This bit always reads as ‘ ’.1
bit 6-5 Read as ‘ ’Unimplemented: 0
bit 4 TXATIE: Transmit Attempts Exhausted Interrupt Enable bit
1 = Enables interrupt
0 = Disables interrupt
bit 3 Unimplemented: Read as ‘ ’0
bit 2 TXQEIE: Transmit Queue Empty Interrupt Enable bit
1 = Interrupt is enabled for TXQ empty
0 = Interrupt is disabled for TXQ empty
bit 1 Unimplemented: Read as ‘ ’0
bit 0 TXQNIE: Transmit Queue Not Full Interrupt Enable bit
1 = Interrupt is enabled for TXQ not full
0 = Interrupt is disabled for TXQ not full
Note 1: Please refer to the specific device data sheet for the Reset value of the TXEN bit.
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DS70005340C-page 32 2018-2022 Microchip Technology Inc.and its subsidiaries
Register 3-30: CxTXQCONH: CAN Transmit Queue Control Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLSIZE2( )1PLSIZE1( )1PLSIZE0( )1FSIZE4( )1FSIZE3( )1FSIZE2( )1FSIZE1( )1FSIZE0( )1
bit 15 bit 8
U-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TXAT1 TXAT0 TXPRI4 TXPRI3 TXPRI2 TXPRI1 TXPRI0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Payload Size bitsPLSIZE[2:0]: ( )1
111 = 64 data bytes
110 = 48 data bytes
101 = 32 data bytes
100 = 24 data bytes
011 = 20 data bytes
010 = 16 data bytes
001 = 12 data bytes
000 = 8 data bytes
bit 12-8 FIFO Size bitsFSIZE[4:0]: ( )1
11111 = FIFO is 32 messages deep
...
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 7 Read as ‘ ’Unimplemented: 0
bit 6-5 TXAT[1:0]: Retransmission Attempts bits
This feature is enabled when RTXAT (CxCONH[0]) is set.
11 = Unlimited number of retransmission attempts
10 = Unlimited number of retransmission attempts
01 = Three retransmission attempts
00 = Disable retransmission attempts
bit 4-0 Message Transmit Priority bitsTXPRI[4:0]:
11111 = Highest message priority
...
00000 = Lowest message priority
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 33
CAN FD Protocol Module
Register 3-31: CxTXQSTA: CAN Transmit Queue Status Register
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — TXQCI4( )1TXQCI3( )1TXQCI2( )1TXQCI1( )1TXQCI0( )1
bit 15 bit 8
R-0 R-0 R-0 HS/C-0 U-0 R-1 U-0 R-1
TXABT( )2TXLARB( )2TXERR( )2TXATIF — TXQEIF — TXQNIF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Read as ‘ ’Unimplemented: 0
bit 12-8 Transmit Queue Message Index bitsTXQCI[4:0]: ( )1
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
bit 7 TXABT: Message Aborted Status bit( )2
1 = Message was aborted
0 = Message completed successfully
bit 6 Message Lost Arbitration Status bitTXLARB: ( )2
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 5 Error Detected During Transmission bitTXERR: ( )2
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3 Read as ‘ ’Unimplemented: 0
bit 2 Transmit Queue Empty Interrupt Flag bitTXQEIF:
1 = TXQ is empty
0 = TXQ is not empty, at least 1 message is queued to be transmitted
bit 1 Read as ‘ ’Unimplemented: 0
bit 0 Transmit Queue Not Full Interrupt Flag bitTXQNIF:
1 = TXQ is not full
0 = TXQ is full
Note 1: The TXQCI[4:0] bits give a zero-indexed value to the message in the TXQ. If the TXQ is four messages
deep (FSIZE = ), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ.3
2: These bits are updated when a message completes (or aborts) or when the TXQ is reset.
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Register 3-32: CxFIFOCONxL: CAN FIFO Control Register x (x = 1 to 31) Low
U-0 U-0 U-0 U-0 U-0 S/HC-1 R/W/HC-0 S/HC-0
— — — — — FRESET TXREQ UINC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXEN RTREN RXTSEN( )1TXATIE RXOVIE TFERFFIE TFHRFHIE TFNRFNIE
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Read as ‘ ’Unimplemented: 0
bit 10 FRESET: FIFO Reset bit
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; user should poll
whether this bit is clear before taking any action
0 = No effect
bit 9 TXREQ: Message Send Request bit
TXEN = 1 (FIFO configured as a transmit FIFO):
1 = Requests sending a message; the bit will automatically clear when all the messages queued in
the FIFO are successfully sent
0 0 = Clearing the bit to ‘ ’ while set (‘ ’) will request a message abort1
TXEN = 0 (FIFO configured as a receive FIFO):
This bit has no effect.
bit 8 Increment Head/Tail bitUINC:
TXEN = (FIFO configured as a transmit FIFO):1
When this bit is set, the FIFO head will increment by a single message.
TXEN = 0 (FIFO configured as a receive FIFO):
When this bit is set, the FIFO tail will increment by a single message.
bit 7 TXEN: TX/RX Buffer Selection bit
1 = Transmits message object
0 = Receives message object
bit 6 RTREN: Auto-Remote Transmit (RTR) Enable bit
1 = When a Remote Transmit is received, TXREQ will be set
0 = When a Remote Transmit is received, TXREQ will be unaffected
bit 5 RXTSEN: Received Message Timestamp Enable bit
( )1
1 = Captures timestamp in received message object in RAM
0 = Does not capture time stamp
bit 4 TXATIE: Transmit Attempts Exhausted Interrupt Enable bit
1 = Enables interrupt
0 = Disables interrupt
bit 3 RXOVIE: Overflow Interrupt Enable bit
1 = Interrupt is enabled for overflow event
0 = Interrupt is disabled for overflow event
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 35
CAN FD Protocol Module
bit 2 Transmit/Receive FIFO Empty/Full Interrupt Enable bitTFERFFIE:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Empty Interrupt Enable
1 = Interrupt is enabled for FIFO empty
0 = Interrupt is disabled for FIFO empty
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Full Interrupt Enable
1 = Interrupt is enabled for FIFO full
0 = Interrupt is disabled for FIFO full
bit 1 Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bitTFHRFHIE:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Half Empty Interrupt Enable
1 = Interrupt is enabled for FIFO half empty
0 = Interrupt is disabled for FIFO half empty
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Half Full Interrupt Enable
1 = Interrupt is enabled for FIFO half full
0 = Interrupt is disabled for FIFO half full
bit 0 Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bitTFNRFNIE:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Not Full Interrupt Enable
1 = Interrupt is enabled for FIFO not full
0 = Interrupt is disabled for FIFO not full
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Not Empty Interrupt Enable
1 = Interrupt is enabled for FIFO not empty
0 = Interrupt is disabled for FIFO not empty
Register 3-32: CxFIFOCONxL: CAN FIFO Control Register x (x = 1 to 31) Low (Continued)
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
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Register 3-33: CxFIFOCONxH: CAN FIFO Control Register x (x = 1 to 31) High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLSIZE2( )1PLSIZE1( )1PLSIZE0( )1FSIZE4( )1FSIZE3( )1FSIZE2( )1FSIZE1( )1FSIZE0( )1
bit 15 bit 8
U-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TXAT1 TXAT0 TXPRI4 TXPRI3 TXPRI2 TXPRI1 TXPRI0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Payload Size bitsPLSIZE[2:0]: ( )1
111 = 64 data bytes
110 = 48 data bytes
101 = 32 data bytes
100 = 24 data bytes
011 = 20 data bytes
010 = 16 data bytes
001 = 12 data bytes
000 = 8 data bytes
bit 12-8 FIFO Size bitsFSIZE[4:0]: ( )1
11111 = FIFO is 32 messages deep
...
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 7 Read as ‘ ’Unimplemented: 0
bit 6-5 TXAT[1:0]: Retransmission Attempts bits
This feature is enabled when RTXAT (CxCONH[0]) is set.
11 = Unlimited number of retransmission attempts
10 = Unlimited number of retransmission attempts
01 = Three retransmission attempts
00 = Disables retransmission attempts
bit 4-0 Message Transmit Priority bitsTXPRI[4:0]:
11111 = Highest message priority
...
00000 = Lowest message priority
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 37
CAN FD Protocol Module
Register 3-34: CxFIFOSTAx: CAN FIFO Status Register x (x = 1 to 31)
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FIFOCI4( )1FIFOCI3( )1FIFOCI2( )1FIFOCI1( )1FIFOCI0( )1
bit 15 bit 8
R-0 R-0 R-0 HS/C-0 HS/C-0 R-0 R-0 R-0
TXABT( )3TXLARB( )2TXERR( )2TXATIF RXOVIF TFERFFIF TFHRFHIF TFNRFNIF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Read as ‘ ’Unimplemented: 0
bit 12-8 FIFO Message Index bitsFIFOCI[4:0]: ( )1
TXEN = (FIFO configured as a transmit buffer):1
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return an index to the message that the FIFO will use to save the next
message.
bit 7 TXABT: Message Aborted Status bit( )3
1 = Message was aborted
0 = Message completed successfully
bit 6 TXLARB: Message Lost Arbitration Status bit( )2
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 5 TXERR: Error Detected During Transmission bit( )2
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 4 TXATIF: Transmit Attempts Exhausted Interrupt Pending bit
TXEN = 1 (FIFO configured as a transmit buffer):
1 = Interrupt is pending
0 = Interrupt is not pending
TXEN = 0 (FIFO configured as a receive buffer):
Unused, reads as ‘ ’.0
bit 3 RXOVIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = (FIFO configured as a transmit buffer):1
Unused, reads as ‘ ’.0
TXEN = 0 (FIFO configured as a receive buffer):
1 = Overflow event has occurred
0 = No overflow event occurred
Note 1: FIFOCI[4:0] gives a zero-indexed value to the message in the FIFO. If the FIFO is four messages deep
(FSIZE = ), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO. 3
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the TXQ is reset.
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bit 2 Transmit/Receive FIFO Empty/Full Interrupt Flag bitTFERFFIF:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Empty Interrupt Flag
1 = FIFO is empty
0 = FIFO is not empty, at least one message is queued to be transmitted
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Full Interrupt Flag
1 = FIFO is full
0 = FIFO is not full
bit 1 Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag bitTFHRFHIF:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Half Empty Interrupt Flag
1 = FIFO is half full
0 = FIFO is > half full
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Half Full Interrupt Flag
1 = FIFO is half full
0 = FIFO is < half full
bit 0 Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag bitTFNRFNIF:
TXEN = 1 (FIFO configured as a transmit FIFO):
Transmit FIFO Not Full Interrupt Flag
1 = FIFO is not full
0 = FIFO is full
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Not Empty Interrupt Flag
1 = FIFO is not empty, has at least one message
0 = FIFO is empty
Register 3-34: CxFIFOSTAx: CAN FIFO Status Register x (x = 1 to 31) (Continued)
Note 1: FIFOCI[4:0] gives a zero-indexed value to the message in the FIFO. If the FIFO is four messages deep
(FSIZE = ), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO. 3
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the TXQ is reset.
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 39
CAN FD Protocol Module
Register 3-35: CxTEFCONL: CAN Transmit Event FIFO Control Register Low
U-0 U-0 U-0 U-0 U-0 S/HC-1 U-0 S/HC-0
— — — — — FRESET — UINC
bit 15 bit 8
U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TEFTSEN( )1— TEFOVIE TEFFIE TEFHIE TEFNEIE
bit 7 bit 0
Legend: S = Settable bit HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Read as ‘ ’Unimplemented: 0
bit 10 FRESET: FIFO Reset bit
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; the user should poll
whether this bit is clear before taking any action
0 = No effect
bit 9 Unimplemented: Read as ‘ ’0
bit 8 Increment Tail bitUINC:
1 = When this bit is set, the FIFO tail will increment by a single message
0 = FIFO tail will not increment
bit 7-6 Read as ‘ ’Unimplemented: 0
bit 5 TEFTSEN: Transmit Event FIFO Timestamp Enable bit( )1
1 = Timestamps elements in TEF
0 = Does not timestamp elements in TEF
bit 4 Unimplemented: Read as ‘ ’0
bit 3 TEFOVIE: Transmit Event FIFO Overflow Interrupt Enable bit
1 = Interrupt is enabled for overflow event
0 = Interrupt is disabled for overflow event
bit 2 TEFFIE: Transmit Event FIFO Full Interrupt Enable bit
1 = Interrupt is enabled for FIFO full
0 = Interrupt is disabled for FIFO full
bit 1 TEFHIE: Transmit Event FIFO Half Full Interrupt Enable bit
1 = Interrupt is enabled for FIFO half full
0 = Interrupt is disabled for FIFO half full
bit 0 TEFNEIE: Transmit Event FIFO Not Empty Interrupt Enable bit
1 = Interrupt is enabled for FIFO not empty
0 = Interrupt is disabled for FIFO not empty
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
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Register 3-36: CxTEFCONH: CAN Transmit Event FIFO Control Register High
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FSIZE[4:0]( )1
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Read as ‘ ’Unimplemented: 0
bit 12-8 FIFO Size bitsFSIZE[4:0]: ( )1
11111 = FIFO is 32 messages deep
...
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 7-0 Read as ‘ ’Unimplemented: 0
Note 1: These bits can only be modified in Configuration mode (OPMOD[2:0] = ).100
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 41
CAN FD Protocol Module
Register 3-37: CxTEFSTA: CAN Transmit Event FIFO Status Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 HS/C R-0 R-0 R-0
— — — — TEFOVIF TEFFIF( )1TEFHIF( )1TEFNEIF( )1
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Read as ‘ ’Unimplemented: 0
bit 3 TEFOVIF: Transmit Event FIFO Overflow Interrupt Flag bit
1 = Overflow event has occurred
0 = No overflow event has occurred
bit 2 TEFFIF: Transmit Event FIFO Full Interrupt Flag bit( )1
1 = FIFO is full
0 = FIFO is not full
bit 1 TEFHIF: Transmit Event FIFO Half Full Interrupt Flag bit( )1
1 = FIFO is half full
0 = FIFO is < half full
bit 0 TEFNEIF: Transmit Event FIFO Not Empty Interrupt Flag bit( )1
1 = FIFO is not empty
0 = FIFO is empty
Note 1: These bits are read-only and reflect the status of the FIFO.
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Register 3-38: CxFIFOUAxL: CAN FIFO User Address Register x (x = 1 to 31) Low
( )1
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA[15:8]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FIFO User Address bitsFIFOUA[15:0]:
TXEN = 1 (FIFO configured as a transmit buffer):
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
Register 3-39: CxFIFOUAxH: CAN FIFO User Address Register x (x = 1 to 31) High( )1
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA[31:24]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
FIFOUA[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 FIFO User Address bitsFIFOUA[31:16]:
TXEN = 1 (FIFO configured as a transmit buffer):
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0 (FIFO configured as a receive buffer):
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
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CAN FD Protocol Module
Register 3-40: CxTEFUAL: CAN Transmit Event FIFO User Address Register Low( )1
R-x R-x R-x R-x R-x R-x R-x R-x
TEFUA[15:8]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TEFUA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Transmit Event FIFO User Address bitsTEFUA[15:0]:
A read of this register will return the address where the next event is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
Register 3-41: CxTEFUAH: CAN Transmit Event FIFO User Address Register High
( )1
R-x R-x R-x R-x R-x R-x R-x R-x
TEFUA[31:24]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TEFUA[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Transmit Event FIFO User Address bitsTEFUA[31:16]:
A read of this register will return the address where the next event is to be read (FIFO tail).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
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Register 3-42: CxTXQUAL: CAN Transmit Queue User Address Register Low( )1
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA[15:8]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Transmit Queue User Address bitsTXQUA[15:0]:
A read of this register will return the address where the next message is to be written (TXQ head).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
Register 3-43: CxTXQUAH: CAN Transmit Queue User Address Register High
( )1
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA[31:24]
bit 15 bit 8
R-x R-x R-x R-x R-x R-x R-x R-x
TXQUA[23:16]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 TXQ User Address bitsTXQUA[31:16]:
A read of this register will return the address where the next message is to be written (TXQ head).
Note 1: This register is not ensured to read correctly in Configuration mode and should only be accessed when the
module is not in Configuration mode.
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Register 3-46: CxBDIAG0L: CAN Bus Diagnostics Register 0 Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NTERRCNT[7:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NRERRCNT[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Nominal Bit Rate Transmit Error Counter bitsNTERRCNT[7:0]:
bit 7-0 Nominal Bit Rate Receive Error Counter bitsNRERRCNT[7:0]:
Register 3-47: CxBDIAG0H: CAN Bus Diagnostics Register 0 High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DTERRCNT[7:0]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DRERRCNT[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Data Bit Rate Transmit Error Counter bitsDTERRCNT[7:0]:
bit 7-0 Data Bit Rate Receive Error Counter bitsDRERRCNT[7:0]:
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CAN FD Protocol Module
Register 3-48: CxBDIAG1L: CAN Bus Diagnostics Register 1 Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EFMSGCNT[15:8]
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EFMSGCNT[7:0]
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 Error-Free Message Counter bitsEFMSGCNT[15:0]:
Register 3-49: CxBDIAG1H: CAN Bus Diagnostics Register 1 High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
DLCMM ESI DCRCERR DSTUFERR DFORMERR — DBIT1ERR DBIT0ERR
bit 15 bit 8
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXBOERR — NCRCERR NSTUFERR NFORMERR NACKERR NBIT1ERR NBIT0ERR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DLC Mismatch bitDLCMM:
During a transmission or reception, the specified DLC is larger than the PLSIZEx of the FIFO element.
bit 14 ESI Flag of Received CAN FD Message Set bitESI:
bit 13 Same as for Nominal Bit RateDCRCERR:
bit 12 Same as for Nominal Bit RateDSTUFERR:
bit 11 Same as for Nominal Bit RateDFORMERR:
bit 10 Read as ‘ ’Unimplemented: 0
bit 9 Same as for Nominal Bit RateDBIT1ERR:
bit 8 Same as for Nominal Bit RateDBIT0ERR:
bit 7 Device Went to Bus Off bit (and auto-recovered)TXBOERR:
bit 6 Read as ‘ ’Unimplemented: 0
bit 5 Received Message with CRC Incorrect Checksum bitNCRCERR:
The CRC checksum of a received message was incorrect. The CRC of an incoming message does not
match with the CRC calculated from the received data.
bit 4 Received Message with Illegal Sequence bitNSTUFERR:
More than five equal bits in a sequence have occurred in a part of a received message where this is not
allowed.
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bit 3 Received Frame Fixed Format bitNFORMERR:
A fixed format part of a received frame has the wrong format.
bit 2 Transmitted Message Not Acknowledged bitNACKERR:
Transmitted message was not Acknowledged.
bit 1 Transmitted Message Recessive Level bitNBIT1ERR:
During the transmission of a message (with the exception of the arbitration field), the device wanted to
send a recessive level (bit of logical value ‘ ’), but the monitored bus value was dominant.1
bit 0 Transmitted Message Dominant Level bitNBIT0ERR:
During the transmission of a message (or Acknowledge bit, or active error flag or overload flag), the
device wanted to send a dominant level (data or identifier bit of logical value ‘ ’), but the monitored bus0
value was recessive. During bus off recovery, this status is set each time a sequence of 11 recessive
bits has been monitored. This enables the CPU to monitor the proceeding bus off recovery sequence
(indicating the bus is not stuck at dominant or continuously disturbed).
Register 3-49: CxBDIAG1H: CAN Bus Diagnostics Register 1 High (Continued)
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Register 3-51: CxFLTCONxH: CAN Filter Control Register x High (x = 0 to 7; c = 2, 6, 10, 14, 18, 22, 26, 30;
d = 3, 7, 11, 15, 19, 23, 27, 31)
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTENd — — FdBP4 FdBP3 FdBP2 FdBP1 FdBP0
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTENc — — FcBP4 FcBP3 FcBP2 FcBP1 FcBP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTENd: Enable Filter d to Accept Messages bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 Read as ‘ ’Unimplemented: 0
bit 12-8 Pointer to FIFO When Filter d Hits bitsFdBP[4:0]:
11111 = Message matching filter is stored in FIFO 31
11110 = Message matching filter is stored in FIFO 30
...
00010 = Message matching filter is stored in FIFO 2
00001 = Message matching filter is stored in FIFO 1
00000 = Reserved; FIFO 0 is the TX Queue and cannot receive messages
bit 7 FLTENc: Enable Filter c to Accept Messages bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 Read as ‘ ’Unimplemented: 0
bit 4-0 Pointer to FIFO When Filter c Hits bitsFcBP[4:0]:
11111 = Message matching filter is stored in FIFO 31
11110 = Message matching filter is stored in FIFO 30
...
00010 = Message matching filter is stored in FIFO 2
00001 = Message matching filter is stored in FIFO 1
00000 = Reserved; FIFO 0 is the TX Queue and cannot receive messages
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CAN FD Protocol Module
Register 3-52: CxFLTOBJxL: CAN Filter Object Register x Low (x = 0 to 31)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Extended Identifier Filter bits EID[4:0]:
In DeviceNet™ mode, these are the filter bits for the first two data bytes.
bit 10-0 Standard Identifier Filter bitsSID[10:0]:
Register 3-53: CxFLTOBJxH: CAN Filter Object Register x High (x = 0 to 31)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— EXIDE SID11 EID17 EID16 EID15 EID14 EID13
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Read as ‘ ’Unimplemented: 0
bit 14 Extended Identifier Enable bitEXIDE:
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
bit 13 SID11: Standard Identifier Filter bit
bit 12-0 Extended Identifier Filter bits EID[17:5]:
In DeviceNet™ mode, these are the filter bits for the first two data bytes.
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Register 3-54: CxMASKxL: CAN Mask Register x Low (x = 0 to 31)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MEID4 MEID3 MEID2 MEID1 MEID0 MSID10 MSID9 MSID8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MSID7 MSID6 MSID5 MSID4 MSID3 MSID2 MSID1 MSID0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Extended Identifier Mask bits MEID[4:0]:
In DeviceNet™ mode, these are the mask bits for the first two data bytes.
bit 10-0 Standard Identifier Mask bitsMSID[10:0]:
Register 3-55: CxMASKxH: CAN Mask Register x High (x = 0 to 31)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— MIDE MSID11 MEID17 MEID16 MEID15 MEID14 MEID13
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MEID12 MEID11 MEID10 MEID9 MEID8 MEID7 MEID6 MEID5
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Read as ‘ ’Unimplemented: 0
bit 14 Identifier Receive Mode bitMIDE:
1 = Matches only message types (standard or extended address) that correspond to the EXIDE bit in
the filter
0 = Matches either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 13 MSID11: Standard Identifier Mask bit
bit 12-0 Extended Identifier Mask bits MEID[17:5]:
In DeviceNet™ mode, these are the mask bits for the first two data bytes.
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CAN FD Protocol Module
4.0 MODES OF OPERATION
The CAN FD Protocol Module has eight modes of operations:
• Configuration mode
• Normal CAN FD mode: Supports mixing of CAN FD and CAN 2.0 messages
• Normal CAN 2.0 mode: Will generate error frames while receiving CAN FD messages. The
FDF bit is forced to zero and only CAN 2.0 frames are sent, even if the FDF bit is set in the
transmit message object.
• Disable mode
• Listen Only mode
• Restricted Operation mode
• Internal Loopback mode
• External Loopback mode
The modes of operations can be grouped into four main groups: Configuration, Normal, Sleep
and Debug (see ).Figure 4-1
4.1 Mode Change
Figure 4-1 illustrates the possible mode transitions. New modes of operation are requested by
writing to the REQOP[2:0] (CxCONH[10:8]) bits. The modes of operations do not change
immediately. The modes will only change when the bus is Idle.
The current operating mode is indicated in the OPMOD[2:0] (CxCONH[7:5]) bits. The
application can enable an interrupt on an OPMODx change or poll the OPMODx bits.
4.1.1 CHANGING BETWEEN NORMAL MODES
Directly changing between Normal modes is not allowed. The Configuration mode must be
selected before a new Normal mode can be selected.
4.1.2 CHANGING BETWEEN DEBUG MODES
Directly changing between Debug modes is not allowed. The Configuration mode must be
selected before a new Debug mode can be selected.
4.1.3 EXITING NORMAL MODE
The device will transition to Configuration or Sleep mode only after the current message is
transmitted.
4.1.4 ENTERING AND EXITING DISABLE MODE
The CAN FD Protocol Module enters Disable mode after a Disable mode request. The device
exits Disable mode after a mode request.
If WAKIE is set, a dominant edge on CxRX will generate an interrupt. The CPU has to enable
the CAN module by requesting a Normal mode.
4.1.5 BUS INTEGRATING MODE
The CAN FD Protocol Module integrates to the bus, according to the ISO11898-1:2015
specifications (eleven consecutive recessive bits), under the following conditions:
• Change from Configuration mode to one of the Normal modes or Debug modes
• Change from Disable mode to one of the Normal modes
dsPIC33/PIC24 Family Reference Manual
DS70005340C-page 54 2018-2022 Microchip Technology Inc.and its subsidiaries
Figure 4-1: CAN FD Modes of Operation
REQOPx = Restricted
and Bus Idle
No
Yes
REQOPx =
“Normal”
REQOP=Listen Only
And Bus Idle
REQOPx = Config
(and Bus Idle)
REQOP=Restricted
And Bus Idle
Recessive bit = 1
Received and PXEDIS = 0
Wait for
Bus Idle
Wait for
128 Idle Conditions
TXBO
System Error
REQOPx = “Normal”
REQOPx = Config
(and Bus Idle) REQOPx = Listen Only
and Bus Idle
REQOPx = Config
and Bus Idle
REQOPx = Loopback Int/Ext
and Bus Idle (Integrating)
WAKIF or OSCDIS = 0
REQOPx = Sleep
and Bus Idle
REQOPx = Config
and Bus Idle
REQOPx = “Normal”
and Bus Idle
(Integrating)
POR
Configuration
Mode
Sleep Mode
Clock Off
CxTX Recessive
“Normal”
Modes
RX and TX
Loopback
Modes
Listen Only
Mode
RX Only
TX Pin High
TXREQ Ignored
Bus Off
Clear All TXREQx
bits (Reset TX
FIFOs/TXQ)
Protocol
Exception Event
No TX
Restricted Operation
Mode
RX
TX: Only ACK,
TXREQx Ignored
c
SERRLOM = 1?
Normal FD
Mode
Normal 2.0
Mode
External/Internal
Loopback
Mode
Listen Only
Mode
“Normal” Modes “Debug” Modes
Restricted
Operation
Mode
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 55
CAN FD Protocol Module
4.2 Configuration Mode
After Reset, the CAN FD Protocol Module is in Configuration mode. The error counters are
cleared and all registers contain the Reset values.
The CAN FD Protocol Module has to be initialized before activation. This is only possible when
the module is in Configuration mode, OPMOD[2:0] = . The Configuration mode is requested100
by setting REQOP[2:0] = .100
The CAN FD Protocol Module will protect the user from accidentally violating the CAN protocol
through programming errors. The following registers and bit fields can only be programmed
during Configuration mode:
• CxCONL: WAKFIL, CLKSEL, PXEDIS, ISOCRCEN
• CxCONH: TXQEN, STEF, SERRLOM, ESIGM, RTXAT
• CxNBTCFGL/H, CxDBTCFGL/H, CxTDCL/H
• CxTXQCONH: PLSIZE[2:0], FSIZE[4:0]
• CxFIFOCONxL: TXEN, RXTSEN
• CxFIFOCONxH: PLSIZE[2:0], FSIZE[4:0]
• CxTEFCONL: TEFTSEN
• CxTEFCONH: FSIZE[4:0]
• CxFIFOBAL/H
The CAN FD Protocol Module is not allowed to enter Configuration mode during transmission or
reception to prevent the module from causing errors on the CAN bus. The following registers
are reset when exiting Configuration mode:
• CxTRECL/H
• CxBDIAG0L/H
• CxBDIAG1L/H
In Configuration mode, FRESET is set in the CxFIFOCONxL, CxTXQCONL and CxTEFCONL
registers, and all FIFOs and the TXQ are reset.
4.3 Normal Modes
4.3.1 NORMAL CAN FD MODE
Once the device is configured, Normal Operation mode can be requested by setting
REQOP[2:0] = . 000
In this mode, the device will be on the CAN bus. It can transmit and receive messages in CAN
FD mode, Bit Rate Switching can be enabled, and up to 64 data bytes can be transmitted and
received.
4.3.2 NORMAL CAN 2.0 MODE
The Normal CAN 2.0 Operation mode can be requested by setting REQOP[2:0] = . 110
In this mode, the device will be on the CAN bus. This is a the Classic CAN 2.0 mode. The
module will not receive CAN FD frames. It might send error frames if CAN FD frames are
detected on the bus. The FDF, BRS and ESI bits in the TX objects will be ignored and
transmitted as ‘ ’. 0
dsPIC33/PIC24 Family Reference Manual
DS70005340C-page 56 2018-2022 Microchip Technology Inc.and its subsidiaries
4.4 Disable Mode
Disable mode is similar to Configuration mode, except the error counters are not reset. Disable
mode is requested by setting REQOP[2:0] = 001.
The CAN module will not be allowed to enter Disable mode while a transmission or reception is
taking place to prevent causing errors on the CAN bus. The module will enter Disable mode when
the current message completes.
The OPMODx bits indicate whether the module successfully entered Disable mode. The application
software should use this bit field as a handshake indication for the Disable mode request.
The CxTX pin will stay in the recessive state while the module is in Disable mode to prevent
inadvertent CAN bus errors.
4.5 Debug Modes
4.5.1 LISTEN ONLY MODE
Listen Only mode is a variant of Normal CAN FD Operation mode. If the Listen Only mode is
activated, the module on the CAN bus is passive. It will receive messages, but it will not transmit
any bits. TXREQx bits will be ignored. No error flags or Acknowledge signals are sent. The error
counters are deactivated in this state. The Listen Only mode can be used for detecting the baud
rate on the CAN bus. It is necessary that there are at least two further nodes that communicate
with each other. The baud rate can be detected empirically by testing different values until a
message is received successfully. This mode is also useful for monitoring the CAN bus without
influencing it.
4.5.2 RESTRICTED OPERATION MODE
In Restricted Operation mode, the node is able to receive data and remote frames, and to
Acknowledge valid frames, but it does not send data frames, remote frames, error frames or
overload frames. In case of an error or overload condition, it does not send dominant bits; instead,
it waits for the bus to enter the Idle condition to resynchronize itself to the CAN communication.
The error counters are not incremented.
4.5.3 LOOPBACK MODE
Loopback mode is a variant of Normal CAN FD Operation mode. This mode will allow internal
transmission of messages from the transmit FIFOs to the receive FIFOs. The module does not
require an external Acknowledge from the bus. No messages can be received from the bus,
because the CxRX pin is disconnected.
4.5.3.1 Internal Loopback Mode
The transmit signal is internally connected to receive and the CxTX pin is driven high.
4.5.3.2 External Loopback Mode
The transmit signal is internally connected to receive and transmit messages, and can be
monitored on the CxTX pin.
2018-2022 Microchip Technology Inc. and its subsidiaries DS70005340C-page 57
CAN FD Protocol Module
4.6 Low-Power Modes
4.6.1 SLEEP MODE
In the CAN module, special conditions need to be met for Sleep mode. The module must first be
switched to Disable mode by setting REQOPx = 001. When OPMODx = 001, indicating Disable
mode has been achieved, the CAN FD Protocol Module enters Sleep mode after a Sleep mode
request.
In Sleep mode, the register contents do not change, so the OPMODx bits do not change. At the
end of Sleep, the module will continue in the mode specified by the OPMODx bits previous to
Sleep mode (which should be Disable mode, OPMODx = ).001
If the user executes a instruction without switching to Disable mode, the moduleSLEEP
assumes a clock is available to read/write from RAM.
Since the system clock input is not available in Sleep mode, the CAN module cannot run as it
requires a system clock to transmit or receive. Also, the FIFO is in system RAM, which has no
clock in Sleep mode.
Recommended steps:
1. Write the REQOP[2:0] bits to ‘ ’; the module will enter Disable mode.001
2. Poll the OPMOD[2:0] bits to verify whether they are ‘ ’, which indicates that the module001
has successfully entered Disable mode.
3. Execute the instruction.SLEEP
4.6.2 IDLE MODE
The system can be set to run in a low-power mode, called Idle mode. When the device is in Idle
mode, the CPU is disabled and only select peripherals are active.
Based on the configuration of the CAN SIDL bit, the module can either be in or out of Idle mode:
• If SIDL = , the module continues operation in Idle mode. If the module generates an 0
interrupt while in Idle mode, the interrupt may generate a wake-up event.
• If SIDL = , the module stops when the device is in Idle mode. The module performs the 1
same procedures when stopped in Idle mode as it does in Disable mode and the same
requirements apply.
The user should ensure that the module is not active when the CPU transitions to Idle mode
with SIDL = . To protect the CAN bus system from fatal consequences due to violation of this1
rule, the module will drive the TX pin into the recessive state while stopped in Idle mode.
If the CAN SIDL bit is set, the recommended procedure is to bring the module into Disable
mode before the device is placed in Idle mode.
4.6.3 WAKE-UP FROM SLEEP
Figure 4-2 depicts how the CAN module will execute the SLEEP instruction and how the module
wakes up on bus activity. Upon a wake-up from Sleep mode, the WAKIF flag is set.
dsPIC33/PIC24 Family Reference Manual
DS70005340C-page 58 2018-2022 Microchip Technology Inc.and its subsidiaries
Figure 4-2: Processor Sleep and CAN Bus Wake-up Interrupt
The module will monitor the CAN receive line for activity while the module is Sleeping. The
device will generate a wake-up interrupt on the falling edges of CxRX if WAKIE is enabled.
The device will exit Sleep mode after a new mode request or a negative edge on CxRX.
The module will be in Sleep mode if either of the following is true:
• The system is in Sleep mode following Disable mode
• The system is in Idle mode with SIDL = 1
TOST
Processor in
Sleep
23 4 5
– Processor executes ( ) instruction.SLEEP PWRSAV #0
– SOF of message wakes up processor. Oscillator start time begins. CAN message is lost. WAKIF bit is set.
– Processor completes oscillator start time. Processor resumes program or interrupt, based on GIE bits.
accepting CAN bus activity. CAN message is lost.
– Module detects 11 recessive bits. Module will begin to receive messages and transmits any pending messages.
OSC1
CAN Bus
Disabled
001
001000
000 000
000
Sleep
WAKIF
WAKIE
1
– Processor requests and receives Module Disable mode. Wake-up interrupt is enabled.
Processor requests Normal Operating mode. Module waits for 11 recessive bits before
1
2
3
4
5
REQOP[2:0]
OPMOD[2:0]
CAN Module
Note 1: If the module is in Sleep mode, the module generates an interrupt if the WAKIE bit
(CxINTH[14]) is set and bus activity is detected. Due to delays in starting up the
oscillator and CPU, the message activity that caused the wake-up will be lost.
2: The module can be programmed to apply a low-pass filter function to the CAN
receive input line while in Disable, Sleep or Idle mode. This feature can be used to
protect the module from wake-up due to short glitches on the CAN bus lines. The
WAKFIL bit (CxCONL[8]) enables or disables the filter while the module is in Sleep.

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: dsPIC33/PIC24FRM

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