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© 2006-2012 Microchip Technology Inc. DS70183D-page 16-1
Analog-to-Digital
Converter (ADC)
16
Section 16. Analog-to-Digital Converter (ADC)
HIGHLIGHTS
This section of the manual contains the following major topics:
16.1 Introduction .................................................................................................................. 16-2
16.2 Control Registers ......................................................................................................... 16-6
16.3 Overview of Sample and Conversion Sequence ....................................................... 16-17
16.4 ADC Configuration..................................................................................................... 16-27
16.5 ADC Interrupt Generation .......................................................................................... 16-33
16.6 Analog Input Selection for Conversion....................................................................... 16-35
16.7 Specifying Conversion Results Buffering for Devices with DMA................................ 16-44
16.8 ADC Configuration Example ...................................................................................... 16-48
16.9 ADC Configuration for 1.1 Msps ................................................................................16-49
16.10 Sample and Conversion Sequence Examples for Devices without DMA .................. 16-51
16.11 Sample and Conversion Sequence Examples for Devices with DMA ....................... 16-63
16.12 Analog-to-Digital Sampling Requirements ................................................................. 16-73
16.13 Reading the ADC Result Buffer .................................................................................16-74
16.14 Transfer Functions ..................................................................................................... 16-76
16.15 ADC Accuracy/Error................................................................................................... 16-78
16.16 Connection Considerations........................................................................................ 16-78
16.17 Operation During Sleep and Idle Modes .................................................................... 16-79
16.18 Effects of a Reset....................................................................................................... 16-79
16.19 Special Function Registers ........................................................................................ 16-80
16.20 Design Tips ................................................................................................................ 16-81
16.21 Related Application Notes.......................................................................................... 16-82
16.22 Revision History ......................................................................................................... 16-83
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-2 © 2006-2012 Microchip Technology Inc.
16.1 INTRODUCTION
This document describes the features and associated operational modes of the Successive
Approximation (SAR) Analog-to-Digital Converter (ADC) available on the dsPIC33F/PIC24H
families of devices.
The ADC module can be configured by the user application to function as a 10-bit, 4-channel
ADC (for devices with 10-bit only ADC) or a 12-bit, single-channel ADC (for devices with
selectable 10-bit or 12-bit ADC).
Figure 16-1 illustrates a block diagram of the ADC module for devices with DMA. Figure 16-2
illustrates a block diagram of the ADC module for devices without DMA.
The dsPIC33F/PIC24H ADC module has the following key features:
SAR conversion
Up to 1.1 Msps conversion speed
Up to 32 analog input pins
External voltage reference input pins
Four unipolar differential Sample and Hold (S&H) amplifiers
Simultaneous sampling of up to four analog input pins
Automatic Channel Scan mode
Selectable conversion trigger source
Up to 16-word conversion result buffer
Selectable Buffer Fill modes (not available on all devices)
DMA support, including Peripheral Indirect Addressing (not available on all devices)
Operation during CPU Sleep and Idle modes
Depending on the device variant, the ADC module may have up to 32 analog input pins,
designated AN0-AN31. These analog inputs are connected by multiplexers to four S&H
amplifiers, designated CH0-CH3. The analog input multiplexers have two sets of control bits,
designated as MUXA (CHySA/CHyNA) and MUXB (CHySB/CHyNB). These control bits select a
particular analog input for conversion. The MUXA and MUXB control bits can alternatively select
the analog input for conversion. Unipolar differential conversions are possible on all channels
using certain input pins (see Figure 16-1 Figure 16-2 and ).
Channel Scan mode can be enabled for the CH0 S&H amplifier. Any subset of the analog inputs
(AN0 to AN31 based on availability) can be selected by the user application. The selected inputs
are converted in ascending order using CH0.
The ADC module supports simultaneous sampling using multiple S&H channels to sample the
inputs at the same time, and then performs the conversion for each channel sequentially. By
default, the multiple channels are sampled and converted sequentially.
For devices with DMA, the ADC module is connected to a single-word result buffer. However,
multiple conversion results can be stored in a DMA RAM buffer with no CPU overhead when
DMA is used with the ADC module. Each conversion result is converted to one of four 16-bit
output formats when it is read from the buffer.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33F/PIC24H devices.
Please consult the note at the beginning of the “Analog-to-Digital Converter
(ADC)” chapter in the current device data sheet to check whether this document
supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-3
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
For devices without DMA, the ADC module is connected to a 16-word result buffer. The ADC
result is available in four different numerical formats (see Figure 16-14).
Note 1: A ‘y’ is used with MUXA and MUXB control bits to specify the S&H channel numbers
(y = 0 or 123).
2: Depending on a particular device pinout, the ADC can have up to 32 analog input
pins, designated AN0 through AN31. In addition, there are two analog input pins for
external voltage reference connections (VREF+, VREF-). These voltage reference
inputs can be shared with other analog input pins. The actual number of analog
input pins and external voltage reference input configuration depends on the
specific device. For further details, refer to the specific device data sheet.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-4 © 2006-2012 Microchip Technology Inc.
Figure 16-1: ADC Block Diagram for Devices with DMA
SAR ADC
S/H0
S/H1
AN0
AN31
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
AN9
VREFL
CH123SB
CH123NA CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
AN10
VREFL
CH123SB
CH123NA CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
AN11
VREFL
CH123SB
CH123NA CH123NB
AN8
+
-
CH1(2)
CH0
CH2(2)
CH3(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For details, refer to the “Pin Diagrams” section in the specific device
data sheet.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
Input Selection
VREFH VREFL
V +REF (1) AV AVDD SS
V -REF (1)
VCFG<2:0>
Bus Interface
ADC1BUF0
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-5
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Figure 16-2: ADC Block Diagram for Devices without DMA
SAR ADC
S/H0
S/H1
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUFF
ADC1BUFE
AN0
AN31
AN1
VREFL
CH0SB<4:0>
CH0NA CH0NB
+
-
AN0
AN3
CH123SA
AN9
VREFL
CH123SB
CH123NA CH123NB
AN6
+
-
S/H2
AN1
AN4
CH123SA
AN10
VREFL
CH123SB
CH123NA CH123NB
AN7
+
-
S/H3
AN2
AN5
CH123SA
AN11
VREFL
CH123SB
CH123NA CH123NB
AN8
+
-
CH1(2)
CH0
CH2(2)
CH3(2)
CH0SA<4:0>
CHANNEL
SCAN
CSCNA
Alternate
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. For details, refer to the “Pin Diagrams” section in the specific device
data sheet.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
Input Selection
VREFH VREFL
V +REF (1) AV AVDD SS
V -REF (1)
VCFG<2:0>
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-6 © 2006-2012 Microchip Technology Inc.
16.2 CONTROL REGISTERS
The ADC module has ten Control and Status registers. These registers are:
ADxCON1: ADCx Control Register 1
ADxCON2: ADCx Control Register 2
ADxCON3: ADCx Control Register 3
ADxCON4: ADCx Control Register 4
ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register
ADxCHS0: ADCx Input Channel 0 Select Register
AD1CSSH: ADC1 Input Scan Select Register High
ADxCSSL: ADCx Input Scan Select Register Low
AD1PCFGH: ADC1 Port Configuration Register High
ADxPCFGL: ADCx Port Configuration Register Low
The ADxCON1, ADxCON2 and ADxCON3 registers control the operation of the ADC module.
The ADxCON4 register sets up the number of conversion results stored in a DMA buffer for each
analog input in the Scatter/Gather mode for devices with DMA. The ADxCHS123 and ADxCHS0
registers select the input pins to be connected to the S&H amplifiers. The ADCSSH/L registers
select inputs to be sequentially scanned. The ADxPCFGH/L registers configure the analog input
pins as analog inputs or as digital I/O.
16.2.1 ADC Result Buffer
For devices with DMA, the ADC module contains a single-word result buffer, ADC1BUF0. For
devices without DMA, the ADC module contains a 16-word dual-port RAM, to buffer the results.
The 16 buffer locations are referred to as ADC1BUF0, ADC1BUF1, ADC1BUF2, ..., ADC1BUFE
and ADC1BUFF.
Note: After a device reset, the ADC buffer register(s) will contain unknown data.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-7
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-1: ADxCON1: ADCx Control Register 1
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
ADON ADSIDL ADDMABM(2) — AD12B(2) FORM<1:0>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0> SIMSAM ASAM SAMP DONE
bit 7 bit 0
Legend: HC = Cleared by hardware HS = Set by hardware C = Clear only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14 Unimplemented: Read as ‘0
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 ADDMABM: DMA Buffer Build Mode bit(3)
1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0 = DMA buffers are written in Scatter/Gather mode. The module provides a Scatter/Gather address to
the DMA channel, based on the index of the analog input and the size of the DMA buffer
bit 11 Unimplemented: Read as ‘0
bit 10 AD12B: 10-bit or 12-bit Operation Mode bit(2)
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
bit 9-8 FORM<1:0>: Data Output Format bits
For 10-bit operation:
11 sddd dddd dd00 0000 = Signed fractional (DOUT = , where s d = sign, = data)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 ssss sssd dddd dddd = Signed integer (DOUT = , where s d = sign, = data)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11 sddd dddd dddd 0000 = Signed fractional (DOUT = , where s d = sign, = data)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 ssss sddd dddd dddd = Signed Integer (DOUT = , where s = sign, d = data)
00 = Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Motor Control PWM2 interval ends sampling and starts conversion(1)
100 = GP timer (Timer5 for ADC1, Timer3 for ADC2) compare ends sampling and starts conversion
(2)
011 = Motor Control PWM1 interval ends sampling and starts conversion(1)
010 = GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
bit 4 Unimplemented: Read as ‘0
Note 1: This clock source is not available on all devices. Refer to the specific device data sheet for availability.
2: This bit is not available on all devices. Refer to the “Analog-to-Digital Converter” chapter in the specific
device data sheet for availability.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-8 © 2006-2012 Microchip Technology Inc.
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 1x or )
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion. SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit
1 = ADC S&H amplifiers are sampling
0 = ADC S&H amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADC Conversion Status bit
1 = ADC conversion cycle is completed
0 = ADC conversion not started or in progress
Automatically set by hardware when analog-to-digital conversion is complete. Software can write ‘0’ to
clear DONE status (software not allowed to write 1’). Clearing this bit does NOT affect any operation
in progress. Automatically cleared by hardware at the start of a new conversion.
Register 16-1: ADxCON1: ADCx Control Register 1 (Continued)
Note 1: This clock source is not available on all devices. Refer to the specific device data sheet for availability.
2: This bit is not available on all devices. Refer to the “Analog-to-Digital Converter” chapter in the specific
device data sheet for availability.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-9
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-2: ADxCON2: ADCx Control Register 2
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
VCFG<2:0> — CSCNA CHPS<1:0>
bit 15 bit 8
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS — SMPI<3:0>(1,2) BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
bit 12-11 Unimplemented: Read as ‘0
bit 10 CSCNA: Input Scan Select bit
1 = Scan inputs for CH0+ during Sample A bit
0 = Do not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADC is currently filling the second half of the buffer. The user application should access data in the
first half of the buffer
0 = ADC is currently filling the first half of the buffer. The user application should access data in the
second half of the buffer
bit 6 Unimplemented: Read as ‘0
Note 1: For devices with DMA, the SMPI<3:0> bits are referred to as the Increment Rate for DMA Address Select
bits.
2: For devices without DMA, the SMPI<3:0> bits are referred to as the Number of Samples Per Interrupt
Select bits.
3: The VREF+ and VREF- pins are not available on all devices. Refer to the “Pin Diagrams” section in the
specific device data sheet for availability.
VREFH VREFL
000 AVDD AVss
001 External VREF+(3) AVss
010 AVDD External VREF-(3)
011 External VREF+(3) External VREF-(3)
1xx AVDD AVss
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-10 © 2006-2012 Microchip Technology Inc.
bit 5-2 SMPI<3:0>: Sample and Conversion Operation bits (1,2)
For devices with DMA:
1111 = Increments the DMA address after completion of every 16th sample/conversion operation
1110 = Increments the DMA address after completion of every 15th sample/conversion operation
0001 = Increments the DMA address after completion of every 2nd sample/conversion operation
0000 = Increments the DMA address after completion of every sample/conversion operation
For devices without DMA:
1111 = ADC interrupt is generated at the completion of every 16th sample/conversion operation
1110 = ADC interrupt is generated at the completion of every 15th sample/conversion operation
0001 = ADC interrupt is generated at the completion of every 2nd sample/conversion operation
0000 = ADC interrupt is generated at the completion of every sample/conversion operation
bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts filling the first half of the buffer on the first interrupt and the second half of the buffer on the
next interrupt
0 = Always starts filling the buffer from the start address
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
Register 16-2: ADxCON2: ADCx Control Register 2 (Continued)
Note 1: For devices with DMA, the SMPI<3:0> bits are referred to as the Increment Rate for DMA Address Select
bits.
2: For devices without DMA, the SMPI<3:0> bits are referred to as the Number of Samples Per Interrupt
Select bits.
3: The V REF+ and VREF- pins are not available on all devices. Refer to the “Pin Diagrams” section in the
specific device data sheet for availability.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-11
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-3: ADxCON3: ADCx Control Register 3
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADRC — SAMC<4:0>(1,2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCS<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADRC: ADC Conversion Clock Source bit
1 = ADC Internal RC Clock
0 = Clock Derived from System Clock
bit 14-13 Unimplemented: Read as ‘0
bit 12-8 SAMC<4:0>: Auto Sample Time bits(1,2)
11111 = 31 TAD
00001 = 1 T
AD
00000 = 0 TAD
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits
11111111 = Reserved
01000000 = Reserved
00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD
00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD
00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD
00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD
Note 1: This bit is only used when the SSRC<2:0> bits (ADxCON1<7:5>) = 111.
2: If SSRC<2:0> = 111, the SAMC bit should be set to at least ‘1’ when using one S&H channel or using
simultaneous sampling. When using multiple S&H channels with sequential sampling, the SAMC bit
should be set to0’ for the fastest possible conversion rate.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-12 © 2006-2012 Microchip Technology Inc.
Register 16-4: ADxCON4: ADCx Control Register 4
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — DMABL<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0
bit 2-0 DMABL<2:0>: DMA Buffer Locations per Analog Input bits
111 = Allocates 128 words of buffer to each analog input
110 = Allocates 64 words of buffer to each analog input
101 = Allocates 32 words of buffer to each analog input
100 = Allocates 16 words of buffer to each analog input
011 = Allocates 8 words of buffer to each analog input
010 = Allocates 4 words of buffer to each analog input
001 = Allocates 2 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input
Note: This register is not available in devices without DMA. Refer to the “Direct Memory Access (DMA)”
chapter in the specific device data sheet for availability.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-13
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-5: ADxCHS123: ADCx Input Channel 1, 2, 3 Select Register
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CH123NB<1:0> CH123SB
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CH123NA<1:0> CH123SA
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0
bit 10-9 CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is V
REFL
bit 8 CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3 Unimplemented: Read as 0
bit 2-1 CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is V
REFL
bit 0 CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-14 © 2006-2012 Microchip Technology Inc.
Register 16-6: ADxCHS0: ADCx Input Channel 0 Select Register
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB — CH0SB<4:0>(1)
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA — CH0SA<4:0>(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13 Unimplemented: Read as ‘0
bit 12-8 CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
(1)
Same definition as bit<4:0>.
bit 7 CH0NA: Channel 0 Negative Input Select for Sample A bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
REFL
bit 6-5 Unimplemented: Read as 0
bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1,2)
11111 = Channel 0 positive input is AN31
11110 = Channel 0 positive input is AN30
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
Note 1: The AN16 through AN31 pins are not available for ADC2.
2: These bits have no effect when the CSCNA bit (ADxCON2<10>) = 1.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-15
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Register 16-7: AD1CSSH: ADC1 Input Scan Select Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSS<31:16>: ADC Input Scan Selection bits
(1,2)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 Input Scan Select Register High exists.
2: A maximum of 16 inputs (any) can be scanned.
Note: This register is not available in devices without DMA. Refer to the “Analog-to-Digital Converter (ADC)”
chapter in the specific device data sheet for availability.
Register 16-8: ADxCSSL: ADCx Input Scan Select Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS15(3) CSS14(3) CSS13(3) CSS12 CSS11 CSS10 CSS9 CSS8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CSS<15:0>: ADC Input Scan Selection bits(1,2)
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: On devices with less than 16 analog inputs, all ADxCSSL bits can be selected by the user. However,
inputs selected for scan without a corresponding input on device convert VREF-.
2: A maximum of 16 inputs (any) can be scanned.
3: This bit is not available in devices without DMA. Refer to the “Analog-to-Digital Converter (ADC)”
chapter in the specific device data sheet for availability.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-16 © 2006-2012 Microchip Technology Inc.
Register 16-9: AD1PCFGH: ADC1 Port Configuration Register High
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG31 PCFG30 PCFG29 PCFG28 PCFG27 PCFG26 PCFG25 PCFG24
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG23 PCFG22 PCFG21 PCFG20 PCFG19 PCFG18 PCFG17 PCFG16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PCFG<31:16>: ADC Port Configuration Control bits(1,2)
1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices with less than 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are
ignored on ports without a corresponding input on device.
2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 Port Configuration register exists.
Note: This register is not available in devices without DMA. Refer to the “Analog-to-Digital Converter (ADC)”
chapter in the specific device data sheet for availability.
Register 16-10: ADxPCFGL: ADCx Port Configuration Register Low
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG15(3) PCFG14(3) PCFG13(3) PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PCFG<15:0>: ADC Port Configuration Control bits(1,2)
1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices with less than 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are
ignored on ports without a corresponding input on device.
2: On devices with two ADC modules, both AD1PCFGL and AD2PCFGL affect the configuration of port pins
multiplexed with AN0-AN15.
3: This bit is not available in devices without DMA. Refer to the “Analog-to-Digital Converter (ADC)”
chapter in the specific device data sheet for availability.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-17
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.3 OVERVIEW OF SAMPLE AND CONVERSION SEQUENCE
Figure 16-3 illustrates that the analog-to-digital conversion is a three step process:
1. The input voltage signal is connected to the sample capacitor.
2. The sample capacitor is disconnected from the input.
3. The stored voltage is converted to equivalent digital bits.
The two distinct phases, sample and conversion, are independently controlled.
Figure 16-3: Sample Conversion Sequence
16.3.1 Sample Time
Sample Time is when the selected analog input is connected to the sample capacitor. There is a
minimum sample time to ensure that the S&H amplifier provides a desired accuracy for the
analog-to-digital conversion (see 16.12 “Analog-to-Digital Sampling Requirements”).
The sampling phase can be set up to start automatically upon conversion or by manually setting
the Sample bit (SAMP) in the ADC Control Register 1 (ADxCON1<1>). The sampling phase is
controlled by the Auto-Sample bit (ASAM) in the ADC Control Register 1 (ADxCON1<2>).
Table 16-1 lists the options selected by the specific bit configuration.
Table 16-1: Start of Sampling Selection
If automatic sampling is enabled, the sampling time (TSMP) taken by the ADC module is equal to
the number of TAD cycles defined by the SAMC<4:0> bits (ADxCON3<12:8>), as shown by
Equation 16-1.
Equation 16-1: Sampling Time Calculation
If manual sampling is desired, the user software must provide sufficient time to ensure adequate
sampling time.
+
-
+
-
SAR
ADC
Sample Time Conversion Time
SOC
Trigger
Note: The ADC module requires a finite number of analog-to-digital clock cycles to start
conversion after receiving a conversion trigger or stopping the sampling process.
Refer to the TPCS parameter in the “Electrical Characteristics” chapter of the spe-
cific device data sheet for further details.
ASAM Start of Sampling Selection
0Manual sampling
1Automatic sampling
TSMP = SAMC<4:0> TAD
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-18 © 2006-2012 Microchip Technology Inc.
16.3.2 Conversion Time
The Start of Conversion (SOC) trigger ends the sampling time and begins an analog-to-digital
conversion. During the conversion period, the sample capacitor is disconnected from the
multiplexer, and the stored voltage is converted to equivalent digital bits. The conversion time for
10-bit and 12-bit modes are shown in Equation 16-2 and Equation 16-3. The sum of the sample
time and the analog-to-digital conversion time provide the total conversion time.
For correct analog-to-digital conversion, the analog-to-digital conversion clock (TAD) must be
selected to ensure a minimum TAD time. Refer to the “Electrical Characteristics” chapter of the
specific device data sheet for the minimum TAD specifications for 10-bit and 12-bit modes.
Equation 16-2: 10-bit ADC Conversion Time
Equation 16-3: 12-bit ADC Conversion Time
The SOC can be triggered by a variety of hardware sources or controlled manually in user soft-
ware. The trigger source to initiate conversion is selected by the SOC Trigger Source Select bits
(SSRC<2:0>) in the ADC Control register (ADxCON1<7:5>). Table 16-2 lists the conversion
trigger source selection for different bit settings.
Table 16-2: SOC Trigger Selection
Table 16-3 lists the sample conversion sequence with different sample and conversion phase
selections.
Note: 12-bit mode is not available on all devices. Refer to the “Analog-to-Digital
Converter (ADC) chapter in the specific device data sheet for availability.
TCONV = 12 TAD
Where:
TCONV = Conversion Time
TAD = ADC Clock Period
Where:
TCONV = Conversion Time
TCONV = 14 TAD
TAD = ADC Clock Period
SSRC<2:0>(1) SOC Trigger Source
000 Manual Trigger
001 External Interrupt Trigger (INT0)
010 Timer Interrupt Trigger
011 Motor Control PWM Special Event Trigger
100 Timer Interrupt Trigger
111 Automatic Trigger
Note 1: The SSRC<2:0> selection bits should not be changed when the ADC module is
enabled.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-19
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Table 16-3: Sample Conversion Sequence Selection
16.3.3 Manual Sample and Manual Conversion Sequence
In the Manual Sample and Manual Conversion Sequence, setting the Sample bit (SAMP) in the
ADC Control Register 1 (ADxCON1<1>) initiates sampling, and clearing the SAMP bit terminates
sampling and starts conversion (see Figure 16-4). The user application must time the setting and
clearing of the SAMP bit to ensure adequate sampling time for the input signal. Example 16-1
illustrates a code sequence for Manual Sample and Manual Conversion.
Figure 16-4: Manual Sample and Manual Conversion Sequence
Example 16-1: Code Sequence for Manual Sample and Manual Conversion
ASAM SSRC<2:0> Description
0 000 Manual Sample and Manual Conversion Sequence
0 111 Manual Sample and Automatic Conversion Sequence
0 001
010
011
100
Manual Sample and Triggered Conversion Sequence
1 000 Automatic Sample and Manual Conversion Sequence
1 111 Automatic Sample and Automatic Conversion Sequence
1 001
010
011
100
Automatic Sample and Triggered Conversion Sequence
+
-
+
-
Sample Time Conversion Time
SAMP
12
Sample Time
+
-
3 4
Conversion
5
Note 1: Sampling is started by setting the SAMP bit in software.
2: Conversion is started by clearing the SAMP bit in software.
3: Conversion is complete.
4: Sampling is started by setting the SAMP bit in software.
5: Conversion is started by clearing the SAMP bit in software.
AD1CON1bits.SAMP = 1; // Start sampling
DelayUs(10); // Wait for sampling time (10us)
AD1CON1bits.SAMP = 0; // Start the conversion
while (!AD1CON1bits.DONE); // Wait for the conversion to complete
ADCValue = ADC1BUF0; // Read the conversion result
Note: Due to the internal delay within the ADC module, the SAMP bit will read as 0to the
user software after a small interval of time after the conversion has already begun.
In general, the time interval will be 2 TCY.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-20 © 2006-2012 Microchip Technology Inc.
16.3.4 Automatic Sample and Manual Conversion Sequence
In the Automatic Sample and Manual Conversion Sequence, sampling starts automatically after
conversion of the previous sample. The user application must allocate sufficient time for
sampling before clearing the SAMP bit. Clearing the SAMP bit initiates conversion (see
Figure 16-5).
Figure 16-5: Automatic Sample and Manual Conversion Sequence
Example 16-2: Code Sequence for Automatic Sample and Manual Conversion
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-21
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.3.5 Automatic Sample and Automatic Conversion Sequence
16.3.5.1 CLOCKED CONVERSION TRIGGER
The Auto Conversion method provides a more automated process to sample and convert the
analog inputs as shown in Figure 16-6. The sampling period is self-timed and the conversion
starts automatically upon termination of a self-timed sampling period. The Auto Sample Time bits
(SAMC<4:0>) in the ADxCON3 register (ADxCON3<12:8>) select 0 to 31 ADC clock cycles (TAD)
for sampling period. Refer to the ecific device data“Electrical Characteristics” chapter of the sp
sheet for a minimum recommended sampling time (SAMC value).
The SSRC<2:0> bits are set to ‘ ’ to choose the internal counter as the sample clock source,111
which ends sampling and starts conversion.
Figure 16-6: Automatic Sample and Automatic Conversion Sequence
+
-
+
-
Sample Time Conversion Time
SAMP
12
Sample Time
+
-
3 4
Conversion
Note 1: Sampling starts automatically after conversion.
2: Conversion starts automatically upon termination of self timed sampling period.
3: Sampling starts automatically after conversion.
4: Conversion starts automatically upon termination of self timed sampling period.
N TAD N TAD
Conversion
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-22 © 2006-2012 Microchip Technology Inc.
16.3.5.2 EXTERNAL CONVERSION TRIGGER
In an Automatic Sample and Triggered Conversion Sequence, the sampling starts automatically
after conversion and the conversion is started upon trigger event from the selected peripheral,
as shown in Figure 16-7. This allows ADC conversion to be synchronized with the internal or
external events. The external conversion trigger is selected by configuring the SSRC<2:0> bits
to 001’, 010 or ‘011’. See 16.4.7 “Conversion Trigger Sources” for various external
conversion trigger sources.
The ASAM bit should not be modified while the ADC module is turned on. If automatic sampling
is desired, the ASAM bit must be set before turning the module on. The ADC module does take
some amount of time to stabilize (see the TPDU parameter in the specific device data sheet);
therefore, if automatic sampling is enabled, there is not guarantee that the first ADC result will be
correct until the ADC module stabilizes. It may be necessary to discard the first ADC result
depending on the analog-to-digital clock speed.
Figure 16-7: Automatic Sample and Triggered Conversion Sequence
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-23
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.3.6 Multi-Channel Sample Conversion Sequence
Multi-channel ADC modules typically convert each input channel sequentially using an input
multiplexer. Simultaneously sampling multiple signals ensures that the snapshot of the analog
inputs occurs at precisely the same time for all inputs, as shown in Figure 16-8.
Certain applications require simultaneous sampling, especially when phase information exists
between different channels. Sequential sampling takes a snapshot of each analog input just
before conversion starts on that input, as shown in Figure 16-8. The sampling of multiple inputs
is not correlated. For example, motor control and power monitoring require voltage and current
measurements and the phase angle between them.
Figure 16-8: Simultaneous and Sequential Sampling
Figure 16-9 and Figure 16-10 illustrate the ADC module supports simultaneous sampling using
two S&H or four S&H channels to sample the inputs at the same instant and then perform the
conversion for each channel sequentially.
The Simultaneous Sampling mode is selected by setting Simultaneous Sampling bit (SIMSAM)
in the ADC Control Register 1 (ADxCON1<3>). By default, the channels are sampled and
converted sequentially. Table 16-4 lists the options selected by a specific bit configuration. The
CHPS<1:0> bits determine the channels to be sampled, either sequentially or simultaneously.
Table 16-4: Start of Sampling Selection
SIMSAM Sampling Mode
0Sequential sampling
1Simultaneous sampling
AN0
AN1
AN2
AN3
Simultaneous
Sampling
Sequential
Sampling
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-24 © 2006-2012 Microchip Technology Inc.
Figure 16-9: 2-Channel Simultaneous Sampling (ASAM = 1)
For simultaneous sampling, the total time taken to sample and convert the channels is shown by
Equation 16-4.
Equation 16-4: Channel Sample and Conversion Total Time, Simultaneous Sampling
Selected
Sample 1
Sample 1
CH0
CH1
Convert 1
Convert 1
SOC
Trigger
Sample 2
Sample 2
Convert 2
Convert 2
Sample/Convert Sequence 1 Sample/Convert Sequence 2
1
2 43
5
Note 1: CH0-CH1 Input multiplexer selects analog input for sampling. The selected analog input
is connected to the sample capacitor.
2: On SOC Trigger, CH0-CH1 sample capacitor is disconnected from the multiplexer to
simultaneously sample the analog inputs. The analog value captured in CH0 is
converted to equivalent digital bits.
3: The analog voltage captured in CH1 is converted to equivalent digital bits.
4: CH0-CH1 Input multiplexer selects next analog input for sampling. The selected analog
input is connected to the sample capacitor.
5: On SOC Trigger, CH0-CH1 sample capacitor is disconnected from the multiplexer to
simultaneously sample the analog inputs. The analog value captured in CH0 is
converted to equivalent digital bits.
TSIM TSIM
TS I M TS M P M TC ONV
( )+=
Where:
TSIM = Total time to sample and convert multiple channels with simultaneous sampling.
TSMP = Sampling Time (see Equation 16-1)
TCONV = Conversion Time (see Equation 16-2)
M = Number of channels selected by the CHPS<1:0> bits.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-25
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Figure 16-10: 4-Channel Simultaneous Sampling
Figure 16-11 and Figure 16-12 illustrate that by default, the multiple channels are sampled and
converted sequentially.
For sequential sampling, the total time taken to sample and convert the channels is shown in
Equation 16-5.
Equation 16-5: Channel Sample and Conversion Total Time, Sequential Sampling
Selected
Sample 1
Sample 1
CH0
CH1
Sample 1
Sample 1
CH2
CH3
Convert 1
Convert 1
Convert 1
SOC
Trigger
Convert 1
Sample 2
Sample 2
Sample 2
Sample 2
Convert 2
Convert 2
Convert 2
Convert2
Sample/Convert Sequence 1 Sample/Convert Sequence 2
1 2 4 73 5 6
Note 1: CH0-CH3 Input multiplexer selects analog input for sampling. The selected analog input is connected to the
sample capacitor.
2: On SOC Trigger, CH0-CH3 sample capacitor is disconnected from the multiplexer to simultaneously sample
the analog inputs. The analog value captured in CH0 is converted to equivalent digital bits.
3: The analog voltage captured in CH1 is converted to equivalent digital bits.
4: The analog voltage captured in CH2 is converted to equivalent digital bits.
5: The analog voltage captured in CH3 is converted to equivalent digital bits.
6: CH0-CH3 Input multiplexer selects next analog input for sampling. The selected analog input is connected to
the sample capacitor.
7: On SOC Trigger, CH0-CH3 sample capacitor is disconnected from the multiplexer to simultaneously sample
the analog inputs. The analog value captured in CH0 is converted to equivalent digital bits.
TSIM TSIM
TSEQ M TCONV
=
Where:
TSEQ = Total time to sample and convert multiple channels with sequential sampling.
TCONV
= Conversion Time (see Equation 16-2)
TSMP
= Sampling Time (see Equation 16-1)
M = Number of channels selected by the CHPS<1:0> bits.
(if M > 1)
TSEQ TSMP TCONV
+= (if M = 1)
When TSMP < TCONV,
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-26 © 2006-2012 Microchip Technology Inc.
Figure 16-11: 2-Channel Sequential Sampling (ASAM = 1)
Figure 16-12: 4-Channel Sequential Sampling
Sample 1
Sample 1
CH0
CH1
Convert 1
Convert 1
SOC
Trigger
Sample 2
Sample 2
Convert 2
Convert 2
Sample/Convert Sequence 1 Sample/Convert Sequence 2
Sample 2 Sample 3
1 2 4
35
Note 1: CH0-CH1 Input multiplexer selects analog input for sampling. The selected analog input is connected to
the sample capacitor.
2: On SOC Trigger, CH0 sample capacitor is disconnected from the multiplexer to hold the input voltage
constant during conversion. The analog value captured in CH0 is converted to equivalent digital bits.
3: The CH0 multiplexer output is connected to sample capacitor after conversion. CH1 sample capacitor is
disconnected from the multiplexer to hold the input voltage constant during conversion. The analog value
captured in CH1 is converted to equivalent digital bits.
4: The CH1 multiplexer output is connected to sample capacitor after conversion. CH0-CH1 Input multiplexer
selects next analog input for sampling.
5: On SOC Trigger, CH0 sample capacitor is disconnected from the multiplexer to hold the input voltage
constant during conversion. The analog value captured in CH0 is converted to equivalent digital bits.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-27
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.4 ADC CONFIGURATION
16.4.1 ADC Operational Mode Selection
The 12-bit Operation Mode bit (AD12B) in the ADC Control Register 1 (ADxCON1<10>) allows
the ADC module to function as either a 10-bit, 4-channel ADC (default configuration) or a 12-bit,
single-channel ADC. Table 16-5 lists the options selected by different bit settings.
Table 16-5: ADC Operational Mode
16.4.2 ADC Channel Selection
In 10-bit mode (AD12B = 0), the user application can select 1-channel (CH0), 2-channel (CH0,
CH1) or 4-channel mode (CH0-CH3) using the Channel Select bits (CHPS<1:0>) in the ADC
Control register (ADxCON2<9:8>). In 12-bit mode, the user application can only use CH0.
Table 16-6 lists the number of channels selected for the different bit settings.
Table 16-6: 10-bit ADC Channel Selection
16.4.3 Voltage Reference Selection
The voltage references for analog-to-digital conversions are selected using the Voltage
Reference Configuration bits (VCFG<2:0>) in the ADC Control register (ADxCON2<15:13>). The
voltage reference high (VREFH) and the voltage reference low (VREFL) to the ADC module can be
supplied from the internal AVDD and AVSS voltage rails or the external VREF+ and VREF- input
pins. The external voltage reference pins can be shared with the AN0 and AN1 inputs on low pin
count devices. The ADC module can still perform conversions on these pins when they are
shared with the VREF+ and VREF- input pins. The voltages applied to the external reference pins
must meet certain specifications. For details, refer to the “Electrical Characteristics chapter
of the specific device data sheet. In addition, refer to the “Pin Diagrams” section in the specific
device data sheet for the availability of the VREF+ and VREF- pins.
Table 16-7: Voltage Reference Selection
Note 1: The ADC module must be disabled before the AD12B bit is modified.
2: 12-bit mode is not available on all devices. Refer to the “Analog-to-Digital
Converter (ADC)” chapter in the specific device data sheet for availability.
AD12B Channel Selection
010-bit, 4-channel ADC
112-bit, single-channel ADC
CHPS<1:0> Channel Selection
00 CH0
01 Dual Channel (CH0, CH1)
1x Multi-Channel (CH0-CH3)
VCFG<2:0> VREFH VREFL
000 AV AVDD SS
001 VREF+ AVSS
010 AVDD VREF-
011 VREF+ VREF-
1xx AVDD AVSS
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-28 © 2006-2012 Microchip Technology Inc.
16.4.4 ADC Clock Selection
The ADC module can be clocked from the instruction cycle clock (TCY) or by using the dedicated
internal RC clock (see Figure 16-13). When using the instruction cycle clock, a clock divider
drives the instruction cycle clock and allows a lower frequency to be chosen. The clock divider is
controlled by the ADC Conversion Clock Select bits (ADCS<7:0>) in the ADC Control register
(ADxCON3<7:0>), which allows 64 settings, from 1:1 to 1:64, to be chosen.
For correct analog-to-digital conversion, the ADC Clock period (TAD) must be a minimum of
75 ns.
Equation 16-6 shows the ADC Clock period (TAD) as a function of the ADCS control bits and the
device instruction cycle clock period, TCY.
Equation 16-6: ADC Clock Period
The ADC module has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source is used when analog-to-digital conversions are
performed while the device is in the Sleep mode. The internal RC oscillator is selected by setting
the ADC Conversion Clock Source bit (ADRC) in ster 3 (ADxCON3<15>). the ADC Control Regi
When the ADRC bit is set, the ADCS<7:0> bits have no effect on the ADC operation.
Figure 16-13: ADC Clock Generation
16.4.5 Output Data Format Selection
Figure 16-14 illustrates the ADC result is available in four different numerical formats. The Data
Output Format bits (FORM<1:0>) in the ADC Control register (ADxCON1<9:8>), selects the
output data format. Table 16-8 lists the ADC output format for different bit settings.
Note: Refer to the “Electrical Characteristics” chapter in the specific device data sheet
for ADRC frequency specifications.
If ADRC = 0
ADC Clock Period (TAD) = TCY (ADCS + 1)
If ADRC = 1
ADC Clock Period (TAD) = TADRC
0
1
ADCS<7:0>
ADRC
ADC Clock (TAD)
TCY
ADC Internal RC
N
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-29
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Table 16-8: Voltage Reference Selection
Figure 16-14: ADC Output Format
FORM<1:0> Data Information Selection
11 Signed Fractional Format
10 Unsigned Fractional format
01 Signed Integer format
00 Unsigned Integer format
0000 0000 0000 0000 (0)
0000 0011 1111 1111 (1023)
0000 0010 0000 0000
(512)
1111 1110 0000 0000 (-512)
0000 0001 1111 1111 (511)
0000 0000 0000 0000 (0)
0000 0000 0000 0000 (0)
0000 0011 1111 1111 (4095)
0000 0010 0000 0000 (2048)
1111 1000 0000 0010 (-2046)
0000 0111 1111 1101 (2045)
0000 0000 0000 0000 (0)
10-bit ADC 12-bit ADC
FORM = 0b00
Unsigned
Integer
FORM = 0b01
Signed
Integer
0000 0000 0000 0000 (0)
1111 1111 1100 0000 (+0.999)
1000 0000 0000 0000 (0.5)
1000 0000 0000 0000 (-1)
0111 1111 1100 0000 (+0.999)
0000 0000 0000 0000 (0)
VREFH
VREFL
0000 0000 0000 0000 (0)
FORM = 0b10
Unsigned
Fraction (Q16)
FORM = 0b11
Signed
Fraction (Q15)
Input
0111 1111 1111 0000 (+0.999)
1000 0000 0000 0000 (-1)
VREFH
VREFL
1000 0000 0000 0000 (0.5)
Input
0000 0000 0000 0000 (0)
1111 1111 1111 0000 (+0.999)
VREFH
VREFL Input
VREFH
VREFL Input
VREFH
VREFL Input
VREFH
VREFL Input
VREFH
VREFL Input
VREFH
VREFL Input
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-30 © 2006-2012 Microchip Technology Inc.
16.4.6 Sample and Conversion Operation (SMPI) Bits
The function of the Samples Per Interrupt control bits (SMPI<3:0>) in the ADC Control Register
2 (ADxCON2<5:2>) for devices with DMA is completely different from the function of the
SMPI<3:0> bits for devices without DMA.
For devices without DMA, the SMPI<3:0> bits are referred to as the Number of Samples Per
Interrupt Select bits. For devices with DMA, the SMPI<3:0> bits are referred to as the Increment
Rate for DMA Address Select bit.
16.4.6.1 SMPI FOR DEVICES WITHOUT DMA
For devices without DMA, an interrupt can be generated at the end of each sample/convert
sequence or after multiple sample/convert sequences, as determined by the value of the
SMPI<3:0> bits. The number of sample/convert sequences between interrupts can vary between
1 and 16. The total number of conversion results between interrupts is the product of the number
of channels per sample created by the CHPS<1:0> bits and the value of the SMPI<3:0> bits. See
16.5 “ADC Interrupt Generation” for the SMPI values for various sampling modes.
16.4.6.2 SMPI FOR DEVICES WITH DMA
For devices with DMA, if multiple conversion results need to be buffered, DMA should be used
with the ADC module to store the conversion results in a DMA buffer. In this case, the SMPI<3:0>
bits are used to select how often the DMA RAM buffer pointer is incremented. The number of
increments of the DMA RAM buffer pointer should not exceed the DMA RAM buffer length per
input as specified by the DMABL<2:0> bits. An ADC interrupt is generated after completion of
every conversion, regardless of the SMPI<3:0> bits settings.
When single or dual or multiple channels are enabled in simultaneous or sequential sampling
modes (and CH0 channel scanning is disabled), the SMPI<3:0> bits are set to ‘0’, indicating the
DMA address pointer will increment every sample.
When all single or dual or multiple channels are enabled in simultaneous or sequential sampling
modes with Alternate Input Selection mode enabled (and CH0 channel scanning is disabled), set
SMPI<3:0> = 001 to allow two samples per DMA address point increment.
When channel scanning is used (and Alternate Input Selection mode is disabled), the SMPI<3:0>
bits should be set to the number of inputs being scanned minus one (i.e., SMPI<3:0> = N - 1).
16.4.7 Conversion Trigger Sources
It is often desirable to synchronize the end of sampling and the start of conversion with some
other time event. The ADC module can use one of the following sources as a conversion trigger:
External Interrupt Trigger (INT0 only)
Timer Interrupt Trigger
Motor Control PWM Special Event Trigger (dsPIC33F Motor Control Devices Only)
16.4.7.1 EXTERNAL INTERRUPT TRIGGER (INT0 ONLY)
When SSRC<2:0> = 001, the analog-to-digital conversion is triggered by an active transition on
the INT0 pin. The INT0 pin can be programmed for either a rising edge input or a falling edge
input.
16.4.7.2 TIMER INTERRUPT TRIGGER
This ADC module trigger mode is configured by setting SSRC<2:0> = 010. TMR3 (for ADC1)
and TMR5 (for ADC2) can be used to trigger the start of the analog-to-digital conversion when a
match occurs between the 16-bit Timer Count register (TMRx) and the 16-bit Timer Period
register (PRx). The 32-bit timer can also be used to trigger the start of the analog-to-digital
conversion. When SSRC<2:0> = 100, the timers are swapped (e.g., TMR5 is used with ADC1
and TMR3 is used with ADC2).
Note: If a manual conversion trigger is used and the number of samples per interrupt is
greater than the number of channels per sample, the SAMP bit (ADxCON1<1>)
must be manually cleared at suitable intervals in order to generate a sufficient
number of ADC conversions.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-31
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.4.7.3 MOTOR CONTROL PWM SPECIAL EVENT TRIGGER
(dsPIC33F MOTOR CONTROL DEVICES ONLY)
The PWM module has an event trigger that allows analog-to-digital conversions to be
synchronized to the PWM time base. When SSRC<2:0> = 011, the analog-to-digital sampling
and conversion times occur at any user programmable point within the PWM period. The Special
Event Trigger allows the user to minimize the delay between the time when the analog-to-digital
conversion results are acquired and the time when the duty cycle value is updated.
The application should set the ASAM bit in order to ensure that the ADC module has sampled
the input sufficiently before the next conversion trigger arrives.
16.4.8 Configuring Analog Port Pins
The Analog/Digital Pin Configuration register (ADxPCFGL) specifies the input condition of device
pins used as analog inputs. Along with the Data Direction register (TRISx) in the Parallel I/O Port
module, these registers control the operation of the ADC pins.
A pin is configured as an analog input when the corresponding PCFGn bit (ADxPCFGL<n>) is
clear. The ADxPCFGL register is cleared at Reset, causing the ADC input pins to be configured
for analog input by default at Reset.
When configured for analog input, the associated port I/O digital input buffer is disabled so that
it does not consume current.
The port pins that are desired as analog inputs must have their corresponding TRIS bit set,
specifying the port input. If the I/O pin associated with an analog-to-digital input is configured as
an output, the TRIS bit is cleared and the digital output level (VOH or VOL) of the port is converted.
After a device Reset, all TRIS bits are set.
A pin is configured as a digital I/O when the corresponding PCFGn bit is set. In this configuration,
the input to the analog multiplexer is connected to AVSS.
16.4.9 Enabling the ADC Module
When the ADON bit (ADxCON1<15>) is 1, the module is in active mode and is fully powered
and functional.
When ADON is 0’, the module is disabled. The digital and analog portions of the circuit are
turned off for maximum current savings.
To return to the active mode from the off mode, the user application must wait for the analog
stages to stabilize. For the stabilization time, refer to the “Electrical Characteristics” chapter
of the specific device data sheet.
Note 1: When the ADC Port register is read, any pin configured as an analog input reads
as a ‘0’.
2: Analog levels on any pin that is defined as a digital input may cause the input buffer
to consume current that is out of the device specification.
Note: The SSRC<2:0>, SIMSAM, ASAM, CHPS<1:0>, SMPI<3:0>, BUFM and ALTS bits,
as well as the ADCON3 and ADCSSL registers, should not be written to, while
ADON = 1. This would lead to indeterminate results.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-32 © 2006-2012 Microchip Technology Inc.
16.4.10 Turning the ADC Module Off
Clearing the ADON bit disables the ADC module (stops any scanning, sampling and conversion
processes). In this state, the ADC module still consumes some current. Setting the ADxMD bit in
the PMD register will disable the ADC module and will stop the ADC clock source, which reduces
device current consumption. Note that setting the ADxMD bit and then clearing the bit will reset
the ADC module registers to their default state. Additionally, any digital pins that share their
function with an ADC input pin revert to the analog function. While the ADxMD bit is set, these
pins will be set to digital function. In this case, the ADxPCFG bits will not have any effect.
Note: Clearing the ADON bit during a conversion will abort the current analog-to-digital
conversion. The ADC buffer will not be updated with the partially completed
conversion sample.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-33
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.5 ADC INTERRUPT GENERATION
With DMA enabled, the SMPI<3:0> bits (ADxCON2<5:2>) determine the number of
sample/conversion operations per channel (CH0/CH1/CH2/CH3) for every DMA
address/increment pointer.
The SMPI<3:0> bits have no effect when the ADC module is set up such that DMA buffers are
written in Conversion Order mode.
If DMA transfers are enabled, the SMPI<3:0> bits must be cleared, except when channel
scanning or alternate sampling is used. For more details on SMPI<3:0> setup requirements, see
16.7 “Specifying Conversion Results Buffering for Devices with DMA”.
When the SIMSAM bit (ADxCON1<3>) specifies sequential sampling, regardless of the number
of channels specified by the CHPS<1:0> bits (ADxCON2<9:8>), the ADC module samples once
for each conversion and data sample in the buffer. The value specified by the DMAxCNT register
for the DMA channel being used corresponds to the number of data samples in the buffer.
For devices with DMA, interrupts are generated after every conversion, which sets the DONE bit
since it reflects the interrupt flag (ADxIF) setting.
For devices without DMA, as conversions are completed, the ADC module writes the results of
the conversions into the analog-to-digital result buffer. The ADC result buffer is an array of
sixteen words, accessed through the SFR space. The user application may attempt to read each
analog-to-digital conversion result as it is generated. However, this might consume too much
CPU time. Generally, to simplify the code, the module fills the buffer with results and generates
an interrupt when the buffer is filled. The ADC module supports 16 result buffers. Therefore, the
maximum number of conversions per interrupt must not exceed 16.
The number of conversion per ADC interrupt depends on the following parameters, which can
vary from one to 16 conversions per interrupt.
Number of S&H channels selected
Sequential or Simultaneous Sampling
Samples Convert Sequences Per Interrupt bits (SMPI<3:0>) settings
Table 16-9 lists the number of conversions per ADC interrupt for different configuration modes.
Table 16-9: Samples Per Interrupt in Alternate Sampling Mode
The DONE bit (ADxCON1<0>) is set when an ADC interrupt is generated to indicate completion
of a required sample/conversion sequence. This bit is automatically cleared by the hardware at
the beginning of the next sample/conversion sequence.
On devices without DMA, interrupt generation is based on the SMPI<3:0> and CHPS bits, so the
DONE bit is not set after every conversion, but is set when the Interrupt Flag (ADxIF) is set.
CHPS<1:0> SIMSAM SMPI<3:0> Conversions/
Interrupt Description
00 x N-1 N 1-Channel mode
01 0 N-1 N 2-Channel Sequential Sampling mode
1x 0 N-1 N 4-Channel Sequential Sampling mode
01 1 N-1 2 • N 2-Channel Simultaneous Sampling mode
1x 1 N-1 4 • N 4-Channel Simultaneous Sampling mode
Note 1: In 2-channel Simultaneous Sampling mode, SMPI<3:0> bit settings must be less
than eight.
2: In 4-channel Simultaneous Sampling mode, SMPI<3:0> bit settings must be less
than four.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-34 © 2006-2012 Microchip Technology Inc.
16.5.1 Buffer Fill Mode
When the Buffer Fill Mode bit (BUFM) in the ADC Control Register 2 (ADxCON2<1>) is 1’, the
16-word results buffer is split into two 8-word groups: a lower group (ADC1BUF0 through
ADC1BUF7) and an upper group (ADC1BUF8 through ADC1BUFF). The 8-word buffers
alternately receive the conversion results after each ADC interrupt event. When the BUFM bit is
set, each buffer size is equal to eight. Therefore, the maximum number of conversions per
interrupt must not exceed eight.
When the BUFM bit is 0’, the complete 16-word buffer is used for all conversion sequences. The
decision to use the split buffer feature depends on the time available to move the buffer contents,
after the interrupt, as determined by the application.
If the application can quickly unload a full buffer within the time taken to sample and convert one
channel, the BUFM bit can be 0’, and up to 16 conversions may be done per interrupt. The
application has one sample/convert time before the first buffer location is overwritten. If the
processor cannot unload the buffer within the sample and conversion time, the BUFM bit should
be ‘1’. For example, if an ADC interrupt is generated every eight conversions, the processor has
the entire time between interrupts to move the eight conversions out of the buffer.
16.5.2 Buffer Fill Status
When the conversion result buffer is split using the BUFM control bit, the BUFS Status bit
(ADxCON2<7>) indicates, half of the buffer that the ADC module is currently writing. If BUFS = 0,
the ADC module is filling the lower group, and the user application should read conversion values
from the upper group. If BUFS = 1, the situation is reversed, and the user application should read
conversion values from the lower group.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-35
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
16.6 ANALOG INPUT SELECTION FOR CONVERSION
The ADC module provides a flexible mechanism to select analog inputs for conversion:
Fixed input selection
Alternate input selection
Channel scanning (CH0 only)
16.6.1 Fixed Input Selection
The 10-bit ADC configuration can use up to four S&H channels, designated CH0-CH3, whereas
the 12-bit ADC configuration can use only one S&H channel, CH0. The S&H channels are
connected to the analog input pins through the analog multiplexer.
When ALTS = 0, the CH0SA<4:0>, CH0NA, CH123SA and CH123NA<1:0> bits select the
analog inputs.
Table 16-10: Analog Input Selection
All four channels can be enabled in simultaneous or sequential sampling modes by configuring
the CHPS bit and the SIMSAM bit.
For devices with DMA, the SM ’, indicating the DMA address pointer willPI<3:0> bits are set to ‘0
increment every sample.
Example 16-3 shows the code sequence to set up ADC inputs for a 4-channel ADC
configuration.
Example 16-3: Code Sequence to Set Up ADC Inputs
MUXA
Control bits Analog Inputs
CH0 +ve CH0SA<4:0> AN0 to AN31
-ve CH0NA VREF-, AN1
CH1 +ve CH123SA AN0, AN3
-ve CH123NA<1:0> AN6, AN9, VREF-
CH2 +ve CH123SA AN1, AN4
-ve CH123NA<1:0> AN7, AN10, VREF-
CH3 +ve CH123SA AN2, AN5
-ve CH123NA<1:0> AN8, AN11, VREF-
Note: Not all inputs are present on all devices.
// Initialize MUXA Input Selection
AD1CHS0bits.CH0SA = 3; // Select AN3 for CH0 +ve input
AD1CHS0bits.CH0NA = 0; // Select VREF- for CH0 -ve input
AD1CHS123bits.CH123SA=0; // Select AN0 for CH1 +ve input
// Select AN1 for CH2+ve input
// Select AN2 for CH3 +ve input
AD1CHS123bits.CH124NA=0; // Select VREF- for CH1/CH2/CH3 -ve inputs
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-36 © 2006-2012 Microchip Technology Inc.
16.6.2 Alternate Input Selection Mode
In an Alternate Input Selection mode, the MUXA and MUXB control bits select the channel for
conversion. The ADC completes one sweep using the MUXA selection, and then another sweep
using the MUXB selection, and then another sweep using the MUXA selection, and so on. The
Alternate Input Selection mode is enabled by setting the Alternate Sample bit (ALTS) in the ADC
Control Register 2 (ADxCON2<0>).
The analog input multiplexer is controlled by the AD1CHS123 and AD1CHS0 registers. There
are two sets of control bits designated as MUXA (CHySA/CHyNA) and MUXB (CHySB/CHyNB)
to select a particular input source for conversion. The MUXB control bits are used in Alternate
Input Selection mode.
Table 16-11: Analog Input Selection
For Alternate Input Selection mode in devices without DMA, an ADC interrupt must be generated
after an even number of sample/conversion sequences by programming the Samples Convert
Sequences Per Interrupt bits (SMPI<3:0>). Table 16-12 lists the valid SMPI values for Alternate
Input Selection mode in different ADC configurations.
Table 16-12: Valid SMPI Values for Alternate Input Selection Mode
Example 16-4 shows the code sequence to set up the ADC module for Alternate Input Selection
mode for devices without DMA in the 4-Channel Simultaneous Sampling configuration.
Figure 16-15 illustrates the ADC module operation sequence.
MUXA MUXB
Control bits Analog Inputs Control bits Analog Inputs
CH0 +ve CH0SA<4:0> AN0 to AN31 CH0SB<4:0> AN0 to AN31
-ve CH0NA VREF-, AN1 CH0NB VREF-, AN1
CH1 +ve CH123SA AN0, AN3 CH123SB AN0, AN3
-ve CH123NA<1:0> AN6, AN9, VREF REF- CH123NB<1:0> AN6, AN9, V -
CH2 +ve CH123SA AN1, AN4 CH123SB AN1, AN4
-ve CH123NA<1:0> AN7, AN10, VREF- CH123NB<1:0> AN7, AN10, VREF-
CH3 +ve CH123SA AN2, AN5 CH123SB AN2, AN5
-ve CH123NA<1:0> AN8, AN11, VREF- CH123NB<1:0> AN8, AN11, VREF-
Note: Not all inputs are present on all devices.
CHPS<1:0> SIMSAM SMPI<3:0>
(Decimal)
Conversions/
Interrupt Description
00 x 1,3,5,7,9,11,13,15 2,4,6,8,10,12,14,16 1-Channel mode
01 0 3,7,11,15 4,8,12,16 2-Channel Sequential
Sampling mode
1x 0 7,15 8,16 4-Channel Sequential
Sampling mode
01 1 1,3,5,7 4,8,12,16 2-Channel Simultaneous
Sampling mode
1x 1 1,3 8,16 4-Channel Simultaneous
Sampling mode
Note: On ADC Interrupt, the ADC internal logic is initialized to restart the conversion
sequence from the beginning.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-37
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Example 16-4: Code Sequence to Set Up ADC for Alternate Input Selection Mode for 4-Channel
Simultaneous Sampling (Devices without DMA)
Figure 16-15: Alternate Input Selection in 4-Channel Simultaneous Sampling Configuration (Devices without
DMA)
AD1CON1bits.AD12B = 0; // Select 10-bit mode
AD1CON2bits.CHPS = 3; // Select 4-channel mode
AD1CON1bits.SIMSAM = 1; // Enable Simultaneous Sampling
AD1CON2bits.ALTS = 1; // Enable Alternate Input Selection
AD1CON2bits.SMPI = 1; // Select 8 conversion between interrupt
AD1CON1bits.ASAM = 1; // Enable Automatic Sampling
AD1CON1bits.SSRC = 2; // Timer3 generates SOC trigger
// Initialize MUXA Input Selection
AD1CHS0bits.CH0SA = 6; // Select AN6 for CH0 +ve input
AD1CHS0bits.CH0NA = 0; // Select VREF- for CH0 -ve input
AD1CHS123bits.CH123SA = 0; // Select CH1 +ve = AN0, CH2 +ve = AN1, CH3 +ve = AN2
AD1CHS123bits.CH123NA = 0; // Select VREF- for CH1/CH2/CH3 -ve inputs
// Initialize MUXB Input Selection
AD1CHS0bits.CH0SB = 7; // Select AN7 for CH0 +ve input
AD1CHS0bits.CH0NB = 0; // Select VREF- for CH0 -ve input
AD1CHS123bits.CH123SB = 1; // Select CH1 +ve = AN3, CH2 +ve = AN4, CH3 +ve = AN5
AD1CHS123bits.CH124NB = 0; // Select VREF- for CH1/CH2/CH3 -ve inputs
Sample
(AN6)
Sample
(AN0)
CH0
CH1
Sample
(AN1)
Sample
(AN2)
CH2
CH3
Convert
(AN6)
Convert
(AN0)
Convert
(AN1)
SOC
Trigger
Convert
(AN2)
Sample
(AN7)
Sample
(AN3)
Sample
(AN4)
Sample
(AN5)
Convert
(AN7)
Convert
(AN3)
Convert
(AN4)
Convert
(AN5)
Sample/Convert Sequence 1 Sample/Convert Sequence 2
Sample
(AN6)
Sample
(AN0)
Sample
(AN1)
Sample
(AN2)
235
ADC
Interrupt
14
AN6
AN0
AN1
AN2
AN7
AN3
AN4
AN5
ADC1BUF0
ADC1BUF1
ADC1BUF7
Note 1: CH0-CH3 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The selected analog input
is connected to the sample capacitor.
2: On SOC Trigger, CH0-CH3 sample capacitor is disconnected from the multiplexer to simultaneously sample the analog inputs. The
analog value captured in CH0/CH1/CH2/CH3 is converted sequentially to equivalent digital counts.
3: CH0-CH3 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
4: On SOC Trigger, CH0-CH3 sample capacitor is disconnected from the multiplexer to simultaneously sample the analog inputs. The
analog value captured in CH0/CH1/CH2/CH3 is converted sequentially to equivalent digital counts.
5: ADC Interrupt is generated after converting 8 samples. CH0-CH3 Input multiplexer selects analog input for sampling using MUXA
control bits (CHySA/CHyNA). The selected analog input is connected to the sample capacitor.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-38 © 2006-2012 Microchip Technology Inc.
Example 16-5 shows the code sequence to set up the ADC module for Alternate Input Selection
mode in a 2-channel sequential sampling configuration for devices without DMA.
Example 16-5: Code Sequence to Set Up ADC for Alternate Input Selection for 2-Channel Sequential
Sampling (Devices without DMA)
Figure 16-16: Alternate Input Selection in 2-Channel Sequential Sampling Configuration (Devices without
DMA)
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-39
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
For devices with DMA, when Alternate Input Selection mode is enabled, set SMPI<3:0> = 001
to allow two samples per DMA address point increment.
Figure 16-17: Alternate Input Selection in 4-Channel Simultaneous Sampling Configuration (Devices with
DMA)
Sample
(AN6)
Sample
(AN0)
CH0
CH1
Sample
(AN1)
Sample
(AN2)
CH2
CH3
Convert
(AN6)
Convert
(AN0)
Convert
(AN1)
SOC
Trigger
Convert
(AN2)
Sample
(AN7)
Sample
(AN3)
Sample
(AN4)
Sample
(AN5)
Convert
(AN7)
Convert
(AN3)
Convert
(AN4)
Convert
(AN5)
Sample/Convert Sequence 1 Sample/Convert Sequence 2
Sample
(AN6)
Sample
(AN0)
Sample
(AN1)
Sample
(AN2)
2 3 5
ADC
Interrupt
1 4
Note 1: CH0-CH3 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The selected analog input
is connected to the sample capacitor.
2: On SOC Trigger, CH0-CH4 sample capacitor is disconnected from the multiplexer to simultaneously sample the analog inputs. The
analog value captured in CH0/CH1/CH2/CH3 is converted sequentially to equivalent digital counts.
3: CH0-CH3 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
4: On SOC Trigger, CH0-CH3 sample capacitor is disconnected from the multiplexer to simultaneously sample the analog inputs. The
analog value captured in CH0/CH1/CH2/CH3 is converted sequentially to equivalent digital counts.
5: ADC Interrupt is generated after converting every sample. CH0-CH3 Input multiplexer selects analog input for sampling using
MUXA control bits (CHySA/CHyNA). The selected analog input is connected to the sample capacitor.
5 5 5 5 5 5
AN0 Sample 1
AN1 Sample 1
AN2 Sample 1
AN3 Sample 1
AN6 Sample 1
AN4 Sample 1
AN5 Sample 1
AN7 Sample 1
AN0
Block
AN1
Block
AN2
Block
AN3
Block
AN4
Block
AN5
Block
AN6
Block
AN7
Block
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-40 © 2006-2012 Microchip Technology Inc.
Figure 16-18: Alternate Input Selection in 2-Channel Sequential Sampling Configuration (Devices with DMA)
16.6.3 Channel Scanning
The ADC module supports the Channel Scan mode using CH0 (S&H channel 0’). The number
of inputs scanned is software selectable. Any subset of the analog inputs from AN0 to AN31
(AN0-AN12 for devices without DMA) can be selected for conversion. The selected inputs are
converted in ascending order. For example, if the input selection includes AN4, AN1 and AN3,
the conversion sequence is AN1, AN3 and AN4. The conversion sequence selection is made by
programming the Channel Select register (AD1CSSL). A logic ‘1’ in the Channel Select register
marks the associated analog input channel for inclusion in the conversion sequence. The
Channel Scanning mode is enabled by setting the Channel Scan bit (CSCNA) in the ADC Control
Register 2 (ADxCON2<10>). In Channel Scan mode, MUXA software control is ignored and the
ADC module sequences through the enabled channels.
In devices without DMA, for every sample/convert sequence, one analog input is scanned. The
ADC interrupt must be generated after all selected channels are scanned. If “N” inputs are
enabled for channel scan, an interrupt must be generated after N” sample/convert sequence.
Table 16-13 lists the SMPI values to scan “N” analog inputs using CH0 in different ADC
configurations.
Note: A maximum of 16 ADC inputs (any) can be configured to be scanned at a time.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-41
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
Table 16-13: Conversions Per Interrupt in Channel Scan Mode (Devices without DMA)
Example 16-6 shows the code sequence to scan four analog inputs using CH0 in devices without
DMA. Figure 16-19 illustrates the ADC operation sequence.
Example 16-6: Code sequence to Scan four Analog Inputs Using CH0
(Devices without DMA and 10-bit/12-bit ADC)
Figure 16-19: Scan Four Analog Inputs Using CH0 (Devices without DMA)
Example 16-7 shows the code sequence to scan two analog inputs using CH0 in a 2-channel
alternate input selection configuration for devices without DMA. Figure 16-20 illustrates the ADC
operation sequence.
CHPS<1:0> SIMSAM SMPI<3:0>
(Decimal)
Conversions/
Interrupt
Description
00 x N-1 N 1-Channel mode
01 0 2N-1 2N 2-Channel Sequential Sampling
mode
1x 0 4N-1 4N 4-Channel Sequential Sampling
mode
01 1 N-1 2N 2-Channel Simultaneous Sampling
mode
1x 1 N-1 4N 4-Channel Simultaneous Sampling
mode
Note: On ADC Interrupt, the ADC internal logic is initialized to restart the conversion
sequence from the beginning.
AD1CON1bits.AD12B=1; // Select 12-bit mode, 1-channel mode
AD1CON2bits.SMPI = 3; // Select 4 conversions between interrupt
AD1CHS0bits.ASAM = 1; // Enable Automatic Sampling
AD1CON2bits.CSCNA = 1; // Enable Channel Scanning
// Initialize Channel Scan Selection
AD1CSSLbits.CSS2=1; // Enable AN2 for scan
AD1CSSLbits.CSS3=1; // Enable AN3 for scan
AD1CSSLbits.CSS5=1; // Enable AN5 for scan
AD1CSSLbits.CSS6=1; // Enable AN6 for scan
Sample
(AN2)
CH0 Convert
(AN2)
SOC
Trigger
Sample
(AN3)
Convert
(AN3)
Sample
(AN5)
Convert
(AN5)
Sample
(AN6)
Convert
(AN6)
ADC
Interrupt
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-42 © 2006-2012 Microchip Technology Inc.
Example 16-7: Code Sequence for Channel Scan with Alternate Input Selection (Devices without DMA)
Figure 16-20: Channel Scan with Alternate Input Selection (Devices without DMA)
Sample
(AN2)
Sample
(AN0)
CH0
CH1
Convert
(AN2)
Convert
(AN0)
SOC
Trigger
Sample
(AN8)
Sample
(AN3)
Convert
(AN8)
Convert
(AN3)
Sample
(AN8)
Sample
(AN3)
Sample
(AN3)
Sample
(AN0)
Convert
(AN3)
Convert
(AN0)
Sample
(AN8)
Sample
(AN3)
Convert
(AN8)
Convert
(AN3)
Sample
(AN8)
ADC
Trigger
Sample/Convert Sequence 1 Sample/Convert Sequence 2 Sample/Convert Sequence 3 Sample/Convert Sequence 4
123456 7 8 9
Note 1: CH0 Input multiplexer selects analog input for sampling using internally generated control bits (from Channel Scan logic) instead
of MUXA control bits. CH1 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The
selected analog input is connected to the sample capacitor.
2: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
3: CH0-CH1 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
4: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
5: CH0 Input multiplexer selects analog input for sampling using internally generated control bits (from Channel Scan logic) instead
of MUXA control bits. CH1 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The
selected analog input is connected to the sample capacitor.
6: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
7: CH0-CH1 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
8: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
9: ADC Interrupt is generated after converting eight samples.
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-43
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
For devices with DMA, when channel scanning is used and only CH0 is active (ALTS = 0), the
SMPI<3:0> bits should be set to the number of inputs being scanned minus one (i.e.,
SMPI<3:0> = N - 1).
Figure 16-21: Scan Four Analog Inputs Using CH0 (Devices with DMA)
Figure 16-22: Channel Scan with Alternate Input Selection (Devices with DMA)
Sample
(AN2)
CH0 Convert
(AN2)
SOC
Trigger
Sample
(AN3)
Convert
(AN3)
Sample
(AN5)
Convert
(AN5)
Sample
(AN6)
Convert
(AN6)
ADC
Interrupt
Sample
(AN2)
Sample
(AN0)
CH0
CH1
Convert
(AN2)
Convert
(AN0)
SOC
Trigger
Sample
(AN8)
Sample
(AN3)
Convert
(AN8)
Convert
(AN3)
Sample
(AN8)
Sample
(AN3)
Sample
(AN3)
Sample
(AN0)
Convert
(AN3)
Convert
(AN0)
Sample
(AN8)
Sample
(AN3)
Convert
(AN8)
Convert
(AN3)
Sample
(AN8)
ADC
Trigger
Sample/Convert Sequence 1 Sample/Convert Sequence 2 Sample/Convert Sequence 3 Sample/Convert Sequence 4
1 2 3 4 5 6 7 8 9
Note 1: CH0 Input multiplexer selects analog input for sampling using internally generated control bits (from Channel Scan logic) instead
of MUXA control bits. CH1 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The
selected analog input is connected to the sample capacitor.
2: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
3: CH0-CH1 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
4: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
5: CH0 Input multiplexer selects analog input for sampling using internally generated control bits (from Channel Scan logic) instead
of MUXA control bits. CH1 Input multiplexer selects analog input for sampling using MUXA control bits (CHySA/CHyNA). The
selected analog input is connected to the sample capacitor.
6: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
7: CH0-CH1 Input multiplexer selects analog input for sampling using MUXB control bits (CHySB/CHyNB). The selected analog input
is connected to the sample capacitor.
8: On SOC Trigger, CH0-CH1 inputs are sequentially sampled and converted to equivalent digital counts.
9: ADC Interrupt is generated after every conversion.
9
9
9
9
9
9
9
9
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-44 © 2006-2012 Microchip Technology Inc.
16.7 SPECIFYING CONVERSION RESULTS BUFFERING FOR DEVICES WITH
DMA
The ADC module contains a single-word, read-only, dual-port register (ADCxBUF0), which
stores the analog-to-digital conversion result. If more than one conversion result needs to be
buffered before triggering an interrupt, DMA data transfers can be used. Both ADC channels
(ADC1 and ADC2) can trigger a DMA data transfer. Depending on which ADC channel is
selected as the DMA IRQ source, a DMA transfer occurs when the ADC Conversion Complete
Interrupt Flag Status bit (AD1IF or AD2IF) in the Interrupt Flag Status Register (IFS0 or IFS1,
respectively) in the Interrupt Module gets set as a result of a sample conversion sequence.
The result of every analog-to-digital conversion is stored in the ADCxBUF0 register. If a DMA
channel is not enabled for the ADC module, each result should be read by the user application
before it gets overwritten by the next conversion result. However, if DMA is enabled, multiple con-
version results can be automatically transferred from ADCxBUF0 to a user-defined buffer in the
DMA RAM area. Thus, the application can process several conversion results with minimal soft-
ware overhead.
The DMA Buffer Build Mode bit (ADDMABM) in ADCx Control Register 1 (ADxCON1<12>) deter-
mines how the conversion results are filled in the DMA RAM buffer area being used for the ADC.
If this bit is set (ADDMABM = 1), DMA buffers are written in the order of conversion. The ADC
module provides an address to the DMA channel that is the same as the address used for the
non-DMA stand-alone buffer. If the ADDMABM bit is cleared, then DMA buffers are written in
Scatter/Gather mode. The ADC module provides a Scatter/Gather address to the DMA channel,
based on the index of the analog input and the size of the DMA buffer.
When the SIMSAM bit specifies simultaneous sampling, the number of data samples in the buffer
is related to the CHPS<1:0> bits. Algorithmically, the channels per sample (CH/S) times the num-
ber of samples results in the number of data sample entries in the buffer. To avoid loss of data in
the buffer due to overruns, the DMAxCNT register must be set to the desired buffer size.
When the ADC module is simultaneously sampling two or more ADC channels and CH0 is in
channel scanning mode, there is a limit of 16 conversions, after which time the ADC module
restarts conversion from the first ADC input in CH0. When operating the ADC module in this
mode, the DMAxCNT register must be set to 15 to avoid data loss due to buffer overrun.
Disabling the ADC interrupt is not done with the SMPI<3:0> bits. To disable the interrupt, clear
the ADxIE analog module interrupt enable bit.
16.7.1 Using DMA in the Scatter/Gather Mode
When the ADDMABM bit is 0’, the Scatter/Gather mode is enabled. In this mode, the DMA chan-
nel must be configured for Peripheral Indirect Addressing. The DMA buffer is divided into con-
secutive memory blocks corresponding to all available analog inputs (out of AN0 - AN31). Each
conversion result for a particular analog input is automatically transferred by the ADC module to
the corresponding block within the user-defined DMA buffer area. Successive samples for the
same analog input are stored in sequence within the block assigned to that input.
The number of samples that need to be stored in the DMA buffer for each analog input is
specified by the DMABL<2:0> bits (ADxCON4<2:0>).
The buffer locations within each block are accessed by the ADC module using an internal pointer,
which is initialized to 0when the ADC module is enabled. When this internal pointer reaches
the value defined by the DMABL<2:0> bits, it gets reset to 0’. This ensures that conversion
results of one analog input do not corrupt the conversion results of other analog inputs. The rate
at which this internal pointer is incremented when data is written to the DMA buffer is specified
by the SMPI<3:0> bits.
Note: For information about how to configure a DMA channel to transfer data from the
ADC buffer and define a corresponding DMA buffer area from where the data can
be accessed by the application, please refer to Section 22. “Direct Memory
Access (DMA)” (DS70182). For specific information about the Interrupt registers,
please refer to Section 6. “Interrupts” (DS70184).
© 2006-2012 Microchip Technology Inc. DS70183D-page 16-45
Section 16. Analog-to-Digital Converter (ADC)
Analog-to-Digital
Converter (ADC)
16
When no channel scanning or alternate sampling is required, SMPI<3:0> should be cleared,
implying that the pointer will increment on every sample per channel. Thus, it is theoretically pos-
sible to use every location in the DMA buffer for the blocks assigned to the analog inputs being
sampled.
In the example illustrated in Figure 16-23, it can be observed that the conversion results for the
AN0, AN1 and AN2 inputs are stored in sequence, leaving no unused locations in their
corresponding memory blocks. However, for the four analog inputs (AN4, AN5, AN6 and AN7)
that are scanned by CH0, the first location in the AN5 block, the first two locations in the AN6
block and the first three locations in the AN7 block are unused, resulting in a relatively inefficient
arrangement of data in the DMA buffer.
When scanning is used, and no simultaneous sampling is performed (SIMSAM = 0), SMPI<3:0>
should be set to one less than the number of inputs being scanned. For example, if CHPS<1:0> = 00
(only one S&H channel is used), and AD1CSSL = 0xFFFF, indicating that AN0-AN15 are being
scanned, then set SMPI<3:0> = 1111 so that the internal pointer is incremented only after every
sixteenth sample/conversion sequence. This avoids unused locations in the blocks corresponding to
the analog inputs being scanned.
Similarly, if ALTS = 1, indicating that alternating analog input selections are used, then
SMPI<3:0> is set to 0001’, thereby incrementing the internal pointer after every second sample.
Note: The ADC module does not perform limit checks on the generated buffer addresses.
For example, you must ensure that the Least Significant bits (LSbs) of the DMAx-
STA or DMAxSTB register used are indeed ‘0’. Also, the number of potential analog
inputs multiplied by the buffer size specified by DMABL<2:0> must not exceed the
total length of the DMA buffer.
dsPIC33F/PIC24H Family Reference Manual
DS70183D-page 16-46 © 2006-2012 Microchip Technology Inc.
Figure 16-23: DMA Buffer in Scatter/Gather Mode
DMAxSTA AN0 – SAMPLE 1
AN0 – SAMPLE 2
AN0 – SAMPLE 3
AN0 – SAMPLE 4
AN0 – SAMPLE 5
AN0 – SAMPLE 6
AN0 – SAMPLE 7
AN0 – SAMPLE 8
AN1 – SAMPLE 1
AN1 – SAMPLE 2
AN1 – SAMPLE 3
AN1 – SAMPLE 4
AN1 – SAMPLE 5
AN1 – SAMPLE 6
AN1 – SAMPLE 7
AN1 – SAMPLE 8
AN2 – SAMPLE 1
AN2 – SAMPLE 2
AN2 – SAMPLE 3
AN2 – SAMPLE 4
AN2 – SAMPLE 5
AN2 – SAMPLE 6
AN2 – SAMPLE 7
AN2 – SAMPLE 8
AN4 – SAMPLE 1
AN4 – SAMPLE 5
AN5 – SAMPLE 2
AN5 – SAMPLE 6
AN6 – SAMPLE 3
AN6 – SAMPLE 7
AN7 – SAMPLE 4
AN7 – SAMPLE 8
AN0 BLOCK
AN1 BLOCK
AN2 BLOCK
AN3 BLOCK
AN4 BLOCK
AN5 BLOCK
AN6 BLOCK
AN7 BLOCK
AN31 BLOCK
|
|
|
{
{
{
{
{
{
{
Unused Buffer Locations
Unused Buffer Locations
Unused Buffer Locations
Unused Buffer Locations
Unused Buffer Locations
Unused Buffer Locations
Unused Buffer Locations
{
{
{
{
{
{
{
{
{


Product specificaties

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Categorie: Niet gecategoriseerd
Model: dsPIC33FJ64MC508

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