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© 2010-2011 Microchip Technology Inc. DS70645C-page 14-1
High-Speed PWM
14
Section 14. High-Speed PWM
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction .................................................................................................................. 14-2
14.2 Features....................................................................................................................... 14-2
14.3 Control Registers ......................................................................................................... 14-3
14.4 Architecture Overview................................................................................................ 14-24
14.5 Module Description .................................................................................................... 14-27
14.6 PWM Operating Modes.............................................................................................. 14-33
14.7 PWM Generator......................................................................................................... 14-71
14.8 PWM Trigger.............................................................................................................. 14-87
14.9 PWM Interrupts.......................................................................................................... 14-98
14.10 PWM Fault Pins ......................................................................................................... 14-99
14.11 Special Features ...................................................................................................... 14-105
14.12 PWM Output Pin Control...........................................................................................14-111
14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113
14.14 Power-Saving Modes............................................................................................... 14-114
14.15 External Control of Individual Time Base(s)............................................................. 14-114
14.16 Application Information ............................................................................................ 14-115
14.17 Register Map............................................................................................................ 14-126
14.18 Related Application Notes........................................................................................ 14-127
14.19 Revision History ....................................................................................................... 14-128
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-2 © 2010-2011 Microchip Technology Inc.
14.1 INTRODUCTION
This section describes the High-Speed Pulse-Width Modulator (PWM) module and its
associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E
device family supports a wide variety of PWM modes and is ideal for power
conversion/motor control applications. Some of the common applications include:
AC-to-DC converters
DC-to-DC converters
AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.
• Inverters
Battery chargers
Digital lighting
Uninterrupted Power Supply (UPS)
Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)
14.2 FEATURES
The High-Speed PWM module consists of the following major features:
Up to seven PWM generators, each with an individual time base
Two PWM outputs per PWM generator
Individual period and duty cycle for each PWM output
Duty cycle, dead time, phase shift and frequency resolution equal to the system clock
source (TOSC)
Independent fault and current-limit inputs for up to 14 PWM outputs
Redundant Output mode
Independent Output mode (this feature is not available on all devices)
Push-Pull Output mode
Complementary Output mode
Center-Aligned PWM mode
Output override control
Special Event Trigger
PWM capture feature
Prescaler for input clock
ADC triggering with PWM
Independent PWM frequency, duty cycle and phase shift changes
Leading-Edge Blanking (LEB) functionality
Dead time compensation
Output clock chopping
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-3
Section 14. High-Speed PWM
High-Speed PWM
14
14.3 CONTROL REGISTERS
The following registers control the operation of the High-Speed PWM module:
PTCON: PWM Time Base Control Register
- Enables or disables the High-Speed PWM module
- Sets the Special Event Trigger for the ADC
- Enables or disables immediate period updates
- Selects the synchronizing source for the master time base
- Specifies synchronization settings
PTCON2: PWM Clock Divider Select Register 2
Provides the clock prescaler to the PWM master time base
PTPER: Primary Master Time Base Period Register
Provides the PWM time period value
STCON: PWM Secondary Master Time Base Control Registe (1)
- Enables or disables immediate period updates based on the secondary master time base
- Selects the synchronization source for the secondary master time base
- Specifies the synchronization setting for secondary master time base control
STCON2: PWM Secondary Clock Divider Select Register 2(1)
Provides the clock prescaler to the PWM secondary master time base
STPER: Secondary Master Time Base Period Register(1)
Provides the secondary master time base period value
MDC: PWM Master Duty Cycle Register
Provides the PWM master duty cycle value
SEVTCMP: PWM Special Event Compare Register
Provides the compare value that is used to trigger the ADC module
SSEVTCMP: PWM Secondary Special Event Compare Register(1)
Provides the compare value that is used to trigger the ADC module based on the
secondary master time base
CHOP: PWM Chop Clock Generator Register
- Provides the chop clock frequency
- Enables or disables the chop clock generator
PWMKEY: PWM Unlock Register(1)
Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers
PWMCONx: PWM Control Register
- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt
- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger
interrupt
- Selects the type of time base (master time base or independent time base)
- Selects the type of duty cycle (master duty cycle or independent duty cycle)
- Controls Dead Time mode
- Enables or disables Center-Aligned mode
- Controls the external PWM Reset operation
- Enables or disables immediate updates of the duty cycle, phase offset, independent time
base period
IOCONx: PWM I/O Control Register
- Enables or disables PWM pin control feature (PWM control or GPIO)
- Controls fault/current limit override values
- Enables PWMxH and PWMxL pin swapping
- Controls the PWMxH and PWMxL output polarity
- Controls the PWMxH and PWMxL output if any of the following modes is selected:
Complementary mode
Push-Pull mode
True Independent mode
Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”
chapter in the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-4 © 2010-2011 Microchip Technology Inc.
FCLCONx: PWM Fault Current-Limit Control Register
- Selects the current-limit control signal source
- Selects the current-limit polarity
- Enables or disables Current-Limit mode
- Selects the fault control signal source
- Configures the fault polarity
- Enables or disables Fault mode
PDCx: PWM Generator Duty Cycle Register(1)
- Provides the duty cycle value for the PWMxH and PWMxL outputs, if master time base is
selected
- Provides the duty cycle value for the PWMxH output, if independent time base is selected
PHASEx: PWM Primary Phase Shift Register
- Provides the phase shift value for the PWMxH and PWMxL output, if master time base is
selected
- Provides the independent time base period for the PWMxH output, if independent time
base is selected
SDCx: PWM Secondary Duty Cycle Register(1,2)
Provides the duty cycle value for the PWMxL output, if independent time base is selected
SPHASEx: PWM Secondary Phase Shift Register(1,2,3)
- Provides the phase shift for the PWMxL output, if the master time base is selected
- Provides the independent time base period value for the PWMxL output, if the independent
time base is selected
DTRx: PWM Dead Time Register
- Provides the dead time value for the PWMxH output, if positive dead time is selected
- Provides the dead time value for the PWMxL output, if negative dead time is selected
ALTDTRx: PWM Alternate Dead Time Register
- Provides the dead time value for the PWMxL output, if positive dead time is selected
- Provides the dead time value for the PWMxH output, if negative dead time is selected
TRIGx: PWM Primary Trigger Compare Value Register
Provides the compare value to generate the primary PWM trigger
TRGCONx: PWM Trigger Control Register
- Enables the PWMx trigger postscaler start event
- Specifies the number of PWM cycles to skip before generating the first trigger
LEBCONx: Leading-Edge Blanking Control Register
- Selects the rising or falling edge of the PWM output for LEB
- Enables or disables LEB for fault and current-limit inputs
LEBDLYx: Leading-Edge Blanking Delay Register
Provides leading-edge blanking delay for the fault and current-limit inputs
PWMCAPx: Primary PWM Time Base Capture Register
Provides the captured independent time base value when a leading edge is detected on
the current-limit input, and when LEB processing on the current-limit input signal is
completed
AUXCONx: PWM Auxiliary Control Register
- Selects PWM state blank and chop clock sources
- Selects PWMxH and PWMxL output chopping functionality
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-5
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-1: PTCON: PWM Time Base Control Register
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN(1) SYNCSRC<2:0>(1) SEVTPS<3:0>(1)
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14 Unimplemented: Read as 0
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
(1)
1 = SYNCIx/SYNCO polarity is inverted (active-low)
0 = SYNCIx/SYNCO is active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO output is enabled
0 = SYNCO output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
(1)
1111 = 1:16 postscaler generates Special Event trigger at every 16th compare match event
0001 = 1:2 postscaler generates Special Event trigger at every second compare match event
0000 = 1:1 postscaler generates Special Event trigger at every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-6 © 2010-2011 Microchip Technology Inc.
Register 14-2: PTCON2: PWM Clock Divider Select Register 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
Register 14-3: PTPER: Primary Master Time Base Period Register
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PTPER<15:8>(1)
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0
PTPER<7:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits(1)
Note 1: 1 LSb = 1 Tosc. For example, 7.14 ns for 70 MIPS operation.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-7
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-4: STCON: PWM Secondary Master Time Base Control Registe (1)
U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
SESTAT SEIEN EIPU(2) SYNCPOL SYNCOEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN SYNCSRC<2:0> SEVTPS<3:0>
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as 0
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(2)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCO2 output is active-low
0 = SYNCO2 output is active-high
bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postscale
0001 = 1:2 Postscale
0000 = 1:1 Postscale
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: This bit only applies to the secondary master time base period.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-8 © 2010-2011 Microchip Technology Inc.
Register 14-5: STCON2: PWM Secondary Clock Divider Select Register 2
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — PCLKDIV<2:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(2)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-9
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-6: STPER: Secondary Master Time Base Period Register
(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: Secondary Master Time Base Period Value bits
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-7: MDC: PWM Master Duty Cycle Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
Register 14-8: SEVTCMP: PWM Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-13
Section 14. High-Speed PWM
High-Speed PWM
14
bit 7-6 DTC<1:0>: Dead Time Control bits
11 = Dead Time Compensation mode enabled
10 = Dead time function is disabled
01 = Negative dead time actively applied for Complementary Output mode(6)
00 = Positive dead time actively applied for all output modes
bit 5 DTCP: Dead Time Compensation Polarity bit(5)
1 = If DTCMPx pin = 0, PWMxL is shortened, and PWMxH is lengthened
If DTCMPx pin = 1, PWMxH is shortened, and PWMxL is lengthened
0 = If DTCMPx pin = 0, PWMxH is shortened, and PWMxL is lengthened
If DTCMPx pin = 1, PWMxL is shortened, and PWMxH is lengthened
bit 4 Unimplemented: Read as ‘0
bit 3 MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and the clock source
for the PWM generation logic (if secondary time base is available)
0 = PWM generator uses the primary master time base for synchronization and the clock source for
the PWM generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,3)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 External PWM Reset Control bitXPRES: (4)
1 = Current-limit source resets primary local time base for this PWM generator if it is in Independent
Time Base mode
0 = External pins do not affect PWM time base
bit 0 IUE: Immediate Update Enable bit(3)
1 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
immediate
0 = Updates to the active MDC/PDCx/SDCx/DTRx/ALTDTRx/PHASEx/SPHASEx registers are
synchronized to the PWM time base
Register 14-12: PWMCONx: PWM Control Register (Continued)
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
2: The Independent Time Base mode (ITB = 1 0) must be enabled to use Center-Aligned mode. If ITB = , the
CAM bit is ignored.
3: These bits should not be changed after the PWM is enabled (PTEN = 1).
4: To operate in External Period Reset mode, the ITB bit must be set to ‘ ’ and the CLMOD bit in the 1
FCLCONx register must be set to0’.
5: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
6: Negative dead time is only implemented for Edge-Aligned mode (CAM = 0).
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-35
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-6: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-8: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
PDC1
PDC2
PDC2
PDC3
PDC3
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-36 © 2010-2011 Microchip Technology Inc.
Example 14-7: Push-Pull PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-37
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-8: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-10: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base*/
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
STPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
MDC
MDC
MDC
MDC
MDC
Complete
PWM1L Cycle
DTR1
ALTDTR1
ALTDTR2
DTR2
ALTDTR3
DTR3
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-38 © 2010-2011 Microchip Technology Inc.
Example 14-9: Push-Pull PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-11: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Period on Secondary Time Base*/
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead time for PWMxH Rising Edge
ALTDTRx Dead time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-39
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-10: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-12: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle Complete
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
ALTDTR3
ALTDTR2
ALTDTR1 DTR1
DTR2
DTR3
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-41
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-12: Push-Pull PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned Mode
Figure 14-14: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned Mode
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time before PWMxH Falling Edge
ALTDTRx Dead Time before PWMxL Falling Edge
Start of
PWM Cycle
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Complete PWM1L
and PWM1H Cycle
DTR1
ALTDTR1
DTR2
ALTDTR2
DTR3
ALTDTR3
MDC
MDC
MDC
MDC
MDC
MDC
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-42 © 2010-2011 Microchip Technology Inc.
Example 14-13: Push-Pull PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned Mode
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Push-Pull */
IOCON1 = IOCON2 = IOCON3 = 0xC800;
/* Set Independent Time Bases, Center-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0304;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-47
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-17: Complementary PWM Mode – Master Duty Cycle and Independent Phase, Fixed Secondary
Period, Edge-Aligned
Figure 14-19: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
/* Set PWM Period on Secondary Time Base*/
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Secondary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0108;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-48 © 2010-2011 Microchip Technology Inc.
Example 14-18: Complementary PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Edge-Aligned
Figure 14-20: Complementary PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
PDC1 = 200;
PDC2 = 300;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 25;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 25;
/* Set PWM Mode to Complementary */
IOCON1 = IOCON2 = IOCON3 = 0xC000;
/* Set Independent Time Bases, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0200;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
PHASE1
PHASE2
PHASE3
Start of
PWM Cycle
DTR1
DTR2
DTR3
ALTDTR1
ALTDTR2
ALTDTR3
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
DTRx Dead Time for PWMxH Rising Edge
ALTDTRx Dead Time for PWMxL Rising Edge
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-52 © 2010-2011 Microchip Technology Inc.
14.6.3 Redundant PWM Output Mode
In Redundant PWM Output mode, the High-Speed PWM module has the ability to provide two
copies of a single-ended PWM output signal per PWM pin pair (PWMxH, PWMxL). This mode
uses the PDCx register to specify the duty cycle. In this output mode, the two PWM output pins
will provide the same PWM signal unless the user-assigned application specifies an override
value. The following eight figures and examples show the Redundant PWM Output mode in
multiple operating modes.
Figure 14-23: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
PTPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-53
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-22: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-24: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
PHASE2
PHASE3
PDC1
PDC2
PDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-54 © 2010-2011 Microchip Technology Inc.
Example 14-23: Redundant PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
Figure 14-25: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Primary Period,
Edge-Aligned
/* Set PWM Period on Secondary Time Base */
STPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
PDC1 = 150;
PDC2 = 200;
PDC3 = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Secondary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0008;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PTPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
PTPER Period of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-55
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-24: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-26: Redundant PWM Mode – Master Duty Cycle and Variable Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
PHASE2 = 100;
PHASE3 = 200;
/* Set Duty Cycles */
MDC = 400;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Primary Time Base, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0100;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
PHASE2
PHASE3
MDC
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
MDC
Start of
PWM Cycle
Where:
PHASEx Phase of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-58 © 2010-2011 Microchip Technology Inc.
Example 14-27: Redundant PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Edge-Aligned
Figure 14-29: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 800;
PHASE2 = 900;
PHASE3 = 1000;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Edge-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0300;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
PDC1
PDC2
PDC3
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H and
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
PDCx Duty Cycle of PWMxH and PWMxL
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-59
Section 14. High-Speed PWM
High-Speed PWM
14
Example 14-28: Redundant PWM Mode – Independent Duty Cycles and Independent Periods, No
Phase-Shifting, Center-Aligned
Figure 14-30: Redundant PWM Mode – Master Duty Cycles and Independent Periods, No Phase-Shifting,
Center-Aligned
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 400;
PDC2 = 300;
PDC3 = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
MDC
MDC
PHASE1
PHASE2
PHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
MDC
Start of
PWM1H Cycle
Complete
PWM1H and
PWM1L Cycle
Where:
PHASEx Period of PWMxH and PWMxL
MDC Duty Cycle of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-60 © 2010-2011 Microchip Technology Inc.
Example 14-29: Redundant PWM Mode – Master Duty Cycles and Independent Periods,
No Phase-shifting, Center-Aligned
Table 14-2 provides PWM register functionality for the PWM modes.
Table 14-2: Complementary, Push-Pull and Redundant Mode Register Functionality
Function
Configuration in PWMCONx Pins
MDCS ITB MTBS PWMxH PWMxL
PWM Duty Cycle 0xxPDCx PDCx
1xxMDC MDC
PWM Phase Shift x0xPHASEx PHASEx
PWM Period xx0PTPER PTPER
xx1STPER STPER
x1xPHASEx PHASEx
Legend: x = don’t care
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1000;
PHASE2 = 900;
PHASE3 = 800;
/* Set Duty Cycles */
MDC = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Redundant */
IOCON1 = IOCON2 = IOCON3 = 0xC400;
/* Set Independent Time Bases, Center-Aligned Mode and Master Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0304;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-61
Section 14. High-Speed PWM
High-Speed PWM
14
14.6.4 True Independent PWM Output Mode
In True Independent PWM Output mode (PMOD = 11), the PWM outputs (PWMxH and PWMxL)
can have different duty cycles. The PDCx register specifies the duty cycle for the PWMxH output,
whereas the SDCx register specifies the duty cycle for the PWMxL output. In addition, the
PWMxH and PWMxL outputs can either have different periods or they can be phase-shifted
relative to each other.
When ITB = 1, the PHASEx register specifies the PWM period for the PWMxH output and
the SPHASEx register specifies the PWM period for the PWMxL output
When ITB = 0, the PHASEx register specifies the phase shift for the PWMxH output and
the SPHASEx register specifies the phase shift for the PWMxL output
Figure 14-31: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Note: Not all of the features and registers listed in the Figures and Code Examples in this
section are available on all devices. Refer to the “High-Speed PWM” chapter of the
specific device data sheet for availability.
Note: In Independent Time Base mode (ITB = 1), there may not be a deterministic phase
relationship between the PWMxH and PWMxL outputs.
PTPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
PTPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-62 © 2010-2011 Microchip Technology Inc.
Example 14-30: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Primary Period,
Edge-Aligned
Figure 14-32: Independent PWM Mode – Independent Duty Cycle and Phase, Fixed Secondary Period,
Edge-Aligned
/* Set PWM Period on Primary Time Base */
PTPER = 1000;
/* Set Phase Shift */
PHASE1 = 0;
SPHASE1 = 100;
PHASE2 = 200;
SPHASE2 = 300;
PHASE3 = 400;
SPHASE3 = 500;
/* Set Duty Cycles */
PDC1 = 100;
SDC1 = 200;
PDC2 = 300;
SDC2 = 400;
PDC3 = 500;
SDC3 = 600;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Primary Time Base, Edge-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0000;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;
STPER
PHASE1 = 0
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Where: PHASEx Phase of PWMxH
SPHASEx Phase of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
STPER Period of PWMxH and PWMxL
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-68 © 2010-2011 Microchip Technology Inc.
Figure 14-37: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Center-Aligned
Example 14-36: Independent PWM Mode – Independent Duty Cycles and Periods, No Phase-Shifting,
Center-Aligned
PDC1
SDC1
PDC2
SDC2
PDC3
SDC3
PHASE1
SPHASE1
PHASE2
SPHASE2
PHASE3
SPHASE3
PWM1H
PWM1L
PWM2H
PWM2L
PWM3H
PWM3L
Start of
PWM Cycle
Complete
PWM1H Cycle
Where: PHASEx Period of PWMxH
SPHASEx Period of PWMxL
PDCx Duty Cycle of PWMxH
SDCx Duty Cycle of PWMxL
/* Set PWM Periods on PHASEx Registers */
PHASE1 = 1300;
SPHASE1 = 1200;
PHASE2 = 1100;
SPHASE2 = 1000;
PHASE3 = 900;
SPHASE3 = 800;
/* Set Duty Cycles */
PDC1 = 700;
SDC1 = 600;
PDC2 = 500;
SDC2 = 400;
PDC3 = 300;
SDC3 = 200;
/* Set Dead Time Values */
DTR1 = DTR2 = DTR3 = 0;
ALTDTR1 = ALTDTR2 = ALTDTR3 = 0;
/* Set PWM Mode to Independent */
IOCON1 = IOCON2 = IOCON3 = 0xCC00;
/* Set Independent Time Bases, Center-Aligned Mode and Independent Duty Cycles */
PWMCON1 = PWMCON2 = PWMCON3 = 0x0204;
/* Configure Faults */
FCLCON1 = FCLCON2 = FCLCON3 = 0x0003;
/* 1:1 Prescaler */
PTCON2 = 0x0000;
/* Enable PWM Module */
PTCON = 0x8000;


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Model: dsPIC33EP64MC206

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