Microchip ATTINY817 Handleiding

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ATtiny417/814/816/817
ATtiny417/814/816/817 Silicon Errata and Data Sheet
Clarification
The ATtiny417/814/816/817 devices you have received conform functionally to the current device data sheet
(www.microchip.com/DS40002288), except for the anomalies described in this document. The errata described in this
document will likely be addressed in future revisions of the ATtiny417/814/816/817 devices.
Notes: 
• This document summarizes all the silicon errata issues from all revisions of silicon, previous as well as current
• Refer to the Device/Revision ID section in the current device data sheet (www.microchip.com/DS40002288) for
more detailed information on Device Identification and Revision IDs for your specific device, or contact your local
Microchip sales office for assistance
© 2020 Microchip Technology Inc. Errata DS80000934A-page 1
1. Silicon Issue Summary
Legend
-Erratum is not applicable.
XErratum is applicable.
Peripheral Short Description Valid for Silicon
Revision
Rev. B(1)
Device 2.2.1 Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic
Loading of Calibration Values X
AC
2.3.1 Coupling Through AC Pins X
2.3.2 AC Interrupt Flag Not Set Unless Interrupt is Enabled X
2.3.3 False Triggers May Occur Under Certain Conditions X
2.3.4 False Triggering When Sweeping Negative Input of the AC When the Low-
Power Mode is Disabled X
ADC
2.4.1 One Extra Measurement Performed After Disabling ADC Free-Running
Mode X
2.4.2 Changing ADC Control Bits During Free-Running Mode not Working X
2.4.3 ADC Wake-Up with WCMP X
2.4.4 ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a
Setting of 25% Duty Cycle X
2.4.5 ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD <
2.7V X
2.4.6 Pending Event Stuck When Disabling the ADC X
2.4.7 ADC Interrupt Flags Cleared When Reading RESH X
CCL
2.5.1 Connecting LUTs in Linked Mode Requires OUTEN Set to ‘1’ X
2.5.2 D-latch is Not Functional X
2.5.3 The CCL Must be Disabled to Change the Configuration of a Single LUT X
RTC 2.6.1 Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler X
2.6.2 Disabling the RTC Stops the PIT X
TCA X2.7.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode
TCB
2.8.1 Minimum Event Duration Must Exceed the Selected Clock Period X
2.8.2 The TCB Interrupt Flag is Cleared When Reading CCMPH X
2.8.3 TCB Input Capture Frequency and Pulse-Width Measurement Mode Not
Working with Prescaled Clock X
2.8.4 The TCA Restart Command Does Not Force a Restart of TCB X
2.8.5 CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode X
ATtiny417/814/816/817
Silicon Issue Summary
© 2020 Microchip Technology Inc. Errata DS80000934A-page 2
...........continued
Peripheral Short Description Valid for Silicon
Revision
Rev. B(1)
TCD
2.9.1 TCD Auto-Update Not Working X
2.9.2 TCD Event Output Lines May Give False Events X
2.9.3 Asynchronous Input Events Not Working When TCD Counter Prescaler is
Used X
TWI
2.10.1 TIMEOUT Bits in the TWI.MCTRLB Register are Not Accessible X
2.10.2 TWI Smart Mode Gives Extra Clock Pulse X
2.10.3 TWI Host Mode Wrongly Detects the Start Bit as a Stop Bit X
2.10.4 The TWI Host Enable Quick Command is Not Accessible X
USART
2.11.1 TXD Pin Override Not Released When Disabling the Transmitter X
2.11.2 Frame Error on a Previous Message May Cause False Start Bit Detection X
2.11.3 Full Range Duty Cycle Not Supported When Validating LIN Sync Field X
2.11.4 Open-Drain Mode Does Not Work When TXD is Configured as Output X
2.11.5 Start-of-Frame Detection Can Unintentionally be Enabled in Active Mode
when RXCIF is ‘0’ X
Note: 
1. This revision is the initial release of the silicon.
ATtiny417/814/816/817
Silicon Issue Summary
© 2020 Microchip Technology Inc. Errata DS80000934A-page 3

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: ATTINY817

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