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ATtiny804/806/807/1604/1606/
1607
Silicon Errata and Data Sheet Clarification
The ATtiny804/806/807/1604/1606/1607 devices you have received conform functionally to the current device data
sheet (www.microchip.com/DS40002312), except for the anomalies described in this document. The errata described
in this document will likely be addressed in future revisions of the ATtiny804/806/807/1604/1606/1607 devices.
Notes:β€€
β€’ This document summarizes all the silicon errata issues from all revisions of silicon, previous as well as current
β€’ Refer to the Device/Revision ID section in the current device data sheet (www.microchip.com/DS40002312) for
more detailed information on Device Identification and Revision IDs for your specific device, or contact your local
Microchip sales office for assistance
Β© 2021 Microchip Technology Inc. Errata DS80000951A-page 1
1. Silicon Issue Summary
Legend
-Erratum is not applicable.
XErratum is applicable.
Peripheral Short Description Valid for Silicon
Revision
Rev. A
Device 2.2.1 Writing the OSCLOCK Fuse in FUSE.OSCCFG to β€˜1’ Prevents Automatic
Loading of Calibration Values X
ADC
2.3.1 One Extra Measurement Performed After Disabling ADC Free-Running
Mode X
2.3.2 Pending Event Stuck When Disabling the ADC X
2.3.3 ADC Performance Degrades with CLKADC Above 1.5 MHz and VDD <
2.7V X
2.3.4 ADC Functionality Cannot be Ensured with CLKADC Above 1.5 MHz and a
Setting of 25% Duty Cycle X
CCL
2.4.1 Connecting LUTs in Linked Mode Requires OUTEN Set to β€˜1’ X
2.4.2 D-latch is Not Functional X
2.4.3 The CCL Must be Disabled to Change the Configuration of a Single LUT X
RTC 2.5.1 Disabling the RTC Stops the PIT X
2.5.2 Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler X
TCA X2.6.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode
TCB
2.7.1 The TCA Restart Command Does Not Force a Restart of TCB X
2.7.2 Minimum Event Duration Must Exceed the Selected Clock Period X
2.7.3 CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode X
USART
2.8.1 TXD Pin Override Not Released When Disabling the Transmitter X
2.8.2 Open-Drain Mode Does Not Work When TXD is Configured as Output X
2.8.3 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode X
ATtiny804/806/807/1604/1606/1607
Silicon Issue Summary
Β© 2021 Microchip Technology Inc. Errata DS80000951A-page 2
2. Silicon Errata Issues
2.1 Errata Details
-Erratum is not applicable.
XErratum is applicable.
2.2 Device
2.2.1 Writing the OSCLOCK Fuse in FUSE.OSCCFG to β€˜ ’ Prevents Automatic Loading of Calibration1
Values
Writing the OSCLOCK fuse in FUSE.OSCCFG to β€˜ ’ prevents the automatic loading of calibration values from the1
signature row. The device will run with an uncalibrated OSC20M oscillator.
Work Around
Do not use OSCLOCK for locking the oscillator calibration value. The oscillator calibration value can be locked by
writing LOCK in CLKCTRL.OSC20MCALIBB to β€˜ ’.1
Affected Silicon Revisions
Rev. A
X
2.3 ADC - Analog-to-Digital Converter
2.3.1 One Extra Measurement Performed After Disabling ADC Free-Running Mode
The ADC may perform one additional measurement after clearing ADCn.CTRLA.FREERUN.
Work Around
Write ADCn.CTRLA.ENABLE to β€˜ ’ to stop the Free-Running mode immediately.0
Affected Silicon Revisions
Rev. A
X
2.3.2 Pending Event Stuck When Disabling the ADC
If the ADC is disabled during an event-triggered conversion, the event will not be cleared.
Work Around
Clear ADC.EVCTRL.STARTEI and wait for the conversion to complete before disabling the ADC.
Affected Silicon Revisions
Rev. A
ATtiny804/806/807/1604/1606/1607
Silicon Errata Issues
Β© 2021 Microchip Technology Inc. Errata DS80000951A-page 3
2.4.3 The CCL Must be Disabled to Change the Configuration of a Single LUT
To reconfigure a LUT, the CCL peripheral must be disabled (write ENABLE in CCL.CTRLA to β€˜ ’). Writing ENABLE to0
β€˜ ’ will disable all the LUTs, and affects the LUTs not under reconfiguration.0
Work Around
None
Affected Silicon Revisions
Rev. A
X
2.5 RTC - Real-Time Counter
2.5.1 Disabling the RTC Stops the PIT
Writing RTC.CTRLA.RTCEN to β€˜ ’ will stop the PIT.0
Writing RTC.PITCTRLA.PITEN to β€˜ ’ will stop the RTC.0
Work Around
Do not disable the RTC or the PIT if any of the modules are used.
Affected Silicon Revisions
Rev. A
X
2.5.2 Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler
Any write to the RTC.CTRLA register resets the 15-bit prescaler resulting in a longer period on the current count or
period.
Work Around
None.
Affected Silicon Revisions
Rev. A
X
2.6 TCA - 16-Bit Timer/Counter Type A
2.6.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode
When the TCA is configured to the NORMAL or FRQ mode (WGMODE in TCAn.CTRLB is β€˜ ’ or β€˜ ’), a0x0 0x1
RESTART command or Restart event will reset direction to default. The default is counting upwards.
Work Around
None.
ATtiny804/806/807/1604/1606/1607
Silicon Errata Issues
Β© 2021 Microchip Technology Inc. Errata DS80000951A-page 5
4. Document Revision History
Note:β€€ The document revision is independent of the silicon revision.
4.1 Revision History
Doc.
Rev.
Date Comments
A 04/2021 β€’ Initial document release
The content of the document has been restructured from:
β€’ ATtiny804/1604 Silicon Errata and Data Sheet Clarification
β€’ ATtiny806/1606 Silicon Errata and Data Sheet Clarification
β€’ ATtiny807/1607 Silicon Errata and Data Sheet Clarification
to:
β€’ATtiny804/806/807/1604/1606/1607 Silicon Errata and Data Sheet Clarification (this
document)
Refer to for further details.4.2 Appendix - Obsolete Revision History
The following items are referring to changes between the latest revisions of the obsolete
documents and this document:
β€’ Added new errata:
– Device: 2.2.1 Writing the OSCLOCK Fuse in FUSE.OSCCFG to β€˜1’ Prevents Automatic
Loading of Calibration Values
– CCL: 2.4.3 The CCL Must be Disabled to Change the Configuration of a Single LUT
– TCA: 2.6.1 Restart Will Reset Counter Direction in NORMAL and FRQ Mode
– TCB: 2.7.3 CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode
– USART:
β€’2.8.2 Open-Drain Mode Does Not Work When TXD is Configured as Output
β€’2.8.3 Start-of-Frame Detection Can Unintentionally Be Triggered in Active Mode
β€’ Removed old data sheet clarifications, as the corresponding data sheet has been updated
with correct information
4.2 Appendix - Obsolete Revision History
Notes:β€€ Due to document structure change from pin organized documents, the following obsolete document revision
history is provided as a reference.
β€’ ATtiny804/1604 Silicon Errata and Data Sheet Clarification (DS40002126B)
β€’ ATtiny806/1606 Silicon Errata and Data Sheet Clarification (DS40002127B)
β€’ ATtiny807/1607 Silicon Errata and Data Sheet Clarification (DS40002128B)
4.2.1 Obsolete Document DS40002126
Doc. Rev. Date Comments
B 10/2019 β€’ Updated document template
β€’ The ADC errata, ADC Functionality Cannot be Ensured with ADCCLK Above 1.5
MHz for All Conditions, has been split into two separate erratas and rewritten
β€’ Added clarification for ADC electrical characteristics
A 06/2019 Initial document release.
ATtiny804/806/807/1604/1606/1607
Document Revision History
Β© 2021 Microchip Technology Inc. Errata DS80000951A-page 9

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: ATTINY806

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