Microchip ATF1500A Handleiding

Microchip Niet gecategoriseerd ATF1500A

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TQFP
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I/O/PD
VCC
OE2/I
GCLR/I
OE1/I
CLK/I
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I/O
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PLCC
Top View
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VCC
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CLK/I
GND
I/O
I/O
Pin Configurations
Pin
Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional
Buffers
GCLR Register Reset
(active low)
OE1,
OE2
Output Enable
(active low)
VCC +5V Supply
PD Power-down
(active high)
Features
β€’High-density, High-performance Electrically-erasable Complex
Programmable Logic Device
– 44-pin, 32 I/O CPLD
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up to 125 MHz
– Fully Connected Input and Feedback Logic Array
– Backward Compatibility with ATF1500/L Software and Hardware
β€’Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
β€’Advanced Power Management Features
– Automatic 3 mA Standby (ATF1500AL)
– Pin-controlled 10 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
β€’Available in Commercial and Industrial Temperature Ranges
β€’Available in 44-lead PLCC and TQFP Packages
β€’Advanced Flash Technology
– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
β€’Supported by Popular third-arty Tools
β€’Security Fuse Feature
β€’Pin-compatible with the Most Commonly Used Devices
β€’Green (Pb/Halide-fee/RoHS Compliant) Package Options
Description
The ATF1500A is a high-performance, high-density complex PLD. Built on an
advanced Flash technology, it has maximum pin-to-pin delays of 7.5 ns and supports
sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up
to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.
The ATF1500A’s global input and feedback architecture simplifies logic placement
and eliminates pinout changes due to design changes.
High-
performance
EPLD
ATF1500A
ATF1500AL
Rev. 0759F–6/05
(continued)
ATF1500A(L)
2
Functional Logic Diagram(1)
Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500A has 32 bi-directional I/O pins and four dedi-
cated input pins. Each dedicated input pin can also serve
as a global control signal: register clock, register reset or
output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feed-
back, which goes to the global bus. Each input and I/O pin
also feeds into the global bus. Because of this global bus-
ing, each of these signals is always available to all 32 mac-
rocells in the device.
ATF1500A(L)
3
Each macrocell also generates a foldback logic term, which
goes to a regional bus. All signals within a regional bus are
connected to all 16 macrocells within the region.
Cascade logic between macrocells in the ATF1500A allows
fast, efficient generation of complex logic functions. The
ATF1500A contains four such logic chains, each capable of
creating sum term logic with a fan-in of up to 40 product
terms.
Bus-friendly Pin-keeper Input and I/O’s
All Input and I/O pins on the ATF1500A have programma-
ble β€œpin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
This circuitry prevents unused Input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Pin-keeper circuits can be disabled. Programming is con-
trolled in the logic design file. Once the pin-keeper circuits
are disabled, normal termination procedures are required
for unused inputs and I/Os.
Speed/Power Management
The ATF1500A has several built-in speed and power man-
agement features. The ATF1500A contains circuitry that
automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only
reduces power consumption during inactive periods, but
also provides proportional power savings for most applica-
tions running at system speeds below 10 MHz.
All ATF1500As also have an optional pin-controlled power-
down mode. In this mode, current drops to below 10 mA.
When the power-down option is selected, the PD pin is
used to power-down the part. The power-down option is
selected in the design source file. When enabled, the
device goes into power-down when the PD pin is high. In
the power-down mode, all internal logic signals are latched
and held, as are any enabled outputs. All pin transitions are
ignored until the PD is brought low. When the power-down
feature is enabled, the PD cannot be used as a logic input
or output. However, the PD pin’s macrocell may still
be used to generate buried foldback and cascade
logic signals.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
Design Software Support
ATF1500A designs are supported by several third-party
tools. Automated fitters allow logic synthesis using a variety
of high-level description languages and formats.
Input Diagram
I/O Diagram
100K
VCC
ESD
PROTECTION
CIRCUIT
INPUT
PROGRAMMABLE
OPTION
100K
V
CC
V
CC
DATA
OE
I/O
PROGRAMMABLE
OPTION

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: ATF1500A

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