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2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 1
11AA010/11LC010 11AA080/11LC080
11AA020/11LC020 11AA160/11LC160
11AA040/11LC040 11AA161/11LC161
Features
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current (max.) (I-temp)
• 128 x 8 through 2,048 x 8 Bit Organizations
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• RoHS Compliant
• Available Temperature Ranges:
• Automotive AEC-Q100 Qualified
Packages
• 3-lead SOT-23 and TO-92 Packages
• 4-lead Chip Scale Package
• 8-lead PDIP, SOIC, MSOP and TDFN Packages
Pin Function Table
Description
The Microchip Technology Inc. 11AAXXX/11LCXXX
(11XX( )1) devices are a family of 1-Kbit through 16-Kbit
Serial Electrically Erasable PROMs. The devices are
organized in blocks of x8-bit memory and support the
patented( )2 single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Low-voltage design permits operation down to 1.8V (for
11AAXXX devices), with standby and active currents of
only 1 µA and 1 mA, respectively.
Package Types (not to scale)
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
Name Function
SCIO Serial Clock, Data Input/Output
VSS Ground
VCC Supply Voltage
Note 1: 11XX is used in this document as a
generic part number for the 11 series
devices.
2: Microchip's UNI/O® Bus products are
covered by some or all of the following
patents issued in the U.S.A.: 7.376,020 &
7,788,430.
NC
NC
NC
Vss
1
2
3
4
8
7
6
5
VCC
NC
NC
SCIO
PDIP/SOIC
(P, SN)
NC
NC
NC
V
SS
1
2
3
4
8
7
6
5
VCC
NC
NC
SCIO
(MS)
TDFN
NC
NC
NC
VSS
NC
NC
SCIO
5
6
7
8
4
3
2
1VCC
(MN)
MSOP
SOT23
2
3
1 SCIO
VCC
VSS
(TT)
Vcc
TO-92
SCIO
(TO) 1 2
34
VCC VSS
NC
SCIO
(Top down view,
balls not visible
)
Note 1: Available in I-temp, “AA” only.
Vss
CS (Chip Scale)( )1
1-Kbit to 16-Kbit UNI/O® Serial EEPROM Family Data Sheet
11AAXXX/11LCXXX
DS20002067K-page 2
2011-2023 Microchip Technology Inc. and its subsidiaries
DEVICE SELECTION TABLE
Part Number Density
(bits) Organization VCC Range Page Size
(Bytes)
Temp.
Ranges
Device
Address Packages
11LC010 1 Kbit 128 x 8 2.5V-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA010 1 Kbit 128 x 8 1.8V-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS
11LC020 2 Kbit 256 x 8 2.5V-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA020 2 Kbit 256 x 8 1.8V-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS
11LC040 4 Kbit 512 x 8 2.5V-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA040 4 Kbit 512 x 8 1.8V-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS
11LC080 8 Kbit 1,024 x 8 2.5V-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA080 8 Kbit 1,024 x 8 1.8V-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT, CS
11LC160 16 Kbit 2,048 x 8 2.5V-5.5V 16 I,E 0xA0 P, SN, MS, MN, TO, TT
11AA160 16 Kbit 2,048 x 8 1.8V-5.5V 16 I 0xA0 P, SN, MS, MN, TO, TT,CS
11LC161 16 Kbit 2,048 x 8 2.5V-5.5V 16 I, E 0xA1 P, SN, MS, MN, TO, TT
11AA161 16 Kbit 2,048 x 8 1.8V-5.5V 16 I 0xA1 P, SN, MS, MN, TO, TT, CS
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 3
11AAXXX/11LCXXX
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
SCIO w.r.t. VSS.....................................................................................................................................-0.6V to VCC+1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias............................................................................................................... -40°C to 125°C
ESD protection on all pins.......................................................................................................................................... 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Extended (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
D1 VIH High-level input
voltage 0.7*VCC CCV +1 V —
D2 VIL Low-level input
voltage
-0.3 0.3*VCC V VCC2.5V
-0.3 0.2*VCC V VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs (SCIO) 0.05*Vcc — V VCC2.5V ( )Note 1
D4 VOH High-level output
voltage
VCC -0.5 — V IOH = -300 A, VCC = 5.5V
VCC -0.5 — V IOH = -200 A, Vcc = 2.5V
D5 VOL Low-level output
voltage
— 0.4 V IOI = 300 A, VCC = 5.5V
— 0.4 V IOI = 200 A, Vcc = 2.5V
D6 IOOutput current limit
( )Note 2
— ±4 mA VCC = 5.5V ( )Note 1
— ±3 mA Vcc = 2.5V ( )Note 1
D7 ILI Input leakage current
(SCIO) — ±1 A VIN = VSS or VCC
D8 CINT
Internal Capacitance
(all inputs and
outputs)
— 7 pF TA = 25°C, FCLK = 1 MHz,
VCC = 5.0V ( )Note 1
D9 ICC Read Read Operating
Current
— 3 mA VCC=5.5V; FBUS=100 kHz, CB=100 pF
— 1 mA VCC=2.5V; FBUS=100 kHz, CB=100 pF
D10 ICC Write Write Operating
Current
— 5 mA VCC = 5.5V
— 3 mA VCC = 2.5V
D11 Iccs Standby Current
— 5 AVCC = 5.5V
TA = 125°C
— 1 AVCC = 5.5V
TA = 85°C
D12 ICCI Idle Mode Current — 50 A VCC = 5.5V
Note 1: This parameter is periodically sampled and is not 100% tested.
2: The SCIO output driver impedance will vary to ensure IO is not exceeded.
11AAXXX/11LCXXX
DS20002067K-page 4
2011-2023 Microchip Technology Inc. and its subsidiaries
TABLE 1-3: AC TEST CONDITIONS
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C
VCC = 1.8V to 2.5V TA = -20°C to +85°C
Extended (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Test Conditions
1 FBUS Serial bus frequency 10 100 kHz —
2 TEBit period 10 100 µs —
3 TIJIT Input edge jitter tolerance — ±0.06 UI ( )Note 2
4 FDRIFT Serial bus frequency drift
rate tolerance — ±0.50 % per byte —
5 FDEV Serial bus frequency drift
limit — ±5 % per
command —
6 TOJIT Output edge jitter — ±0.25 UI (Note 2)
7 TRSCIO input rise time
( )Note 1 — 100 ns —
8 TFSCIO input fall time
( )Note 1 — 100 ns —
9 TSTBY Standby pulse time 600 — µs —
10 TSS Start header setup time 10 — µs —
11 THDR Start header low pulse
time 5 — µs —
12 TSP Input filter spike
suppression (SCIO) — 50 ns ( )Note 1
13 TWC Write cycle time
(byte or page)
— 5 m Write, WRSR commands
— 10 ms ERAL SETAL, commands
14 — Endurance (per page) 1M — cycles 25°C, VCC = 5.5V
Note 1: This parameter is periodically sampled and is not 100% tested.
2: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.
3: This parameter is not tested but ensured by characterization.
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 100 pF
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 5
11AAXXX/11LCXXX
FIGURE 1-1: BUS TIMING – START HEADER
FIGURE 1-2: BUS TIMING – DATA
FIGURE 1-3: BUS TIMING – STANDBY PULSE
FIGURE 1-4: BUS TIMING – JITTER
SCIO
2
Data ‘ Data ‘ Data ‘ Data ‘ Data ‘0 1’ Data ‘ ’ 0 1’ Data ‘ ’ 0’1 0’ Data ‘ ’ 1’ MAK bit NoSAK bit
1110
2
SCIO
7 8
Data ‘ Data ‘ Data ‘0’1 1’ Data ‘ ’ 0’
12
SCIO
9
Standby
Mode
Ideal Edge
3
2
3 6 6
2
6 6
Ideal Edge Ideal Edge Ideal Edge
from Host from Host from Client from Client
11AAXXX/11LCXXX
DS20002067K-page 6
2011-2023 Microchip Technology Inc. and its subsidiaries
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 Serial Clock, Data Input/Output
(SCIO)
SCIO is a bidirectional pin used to transfer commands
and addresses into, as well as data into and out of, the
device. The serial clock is embedded into the data
stream through Manchester encoding. Each bit is
represented by a signal transition at the middle of the
bit period.
Name 3-pin SOT-23 3-pin TO-92 4-pin CS 8-pin PDIP/SOIC/
MSOP/TDFN Description
SCIO 1 2 3 5 Serial Clock, Data Input/Output
VCC 2 3 1 8 Supply Voltage
VSS 3 1 2 4 Ground
NC — — 4 1,2,3,6,7 No Internal Connection
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 7
11AAXXX/11LCXXX
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles of Operation
The 11AAXXX/11LCXXX family of serial EEPROMs
support the UNI/O® protocol. They can be interfaced
with microcontrollers, including Microchip’s PIC®
microcontrollers, ASICs, or any other device with an
available discrete I/O line that can be configured prop-
erly to match the UNI/O protocol.
The 11AAXXX/11LCXXX devices contain an 8-bit
instruction register. The devices are accessed via the
SCIO pin.
Table 5-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb
last.
Data is embedded into the I/O stream through
Manchester encoding. The bus is controlled by a host
device which determines the clock period, controls the
bus access and initiates all operations, while the
11AAXXX/11LCXXX works as client. Both host and cli-
ent can operate as transmitter or receiver, but the host
device determines which mode is active.
FIGURE 3-1: BLOCK DIAGRAM
SCIO
STATUS
Register
I/O Control Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
Logic
Vcc
Vss
Current-
Limited
Slope
Control
11AAXXX/11LCXXX
DS20002067K-page 8
2011-2023 Microchip Technology Inc. and its subsidiaries
4.0 BUS CHARACTERISTICS
4.1 Standby Pulse
When the host has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11AAXXX/11LCXXX will reset and return
to Standby mode. Subsequently, a high-to-low
transition on SCIO (the first low pulse of the header)
will return the device to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the
previous command. However, a period of TSS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the host must perform
a standby pulse before beginning a new command,
regardless of which device is to be selected.
An example of two consecutive commands is shown in
Figure 4-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the client
has control of SCIO. In this situation, the host must
wait for the client to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command, an error is detected
by the host, a standby pulse should be generated and
the command should be performed again.
FIGURE 4-1: CONSECUTIVE COMMANDS EXAMPLE
4.2 Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101’
code. This code is used to synchronize the client’s
internal clock period with the host’s clock period, so
accurate timing is very important.
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
TSS must be observed at the end of the command and
before the beginning of the start header.
Figure 4-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
FIGURE 4-2: START HEADER
Note: After a POR/BOR event occurs, a low-to-
high transition on SCIO must be
generated before proceeding with
communication, including a standby
pulse.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 000101 0
MAK
NoSAK
SAK
Standby Pulse(1)
1 101010 0
Start Header
SCIO
Device Address
MAK
0 000101 0
MAK
NoSAK
SAK
NoMAK
SAK
TSS
Note 1: After a POR/BOR event, a low-to-high transition on SCIO must occur before the first standby
pulse.
SCIO
Data ‘ Data ‘0 1 0 1 0’ Data ‘ ’ Data ‘ ’ Data ‘ ’ Data ‘ ’ 1 0 1’ Data ‘ ’ Data ‘ ’ MAK NoSAKT TSS HDR
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 9
11AAXXX/11LCXXX
4.3 Acknowledge
An Acknowledge routine occurs after each byte is
transmitted, including the start header. This routine
consists of two bits. The first bit is transmitted by the
host, and the second bit is transmitted by the client.
The Host Acknowledge, or MAK, is signified by trans-
mitting a ‘1’, and informs the client that the current
operation is to be continued. Conversely, a Not
Acknowledge, or NoMAK, is signified by transmitting a
‘0’, and is used to end the current operation (and initiate
the write cycle for write operations).
The Client Acknowledge, or SAK, is also signified by
transmitting a ‘1’, and confirms proper communication.
However, unlike the NoMAK, the NoSAK is signified by
the lack of a middle edge during the bit period.
A NoSAK will occur for the following events:
• Following the start header
• Following the device address, if no client on the
bus matches the transmitted address
• Following the command byte, if the command is
invalid, including Read, CRRD, Write, WRSR,
SETAL and ERAL during a write cycle.
• If the client becomes out of sync with the host
• If a command is terminated prematurely by using
a NoMAK, with the exception of immediately after
the device address.
See Figure 4-3 and Figure 4-4 for details.
If a NoSAK is received from the client after any byte
(except the start header), an error has occurred. The
host should then perform a standby pulse and begin
the desired command again.
FIGURE 4-3: ACKNOWLEDGE
ROUTINE
FIGURE 4-4: ACKNOWLEDGE BITS
4.4 Device Addressing
A device address byte is the first byte received from the
host device following the start header. The device
address byte consists of a four-bit family code. For the
11AAXXX/11LCXXX, this is set as ‘
1010’. The last four
bits of the device address byte are the device code,
which is hardwired to ‘0000’ on the 11XXXX0 devices.
The device code on 11XXXX1 devices is hardwired to
‘0001’. This allows both 11XXXX0 and 11XXXX1
devices to be used on the same bus without address
conflicts.
FIGURE 4-5: DEVICE ADDRESS BYTE
ALLOCATION
4.5 Bus Conflict Protection
To help guard against high current conditions arising
from bus conflicts, the 11AAXXX/11LCXXX features a
current-limited output driver. The IOL and IOH
specifications describe the maximum current that can
be sunk or sourced, respectively, by the SCIO pin. The
11AAXXX/11LCXXX will vary the output driver
impedance to ensure that the maximum current level is
not exceeded.
Note: A MAK must always be transmitted
following the start header.
Note: When a NoMAK is used to end a
WRITE WRSR or instruction, the write
cycle is not initiated if no bytes of data
have been received.
Note: To guard against bus contention, a
NoSAK will occur after the start header.
Host Client
MAK SAK
MAK (‘1’)
NoMAK (‘0’)
SAK (‘1’)
NoSAK(1)
Note 1:
valid SAK.
A NoSAK is defined as any sequence that is not a
1 0 1 0 0 0 0
MAK
CLIENT ADDRESS
0(1)
SAK
Note 1: This bit is a ‘1’ on the 11XXXX1.
11AAXXX/11LCXXX
DS20002067K-page 10
2011-2023 Microchip Technology Inc. and its subsidiaries
4.6 Device Standby
The 11AAXXX/11LCXXX features a low-power
Standby mode during which the device is waiting to
begin a new command. A high-to-low transition on
SCIO will exit low-power mode and prepare the device
for receiving the start header.
Standby mode will be entered upon the following
conditions:
• A NoMAK followed by a SAK (i.e., valid
termination of a command)
• Reception of a standby pulse
4.7 Device Idle
The 11AAXXX/11LCXXX features an Idle mode during
which all serial data is ignored until a standby pulse
occurs. Idle mode will be entered upon the following
conditions:
• Invalid device address
• Invalid command byte, including Read, CRRD,
Write, WRSR, SETAL and ERAL during a write
cycle.
• Missed edge transition
• Reception of a MAK following a WREN WRDI, ,
SETAL ERAL or command byte
• Reception of a MAK following the data byte of a
WRSR command
An invalid start header will indirectly cause the device
to enter Idle mode. Whether or not the start header is
invalid cannot be detected by the client, but will
prevent the client from synchronizing properly with the
host. If the client is not synchronized with the host, an
edge transition will be missed, thus causing the device
to enter Idle mode.
4.8 Synchronization
At the beginning of every command, the
11AAXXX/11LCXXX utilizes the start header to
determine the host’s bus clock period. This period is
then used as a reference for all subsequent
communication within that command.
The 11AAXXX/11LCXXX features re-synchronization
circuitry, which will monitor the position of the middle
data edge during each MAK bit and will subsequently
adjust the internal time reference to remain
synchronized with the host.
There are two variables which can cause the
11AAXXX/11LCXXX to lose synchronization. The first
is frequency drift, defined as a change in the bit period,
TE. The second is edge jitter, which is a single
occurrence change in the position of an edge within a
bit period, while the bit period itself remains constant.
4.8.1 FREQUENCY DRIFT
Within a system, there is a possibility that frequencies
can drift due to changes in voltage, temperature, etc.
The re-synchronization circuitry provides some
tolerance for such frequency drift. The tolerance range
is specified by two parameters, FDRIFT and FDEV.
FDRIFT specifies the maximum tolerable change in bus
frequency per byte. FDEV specifies the overall limit in
frequency deviation within an operation (i.e., from the
end of the start header until communication is
terminated for that operation). The start header at the
beginning of the next operation will reset the re-
synchronization circuitry and allow for another FDEV
amount of frequency drift.
4.8.2 EDGE JITTER
Ensuring that edge transitions from the host always
occur exactly in the middle or end of the bit period is not
always possible. Therefore, the re-synchronization
circuitry is designed to provide some tolerance for edge
jitter.
The 11XX adjusts its phase every MAK bit, so T
IJIT
specifies the maximum allowable peak-to-peak jitter
relative to the previous MAK bit. Since the position of
the previous MAK bit would be difficult to measure by
the host, the minimum and maximum jitter values for a
system should be considered the worst-case. These
values will be based on the execution time for different
branch paths in software, jitter due to thermal noise,
etc.
The difference between the minimum and maximum
values, as a percentage of the bit period, should be cal-
culated and then compared against TIJIT to determine
jitter compliance.
Note: In the case of the
WRITE, WRSR, SETAL or
ERAL commands, the write cycle is initiated
upon receipt of the NoMAK, assuming all
other write requirements have been met.
Note: Because the 11AAXXX/11LCXXX only re-
synchronizes during the MAK bit, the overall
ability to remain synchronized depends on a
combination of frequency drift and edge
jitter (i.e., if the MAK bit edge is
experiencing the maximum allowable edge
jitter, then there is no room for frequency
drift). Conversely, if the frequency has
drifted to the maximum amount tolerable
within a byte, then no edge jitter can be
present.
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 11
11AAXXX/11LCXXX
5.0 DEVICE COMMANDS
After the device address byte, a command byte must
be sent by the host to indicate the type of operation to
be performed. The code for each instruction is listed in
Table 5-1.
TABLE 5-1: INSTRUCTION SET
5.1 Read Instruction
The Read command allows the host to access any
memory location in a random manner. After the READ
instruction has been sent to the client, the two bytes of
the Word Address are transmitted, with an
Acknowledge sequence being performed after each
byte. Then, the client sends the first data byte to the
host. If more data is to be read, the host sends a MAK,
indicating that the client should output the next data
byte. This continues until the host sends a NoMAK,
which ends the operation.
To provide sequential reads in this manner, the
11AAXXX/11LCXXX contains an internal Address
Pointer which is incremented by one after the
transmission of each byte. This Address Pointer allows
the memory contents to be serially read during one
operation. When the highest address is reached, the
Address Pointer rolls over to address ‘0x000’ if the host
chooses to continue the operation by providing a MAK.
FIGURE 5-1: READ COMMAND SEQUENCE
Instruction Name Instruction Code Hex Code Description
READ 0000 0011 0x03 Read data from memory array beginning at specified address
CRRD 0000 0110 0x06 Read data from current location in memory array
WRITE 0110 1100 0x6C Write data to memory array beginning at specified address
WREN 1001 0110 0x96 Set the write enable latch (enable write operations)
WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations)
RDSR 0000 0101 0x05 Read STATUS register
WRSR 0110 1110 0x6E Write STATUS register
ERAL 0110 1101 0x6D Write ‘ 0x00’ to entire array
SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array
7 6 5 4
Data Byte 1
3 2 1 0 7 6 5 4
Data Byte 2
3 2 1 0 7 6 5 4
Data Byte n
3 2 1 0
SCIO
MAK
MAK
NoMAK
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
0 100000 1
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address MSB
11 10 9 8
MAK
SAK
7 6 5 4
Word Address LSB
3 2 1 0
MAK
SAK
SAK
SAK
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11AAXXX/11LCXXX
DS20002067K-page 12
2011-2023 Microchip Technology Inc. and its subsidiaries
5.2 Current Address Read (CRRD)
Instruction
The internal address counter featured on the
11AAXXX/11LCXXX maintains the address of the last
memory array location accessed. The CRRD
instruction allows the host to read data back beginning
from this current location. Consequently, no word
address is provided upon issuing this command.
Note that, except for the initial word address, the
READ CRRD and instructions are identical, including
the ability to continue requesting data through the use
of MAKs in order to sequentially read from the array.
As with the READ CRRD instruction, the instruction is
terminated by transmitting a NoMAK.
Table 5-2 lists the events upon which the internal
address counter is modified.
TABLE 5-2: INTERNAL ADDRESS
COUNTER
FIGURE 5-2: CRRD COMMAND SEQUENCE
Command Event Action
— Power-on Reset Counter is undefined
READ or
WRITE
MAK edge fol-
lowing each
Address byte
Counter is updated
with newly received
value
READ,
WRITE or
CRRD
MAK/NoMAK
edge following
each data byte
Counter is
incremented by 1
Note 1: If, following each data byte in a READ,
WRITE CRRD or instruction, neither a
MAK nor a NoMAK edge is received (i.e.,
if a standby pulse occurs instead), the
internal address counter will not be incre-
mented.
2: During a Write command, once the last
data byte for a page has been loaded, the
internal Address Pointer will rollover to
the beginning of the selected page.
7 6 5 4
Data Byte 1
3 2 1 7 6 50 4
Data Byte 2
3 2 1 0
7 6 5 4
Data Byte n
3 2 1 0
SCIO
MAK
MAK
NoMAK
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 000000 1
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
SAK
SAK
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 13
11AAXXX/11LCXXX
5.3 Write Instruction
Prior to any attempt to write data to the
11AAXXX/11LCXXX, the write enable latch must be set
by issuing the WREN instruction (see Section 5.4
“Write Enable (WREN) and Write Disable (WRDI)
Instructions”).
Once the write enable latch is set, the user may
proceed with issuing a WRITE instruction (including
the header and device address bytes) followed by the
MSB and LSB of the Word Address. Once the last
Acknowledge sequence has been performed, the host
transmits the data byte to be written.
The 11AAXXX/11LCXXX features a 16-byte page
buffer, meaning that up to 16 bytes can be written at
one time. To utilize this feature, the host can transmit
up to 16 data bytes to the 11AAXXX/11LCXXX, which
are temporarily stored in the page buffer. After each
data byte, the host sends a MAK, indicating whether or
not another data byte is to follow. A NoMAK indicates
that no more data is to follow, and as such will initiate
the internal write cycle.
Upon receipt of each word, the four lower-order
Address Pointer bits are internally incremented by one.
The higher-order bits of the word address remain
constant. If the host should transmit data past the end
of the page, the address counter will roll over to the
beginning of the page, where further received data will
be written.
FIGURE 5-3: WRITE COMMAND SEQUENCE
Note: If a NoMAK is generated before any
data has been provided, or if a standby
pulse occurs before the NoMAK is
generated, the 11AAXXX/11LCXXX will
be reset, and the write cycle will not be
initiated.
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses that
are integer multiples of the page size
(16 bytes) and end at addresses that
are integer multiples of the page size
minus 1. As an example, the page that
begins at address 0x30 ends at address
0x3F. If a page Write command attempts
to write across a physical page
boundary, the result is that the data
wraps around to the beginning of the
current page (overwriting data
previously stored there), instead of
being written to the next page as might
be expected. It is, therefore, necessary
for the application software to prevent
page write operations that would
attempt to cross a page boundary.
7 6 5 4
Data Byte 1
3 2 1 0 7 6 5 4
Data Byte 2
3 2 1 0 7 6 5 4
Data Byte n
3 2 1 0
SCIO
MAK
MAK
NoMAK
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 010110 0
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
15 14 13 12
Word Address MSB
11 10 9 8
MAK
SAK
7 6 5 4
Word Address LSB
3 2 1 0
MAK
SAK
SAK
SAK
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11AAXXX/11LCXXX
DS20002067K-page 14
2011-2023 Microchip Technology Inc. and its subsidiaries
5.4 Write Enable (WREN) and Write
Disable ( ) InstructionsWRDI
The 11XX contains a write enable latch. See Table 7-1
for the Write-Protect Functionality Matrix. This latch
must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI instruction will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
•WRDI instruction successfully executed
•WRSR instruction successfully executed
•WRITE instruction successfully executed
•ERAL instruction successfully executed
•SETAL instruction successfully executed
FIGURE 5-4: WRITE ENABLE COMMAND SEQUENCE
FIGURE 5-5: WRITE DISABLE COMMAND SEQUENCE
Note: The WREN and WRDI instructions must
be terminated with a NoMAK following
the command byte. If a NoMAK is not
received at this point, the command will
be considered invalid, and the device
will go into Idle mode without
responding with a SAK or executing the
command.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 001001 1
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
0 101001 0
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 15
11AAXXX/11LCXXX
5.5 Read Status Register (RDSR)
Instruction
The RDSR instruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
11AAXXX/11LCXXX is busy with a write operation.
When set to a ‘1’, a write is in progress. When set to a
‘0’, no write is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
1’, the latch
allows writes to the array. When set to a ‘
0’, the latch
prohibits writes to the array. This bit is set and cleared
using the WREN and WRDI instructions, respectively.
This bit is read-only for any other instruction.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user through the WRSR instruction.
These bits are nonvolatile.
The WIP and WEL bits will update dynamically
(asynchronous to issuing the RDSR instruction).
Furthermore, after the STATUS register data is
received, the host can provide a MAK during the
Acknowledge sequence to request that the data be
transmitted again. This allows the host to continuously
monitor the WIP and WEL bits without the need to issue
another full command.
Once the host is finished, it provides a NoMAK to end
the operation.
FIGURE 5-6: READ STATUS REGISTER COMMAND SEQUENCE
7 6 5 4 3 2 1 0
X X X X BP1 BP0 WEL WIP
Note: Bits 4-7 are don’t cares, and will read as ‘0’.
Note: If Read Status Register command is
initiated while the 11XX is currently
executing an internal write cycle on the
STATUS register, the new Block
Protection bit values will be read during
the entire command.
Note: The current drawn for a Read Status
Register command during a write cycle
is a combination of the ICC Read and ICC
Write operating currents.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 100000 0
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
STATUS Register Data
3 2 1 0
NoMAK
SAK
The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAKNote 2:
0000
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11AAXXX/11LCXXX
DS20002067K-page 16
2011-2023 Microchip Technology Inc. and its subsidiaries
5.6 Write Status Register (WRSR)
Instruction
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided into four segments. The user has the ability to
write-protect none, one, two, or all four of the segments
of the array. The partitioning is controlled as illustrated
in Table 5-3.
After transmitting the STATUS register data, the host
must transmit a NoMAK during the Acknowledge
sequence in order to initiate the internal write cycle.
TABLE 5-3: ARRAY PROTECTION
TABLE 5-4: PROTECTED ARRAY ADDRESS LOCATIONS
FIGURE 5-7: WRITE STATUS REGISTER COMMAND SEQUENCE
Note: The WRSR instruction must be
terminated with a NoMAK following the
data byte. If a NoMAK is not received at
this point, the command will be
considered invalid, and the device will
go into Idle mode without responding
with a SAK or executing the command.
BP1 BP0 Address Ranges Write-Protected Address Ranges Unprotected
0 0 None All
0 1 Upper 1/4 Lower 3/4
1 0 Upper 1/2 Lower 1/2
1 1 All None
Density Upper 1/4 Upper 1/2 All Sectors
1K 60h-7Fh 40h-7Fh 00h-7Fh
2K C0h-FFh 80h-FFh 00h-FFh
4K 180h-1FFh 100h-1FFh 000h-1FFh
8K 300h-3FFh 200h-3FFh 000h-3FFh
16K 600h-7FFh 400h-7FFh 000h-7FFh
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 010110 1
MAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
7 6 5 4
Status Register Data
3 2 1 0
NoMAK
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 17
11AAXXX/11LCXXX
5.7 Erase All (ERAL) Instruction
The ERAL instruction allows the user to write ‘0x00’ to
the entire memory array with one command. Note that
the write enable latch (WEL) must first be set by issuing
the WREN instruction.
Once the write enable latch is set, the user may
proceed with issuing a ERAL instruction (including the
header and device address bytes). Immediately after
the NoMAK bit has been transmitted by the host, the
internal write cycle is initiated, during which time all
words of the memory array are written to ‘0x00’.
The ERAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 5-8: ERASE ALL COMMAND SEQUENCE
5.8 Set All (SETAL) Instruction
The SETAL instruction allows the user to write ‘0xFF’
to the entire memory array with one command. Note
that the write enable latch (WEL) must first be set by
issuing the WREN instruction.
Once the write enable latch is set, the user may
proceed with issuing a SETAL instruction (including
the header and device address bytes). Immediately
after the NoMAK bit has been transmitted by the host,
the internal write cycle is initiated, during which time all
words of the memory array are written to ‘0xFF’.
The SETAL instruction is ignored if either of the Block
Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or
all of the array is protected.
FIGURE 5-9: SET ALL COMMAND SEQUENCE
Note: The ERAL instruction must be
terminated with a NoMAK following the
command byte. If a NoMAK is not
received at this point, the command will
be considered invalid, and the device
will go into Idle mode without
responding with a SAK or executing the
command.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 110110 0
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
Note: The SETAL instruction must be
terminated with a NoMAK following the
command byte. If a NoMAK is not
received at this point, the command will
be considered invalid, and the device
will go into Idle mode without
responding with a SAK or executing the
command.
1 101010 0
Start Header
SCIO
Device Address
MAK
0 0(1)
00101 0
MAK
Command
1 100110 1
NoMAK
NoSAK
SAK
Standby Pulse
SCIO
SAK
Twc
Note 1: For the 11XXXX1, this bit must be a ‘1’.
11AAXXX/11LCXXX
DS20002067K-page 18
2011-2023 Microchip Technology Inc. and its subsidiaries
6.0 DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The Write Enable Latch (WEL) is reset on power-
up
• A Write Enable (WREN) instruction must be issued
to set the write enable latch
• After a write, ERAL, SETAL or WRSR command,
the write enable latch is reset
• Commands to access the array or write to the
STATUS register are ignored during an internal
write cycle and programming is not affected
7.0 POWER-ON STATE
The 11AAXXX/11LCXXX powers on in the following
state:
• The device is in low-power Shutdown mode,
requiring a low-to-high transition on SCIO to enter
Idle mode
• The Write Enable Latch (WEL) is reset
• The internal Address Pointer is undefined
• A low-to-high transition, standby pulse and
subsequent high-to-low transition on SCIO (the
first low pulse of the header) are required to enter
the active state
.
TABLE 7-1: WRITE PROTECT FUNCTIONALITY MATRIX
WEL Protected Blocks Unprotected Blocks Status Register
0Protected Protected Protected
1Protected Writable Writable
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 19
11AAXXX/11LCXXX
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
I/P 13F
11AA160
2234
Example:
8-Lead PDIP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
11AA010 11AA010 11LC010 11LC010
11AA020 11AA020 11LC020 11LC020
11AA040 11AA040 11LC040 11LC040
11AA080 11AA080 11LC080 11LC080
11AA160 11AA160 11LC160 11LC160
11AA161 11AA161 11LC161 11LC161
Note: T = Temperature Grade (I, E)
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
11AAXXX/11LCXXX
DS20002067K-page 20
2011-2023 Microchip Technology Inc. and its subsidiaries
8-Lead SOIC
XXXXYYWW
XXXXXXXT
NNN
Example:
SN 2234
11AA160I
13F
3
e
8-Lead SOIC Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
11AA010 11AA010T 11LC010 11LC010T
11AA020 11AA020T 11LC020 11LC020T
11AA040 11AA040T 11LC040 11LC040T
11AA080 11AA080T 11LC080 11LC080T
11AA160 11AA160T 11LC160 11LC160T
11AA161 11AA161T 11LC161 11LC161T
Note: T = Temperature Grade (I, E)
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 21
11AAXXX/11LCXXX
8-Lead MSOP (150 mil) Example:
XXXXXXT
YWWNNN
11A01I
23413F
8-Lead MSOP Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
11AA010 11A01T 11LC010 11L01T
11AA020 11A02T 11LC020 11L02T
11AA040 11A04T 11LC040 11L04T
11AA080 11A08T 11LC080 11L08T
11AA160 11AAT 11LC160 11LAT
11AA161 11AA1T 11LC161 11LA1T
Note: T = Temperature Grade (I, E)
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
11AAXXX/11LCXXX
DS20002067K-page 22
2011-2023 Microchip Technology Inc. and its subsidiaries
8-Lead 2x3 TDFN Example:
XXX
YWW
NN
D51
234
13
8-Lead 2x3 TDFN Package Marking (Pb-Free)
Device I-Temp Marking Device I-Temp Marking E-Temp Marking
11AA010 D11 11LC010 D14 D15
11AA020 D21 11LC020 D24 D25
11AA040 D31 11LC040 D34 D35
11AA080 D41 11LC080 D44 D45
11AA160 D51 11LC160 D54 D55
11AA161 D5D 11LC161 D5G D5H
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 23
11AAXXX/11LCXXX
3-Lead SOT-23
XXNN
Example:
B513
3-Lead SOT-23 Package Marking (Pb-Free)
Device I-Temp Marking Device I-Temp Marking E-Temp Marking
11AA010 B1NN 11LC010 M1NN N1NN
11AA020 B2NN 11LC020 M2NN N2NN
11AA040 B3NN 11LC040 M3NN N3NN
11AA080 B4NN 11LC080 M4NN N4NN
11AA160 B5NN 11LC160 M5NN N5NN
11AA161 B0NN 11LC161 M0NN N0NN
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
11AAXXX/11LCXXX
DS20002067K-page 24
2011-2023 Microchip Technology Inc. and its subsidiaries
3-Lead TO-92 Package Marking (Pb-Free)
Device Line 1 Marking Device Line 1 Marking
11AA010 11A010 11LC010 11L010
11AA020 11A020 11LC020 11L020
11AA040 11A040 11LC040 11L040
11AA080 11A080 11LC080 11L080
11AA160 11A160 11LC160 11L160
11AA161 11A161 11LC161 11L161
Note: T = Temperature Grade (I, E)
3-Lead TO-92
T/XXXX
XXXXXX
Example:
YWW
NNN
I/TO
11A160
234
13F
3
e
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 25
11AAXXX/11LCXXX
4-Lead Chip Scale Package Marking (Pb-Free)
Device Line 1 Marking
11AA010 AW
11AA020 BW
11AA040 CW
11AA080 DW
11AA160 EW
11AA161 HW
4-Lead Chip Scale
NN
XW
Example:
13
E3
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note: Standard OTP marking consists of Microchip part number, year code, week
code and traceability code.
Note: For very small packages with no room for the JEDEC® designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
11AAXXX/11LCXXX
DS20002067K-page 26
2011-2023 Microchip Technology Inc. and its subsidiaries
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018-P Rev F Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
E1
c
C
PLANE
.010 C
1 2
N
D
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 27
11AAXXX/11LCXXX
Microchip Technology Drawing No. C04-018-P Rev F Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
- -
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(NOTE 5)
5. Lead design above seating plane may vary, based on assembly vendor.
11AAXXX/11LCXXX
DS20002067K-page 28
2011-2023 Microchip Technology Inc. and its subsidiaries
0.25 C DA–B
C
SEATING
PLANE
TOP VIEW
SIDE VIEW
VIEW A–A
0.10 C
0.10 C
Microchip Technology Drawing No. C04-057-SN Rev K Sheet 1 of 2
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
1 2
N
h
h
A1
A2
A
A
B
e
D
E
E
2
E1
2
E1
NOTE 5
NOTE 5
NX b
0.10 C A–B
2X
H
ș
c
ș2
4X ș1
4X ș1
(L1)
L
R1
R
VIEW C
SEE VIEW C
NOTE 1
D
0.10 C A–B
2X
0.10 C A–B
2X
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 29
11AAXXX/11LCXXX
Microchip Technology Drawing No. C04-057-SN Rev K Sheet 2 of 2
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
protrusions shall not exceed 0.15mm per side.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
4. Dimensioning and tolerancing per ASME Y14.5M
Notes:
5. Datums A & B to be determined at Datum H.
Foot Angle 0° – 8°
––0°Lead Angle
0.51–0.31bLead Width
0.25–0.17
c
Lead Thickness
1.27–0.40LFoot Length
0.50–0.25hChamfer (Optional)
4.90 BSCDOverall Length
3.90 BSCE1Molded Package Width
6.00 BSCEOverall Width
0.25–0.10A1Standoff
-–1.25A2Molded Package Thickness
1.75––AOverall Height
1.27 BSC
e
Pitch
8NNumber of Pins
MAXNOMMINDimension Limits
MILLIMETERSUnits
§
Footprint L1 1.04 REF
Mold Draft Angle 5° – 15°
ș
ș1
ș2
––0.07R1Lead Bend Radius
––0.07RLead Bend Radius
11AAXXX/11LCXXX
DS20002067K-page 30
2011-2023 Microchip Technology Inc. and its subsidiaries
RECOMMENDED LAND PATTERN
Microchip Technology Drawing C04-2057-SN Rev K
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
CContact Pad Spacing
Contact Pitch
MILLIMETERS
1.27 BSC
MIN
E
MAX
5.40
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
1.55
0.60
NOM
E
X1
C
Y1
SILK SCREEN
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 31
11AAXXX/11LCXXX
TOP VIEW
VIEW A–A
SIDE VIEW
Note:
http://www.microchip.com/packaging
For the most current package drawings, please see the Microchip Packaging Specification located at
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Microchip Technology Drawing C04-111-MS Rev F
A
B
0.25 C
2X 4 TIPS
0.25 C A-B D
A
A
0.20 H
2X
0.20 H
1 2
N
SEE DETAIL B
NOTE 1
C
0.10 C
H
8X
8X b
e
D
D
2
E
2
E
E1
2
E1
AA2
A1
SEATING
PLANE
2X
Sheet 1 of 2
D
11AAXXX/11LCXXX
DS20002067K-page 32
2011-2023 Microchip Technology Inc. and its subsidiaries
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1.
2.
Pin 1 visual index feature may vary, but must be located within the hatched area.
Dimensioning and tolerancing per ASME Y14.5M
Sheet 2 of 2
C
SEATING
PLANE
H
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Molded Package Width
Molded Package Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E1
A2
e
L
E
N
0.65 BSC
0.85
0.40
0.22
–
0.00
–
0.60
–
–
MILLIMETERS
MIN NOM
8
0.80
0.40
1.10
0.15
MAX
L1 0.95 REFFootprint
Overall Length D 3.00 BSC
Terminal Thickness c0.08 – 0.23
R
R1
ș
ș1
–0.07 –Lead Bend Radius
–0.07 –Lead Bend Radius
–0° 8°Foot Angle
–5° 15°Mold Draft Angle
0.75 0.95
4.90 BSC
3.00 BSC
DETAIL B
ș
c
4X ș1
4X ș1
L
(L1)
R
R1
3.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Microchip Technology Drawing C04-111-MS Rev F
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 33
11AAXXX/11LCXXX
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Contact Pitch
MILLIMETERS
0.65 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y
X
1.45
0.45
NOM
CContact Pad Spacing 4.40
Contact Pad to Contact Pad (X4) G1 2.95
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M1.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
E
C
Contact Pad to Contact Pad (X6) GX 0.20
X
Y
G1
GX
SILK SCREEN
8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Microchip Technology Drawing C04-2111-MS Rev F
11AAXXX/11LCXXX
DS20002067K-page 34
2011-2023 Microchip Technology Inc. and its subsidiaries
B
A
0.15 C
0.15 C
0.10 C A B
0.05 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
1 2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
1 2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
D
E
D2
E2
A
(A3)
A1
e
8X b
L
K
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 35
11AAXXX/11LCXXX
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOM
MILLIMETERS
0.50 BSC
2.00 BSC
3.00 BSC
0.20 REF
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Contact-to-Exposed Pad
Contact Thickness
Exposed Pad Width
Exposed Pad Length
4. Dimensioning and tolerancing per ASME Y14.5M
3. Package is saw singulated
2. Package may have one or more exposed tie bars at ends.
Notes:
Contact Width
Overall Width
Overall Length
Contact Length
Standoff
Number of Pins
Overall Height
Pitch
K 0.20
Units
N
e
A
Dimension Limits
D
A3
A1
b
D2
E2
E
L
0.20
1.35
1.25
0.25
0.00
0.70
MIN
--
0.25
0.30
1.30
1.40
1.35
0.30
0.45
1.45
8
0.75
0.02 0.05
0.80
MAX
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
11AAXXX/11LCXXX
DS20002067K-page 36
2011-2023 Microchip Technology Inc. and its subsidiaries
RECOMMENDED LAND PATTERN
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
1.50
1.60
MILLIMETERS
0.50 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.85
0.25
Microchip Technology Drawing No. C04-129-MN Rev. B
NOM
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
1 2
8
CContact Pad Spacing 2.90
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
C
E
X1
Y1
Y2
X2
EV
EV
ØV
SILK SCREEN
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 37
11AAXXX/11LCXXX
Microchip Technology Drawing C04-101-TO Rev D Sheet 1 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
3-Lead Plastic Transistor Outline (TO) [TO-92]
1
(DATUM B)
(DATUM A)
VIEW A-A
TOP VIEW
2
E
AL
3X b
e
D
c
N
A
A
SIDE VIEW
R
0.006 B A
11AAXXX/11LCXXX
DS20002067K-page 38
2011-2023 Microchip Technology Inc. and its subsidiaries
Microchip Technology Drawing C04-101-TO Rev D Sheet 2 of 2
3-Lead Plastic Transistor Outline (TO) [TO-92]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
2. Dimensioning and tolerancing per ASME Y14.5M
1. Dimensions D and E do not include mold flash or protrusions. Mold flash or
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
protrusions shall not exceed .005" per side.
Notes:
.022.014bLead Width
.021.014
c
Lead Thickness
.105.080RMolded Package Radius
.210.170AOverall Length
.205.175EOverall Width
.165.125DBottom to Package Flat
.050 BSC
e
Pitch
3NNumber of Pins
MAXMINDimension Limits
INCHESUnits
Tip to Seating Plane L .500 -
NOM
-
-
-
-
-
-
-
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 39
11AAXXX/11LCXXX
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DS20002067K-page 42
2011-2023 Microchip Technology Inc. and its subsidiaries
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 43
11AAXXX/11LCXXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 45
11AAXXX/11LCXXX
APPENDIX A: REVISION HISTORY
Revision K (03/23)
Updated formatting to current template; Replaced
terminology “Master” and “Slave” with “Host” and
“Client” respectively; Added Automotive PIS.
Revision J (04/11)
Added new Patent No.; Revised Table 1-2, Param Nos
3 and 4.
Revision H (03/10)
Added 4-lead Chip Scale package.
Revision G (12/09)
Added 11AA161/11LC161 device.
Revision F (10/09)
Added 3-lead TO-92 Package.
Revision E (09/08)
Updated UNI/O trademark; Revised Table 1-2,
parameters 3 and 5; Updated package drawings.
Revision D (04/08)
Revised document status to Preliminary; General
updates.
Revision C (03/08)
Removed patent pending notice; Revised Tables 1-1
and 1-2; Section 3.3 (bullet 3) and 3.7 (bullet 2);
Product ID System.
Revision B (01/08)
Revised SOT-23 Package Type; Revised DFN
package to TDFN; Section 3.3 (added new bullet item);
Section 4.5 note; Table 7-1.
Revision A (10/07)
Original release of this document.
11AAXXX/11LCXXX
DS20002067K-page 46
2011-2023 Microchip Technology Inc. and its subsidiaries
NOTES:
2011-2023 Microchip Technology Inc. and its subsidiaries
DS20002067K-page 47
11AAXXX/11LCXXX
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Cus-
tomer Change Notification” and follow the registra-
tion instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support

Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: 11LC160

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