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ENT-AN1005
Application Note
IEEE 1588v2 Support in the Microsemi PHY API
Released
2016
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 1.1 ........................................................................................................................................
1.2 Revision 1.0 ........................................................................................................................................
2 IEEE 1588v2 Support in the Microsemi PHY API ............................................................................ 2
3 Feature Description ....................................................................................................................... 3
4 Functional Description ................................................................................................................... 7
4.1 FIFO .....................................................................................................................................................
4.1.1 Enable ...................................................................................................................................................... 7
4.1.2 FIFO Overflow_Underflow Indication ...................................................................................................... 7
4.2 Analyzer ..............................................................................................................................................
4.2.1 Enable_Disable ........................................................................................................................................ 7
4.2.2 Encapsulation Protocol(s) ........................................................................................................................ 7
4.2.3 Application Protocol(s) and Modes ......................................................................................................... 7
4.2.4 Operation Mode ...................................................................................................................................... 8
4.2.5 FrameSignature ..................................................................................................................................... 12
4.3 Timestamp Block .............................................................................................................................. 1
4.3.1 LocalLatency .......................................................................................................................................... 13
4.3.2 PathDelay .............................................................................................................................................. 13
4.3.3 DelayAsymmetry ................................................................................................................................... 14
4.3.4 Correction Field Overflow Indication .................................................................................................... 14
4.4 LocalTimeCounter ............................................................................................................................. 14
4.4.1 PtpTime ................................................................................................................................................. 14
4.4.2 SavedPtpTime ........................................................................................................................................ 14
4.4.3 LocalClockAdjustment ........................................................................................................................... 15
4.4.4 LocalClockIncrementDecrement ........................................................................................................... 15
4.4.5 LocalClockFrequency ............................................................................................................................. 15
4.5 Rewriter ............................................................................................................................................ 1
4.5.1 PreambleShrink ..................................................................................................................................... 15
4.5.2 StatisticCounters ................................................................................................................................... 15
4.6 TimestampFIFO ................................................................................................................................. 1
4.6.1 TxTimestampMode ............................................................................................................................... 15
4.6.2 TxTimestamps ....................................................................................................................................... 15
4.6.3 TxTimestampFifo Not Empty Indication ................................................................................................ 16
4.6.4 TxTimestampFifo Overflow Indication .................................................................................................. 16
4.6.5 TxTimestampFifo AgeTime .................................................................................................................... 16
4.6.6 RxTimestamp ......................................................................................................................................... 16
4.6.7 RxTimestampMode ............................................................................................................................... 16
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1
4.7 Module Bring-Up .............................................................................................................................. 1
4.7.1 Cold_Warm Restart ............................................................................................................................... 16
4.8 Other Functions ................................................................................................................................ 1
4.9 Control Module (PTP Engine) ........................................................................................................... 16
4.9.1 Module Management ............................................................................................................................ 17
4.9.2 ClockRate Management ........................................................................................................................ 17
4.9.3 Multiple Timing Domain Support .......................................................................................................... 19
4.9.4 CLI .......................................................................................................................................................... 19
4.10 Distributed Control Module ........................................................................................................... 19
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 1.1
The following is a summary of the changes in revision 2.0 of this document.
Formatting was updated. For more information, see Table 1–Table 6.
Information in Table 8 was updated.
1.2 Revision 1.0
Revision 1.0 was the first publication of this document.
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 2
2 IEEE 1588v2 Support in the Microsemi PHY API
This application note lists all Microsemi PHY API features related to IEEE 1588v2 support in Microsemi
PHYs and is relevant for 1588 API customers, developers, and architects.
The documents for the following products are available for reference: VSC8492 Dual Channel Universal
10G PHY or 10 GbE PHY with OTN/FEC and IEEE 1588; VSC8494 Quad Channel Universal 10G PHY or 10
GbE PHY with OTN/FEC and IEEE 1588; VSC8488-15 Dual Channel WAN/LAN/Backplane XAUI to SFP+/KR
Transceiver; VSC8487-15 WAN/LAN/Backplane XAUI to SFP+/KR Transceiver; and the datasheet section
on IEEE 1588v2 PTP/ITU-T Y.1731 OAM timestamp update block. In addition, consult the ITU-T G.8265.1
[IEEE 1588 profile for telecom (frequency delivery without support from network nodes)] and IEEE
Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems (IEEE Std 1588-2008) standards.
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 3
3 Feature Description
The Microsemi 1588 PHY API provides an interface between different Microsemi hardware components
and applications—it is a hardware abstraction layer. The API is responsible for setting up the hardware
registers in the different 1588 PHY implementations. Possible applications include the Microsemi
precision time protocol (PTP) engine or the customer's own applications. The Microsemi PTP engine
implements the different PTP clock types defined in 1588 and G8265.1. The Microsemi PTP engine also
has an interface for calling customer-defined offset and delay filters.
Figure 1 • 1588 API and Environment
The following two illustrations show typical applications where the API is used. For a more detailed
description of the components, please see the device datasheet. The following illustration shows a one-
step end-2-end (E2E) transparent clock (TC) application.
Figure 2 • Typical TC Application
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 4
In this application, the API resides in the linecard control processor and sets up the PTP packet
processing in PHYs. When this setup is done, the PHYs do all the PTP processing. Assuming that the
system clock operates in free-running mode, a software PTP engine is not needed. If the system clock
has to be syntonized to an external PTP master, a PTP engine has to be implemented in the system
control processor to perform the syntonization. The following illustration shows a one-step boundary
clock (BC) application.
Figure 3 • Typical BC Application
In this application, the API resides in the linecard control processor and sets up the PTP packet
processing in PHYs. When this setup is done, the PHYs do all the PTP timestamping. The boundary clock
PTP engine is implemented on the system card. All the PTP packets intended for the boundary clock are
sent from the switch fabric to the PTP engine. The PTP engine processes the PTP messages and performs
the system clock synchronization. The timestamping functionality exists in both the ingress and egress
paths. Different setups are done on the two paths. The 1588 API is responsible for setting up the
hardware registers in the 1588 PHYs. The following tables briefly describe the hardware interface.
Where possible, the names in parentheses refer to interface names in the device datasheet.
Table 1 • PCS+PMA and Delay FIFO
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
Enable Enable/disable the timestamping feature, and hereby the delay FIFO.
FifoOfSticky Sticky bit indicating a FIFO overflow.
FifoUfSticky Sticky bit indicating a FIFO underflow.
Table 2 • Analyzer
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
FieldMatchPattern Configure which fields to match in the packet, which depends on the encapsulation layers, and what
action to perform in case of a match. The pattern match is done at two levels: first the protocol flow is
identified, and then the protocol action is identified. The software supports many protocol flows and
action matches supported by the hardware. The current hardware version supports 8 protocol flows,
with 8 protocol actions per flow. The FieldMatchPattern also defines the encapsulation protocol(s)
and the application protocol. This component is shown in the following illustration.
FlowEnable Enable/disable a flow in the analyzer.
ActionMatch Set action pattern match (both ingress and egress). The match includes: 64-bit FlowMatch and
Flowmask and a domain range. For more information, please see the device datasheet.
Action Set action per pattern match (both ingress and egress). The action includes command, delay
asymmetry action, save option, rewrite offset and size, clear offset, and size flag offset.
FrameSignatureSet Set frame signature per pattern match. The frame signature, up to 15 bytes, is selected from different
positions in the packet (MAC: SA, DA; IP: SA, DA; PTP (OAM) header bytes).
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 5
Figure 4 • Field Match Pattern
Table 3 • Timestamp Block
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
Local_correction_i Local_latency on ingress path. Unit: ns. (local_correction)
Path_delay Path delay ingress. Unit: ns.
Local_correction_e Local_latency on egress path. Unit: ns. (local_correction)
Asymmetry Path delay asymmetry. Unit: sub-ns.
Correction_field_too_big Indication from hardware correction field overflows.
Table 4 • Rewriter
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
PreambleShrink Enable/disable preamble shrink.
Error_preamble_cnt Count number of frames with preambles too short to shrink when PreambleShrink is set.
Error_FCS_CNT Count of PTP frames with FCS errors.
Mod_frame_cnt 32-bit counter that counts the number of frames that have been modified.
Table 5 • Timestamp FIFOs
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
timestamp_FIFO
block
Handle egress.
si_ena_i Enable the timestamp FIFO serial interface. When not enabled, the timestamps can be read from the
normal CPU interface. When serial interface is enabled, the timestamps are pushed out on a SPI
interface.
TimeStampGet Get timestamp, including a frame identifier (signature).
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 6
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
TimeStampSticky Sticky bit indicating that the TimestampFIFO is not empty. There is also a watermark-based sticky that
indicates a configurable fill level of the TimestampFIFO.
Fifo_overflow Indicates that a TimestampFIFO overflow has occurred. (ts_overflow_o)
TimeStamp indicates timestamp format defined in [1588] (48-bit unsigned integer seconds, 32-bit
unsigned integer nanoseconds).
Table 6 • Local Time Counter
Name
Name
Name
NameName Description
Description
Description
DescriptionDescription
LocalTime Load local time to be synchronized for all modules in a node. Includes gating the load/save signal.
(Local_Time is 10 bytes and the standard PTP timestamp.)
LoadEnable Synchronize the local time to the value written to LocalTime by setting the load/save pin. Includes
gating the load signal.
CurrentTime Register with the current time latched by setting the load/save pin. Includes gating the save signal.
ClockIncrements Configure input clock rate.
AdjustableCounter Adjust clock rate. If the clocks inputs are not synchronized to a master clock, a local clock rate adjust
mechanism can adjust the rate.
IncCounter Increment timer adjusts timing skew (by one ns).
DecCounter Increment timer adjusts timing skew (by one ns).
ClockPulseWidth Configure 1 PPS clock output pulse width (duty cycle).
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 7
4 Functional Description
The following section provides a functional overview of the API.
4.1 FIFO
4.1.1 Enable
The timestamp processing can be enabled/disabled hitless, which means packets are not lost when
enabling or disabling the TSU.
HW ref: Enable.
4.1.2 FIFO Overflow_Underflow Indication
If the FIFO overflows or underflows, it is reported as an event. The software will not perform any
consequent action.
HW ref: FifoOfSticky, FifoUfSticky.
4.2 Analyzer
4.2.1 Enable_Disable
The analyzer flow setup is changed in a series of steps; therefore, the flow in the analyzer during this
sequence is disabled to avoid erroneous packet processing based on an incomplete setup. This is
implicitly done by the API when the encapsulation is changed.
HW ref: FlowEnable
4.2.2 Encapsulation Protocol(s)
Add/remove a protocol encapsulation that is supported by the system.
Up to n (n is defined by HW implementation, currently n is 8) protocol encapsulation flows can be active
at the same time. The API always supports the number of encapsulations supported by the actual HW
implementation.
For a list of supported protocol encapsulations, please see the device datasheet.
HW ref: FieldMatchPattern.
4.2.3 Application Protocol(s) and Modes
Set/get the application protocol(s) and modes that are supported by the system.
This document only covers 1588v2 protocol support. For other application protocols that are supported,
please see the device datasheet. The API maps the encapsulation protocol and application protocol to a
setup of the five comparators in analyzer.
When 1588 PTP protocol is selected the actions to be performed on each PTP event type depends on
the mode of the node (Boundary clock/Transparent clock, E2E/P2p delay measurement method). The
actions in the different modes are shown in .Actions as a Function of Operation Modes Table
HW ref: FieldMatchPattern.
Some examples of pattern match are as follows:
1588 PTP boundary clock, PTP over Ethernet:
Ethertype = 0x88f7; → packet is a PTP message.
1588 PTP boundary clock, PTP over UDP over IP4 over otag: VLAN1 over Ethernet:
TPID = 0x8100; VID = 1; Ethertype = 0x0800; Protocol = 17; Port = \[319...320\] ? pack
1588 PTP boundary clock, PTP over UDP over IP6 over otag: VLAN1 itag: VLAN2 over Ethernet:
TPID = 0x8100; VID = 1; TPID = 0x8100; VID = 2; Ethertype = 0x86dd; Next Header = 17;
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 8
TPID means tag protocol identifier for VLAN tags and VID means VLAN identifier.
4.2.4 Operation Mode
Set/get the operation mode(s) for each interface. Individual modes can be set—for example, per timing
domain. The number of analyzer entries that can be set up is hardware implementation specific.
The operation mode consists of mode and delay_method.
The following modes are supported:
BC One-step
It is not necessary to configure a port as master or slave. The mode is determined by the event
types that are sent and received.
BC Two-step
TC One-step
TC Two-step
The following delay methods are supported:
End-2-end (E2E)
Peer-2-peer (P2P)
The API sets the desired actions in the analyzer according to the mode and delay method.
HW ref: ActionMatch, Action, PreambleShrink
The pattern match depends on the node type and the PTP profile. Some examples are as follows (it is
assumed that the encapsulation protocol match has identified the packet as a PTP packet):
Multicast one-step 1588 PTP boundary clock ingress port
message_type = Sync(0), versionPTP = 2, domainNumber = 'mydomain', → write(RX_timestamp,
reserved); add(Asymmetry, correctionField).
message_type = DelayReq(1), versionPTP = 2, domainNumber = 'mydomain' → write(RX_timestamp,
reserved).
message_type > 1 → packet is P2P event or a PTP general message, no modification is done.
Multicast one-step 1588 PTP boundary clock egress port:
message_type = Sync(0), versionPTP = 2, domainNumber = 'mydomain' → write(TX_timestamp,
originTimestamp).
message_type = DelayReq(1), versionPTP = 2, domainNumber = 'mydomain' → save (TX_timestamp,
TXFiFo);sub((Asymmetry, correctionField).
message_type > 1 → packet is P2P event or a PTP general message, no modification is done.
Different TX_timestamp formats exist in the hardware. TX_timestamp = Raw_timestamp +
Local_correction_e + Variable_latency (in the egress direction).
The Variable_latency is an internal hardware value predicted from the PCS logic (not available
from software).
1588 PTP one-step transparent P2P clock ingress port:
message_type = Sync(0), versionPTP = 2 → write(RX_timestamp, Reserved); add (PathDelay +
Asymmetry, correctionField).
message_type = Delay_Req(1), versionPTP = 2 → no operation.
message_type = Pdelay_Req(2), versionPTP = 2 → write(RX_timestamp, Reserved).
message_type = Pdelay_Resp(3), versionPTP = 2 → write(RX_timestamp, Reserved); add
(Asymmetry, correctionField).
message_type > 3, versionPTP = 2 → no operation.
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 9
Different RX_timestamp formats exist in the hardware. The version used depends on the field that
it is written to (reserved field, correctionField or originTimestamp). These different formats are
invisible for the software. RX_timestamp = Raw_timestamp – Local_correction_i –Variable_latency
(in the ingress direction).
1588 PTP one-step transparent P2P clock egress port:
message_type = Sync(0) | Pdelay_Resp(3), versionPTP = 2 → Subtract_add(TX_timestamp, Reserved,
correctionField).
message_type = Pdelay_Req(2), versionPTP = 2 → write(TX_timestamp - Asymmetry, TXFiFo).
message_type = Delay_Req(1), versionPTP = 2 → no operation.
message_type > 3, versionPTP = 2 → no operation.
The following code shows how the multicast one-step 1588 PTP boundary, E2E Sync ingress example is
mapped to the hardware registers defined in the device datasheet.
Action match:
PTP_Flow_Match = , 0x0002 0000 0100 0000 /* assuming 'mydomain' = 1 */
PTP_Flow_Mask = FF00 ,0x0F0F 0000 0000
PTP_Flow_Oset = 0
PTP_Domain_Range_Enable = 0
Action:
PTP_Clear_ChkSum = ,1
PTP_Update_ChkSum = ,0
PTP_Action_Command = WRITE
PTP_Correction_Field_Oset = 8
PTP_Time_Storage_Field_Oset = 16
PTP_Add_Delay_Asymmetry_Enable = 1
PTP_Modied_Frame_Byte_Oset = 6/* ag eld */
PTP_Modied_Frame_Byte_Update = 1
The following definitions are used in the following table to show how the delay method mode maps to
an action:
Reserved—32-bit reserved field in the PTP packet.
Asymmetry—the configured delay Asymmetry for a port.
RX_timestamp—registered receive time (32-bit ns only), including the configured ingress latency.
OriginTimestamp—originTimestamp field in the sync and Delay_Req messages.
TX_timestamp—registered transmit time for a packet (48-bit second counter and 32-bit ns counter),
including the configured egress latency.
CorrectionField—correction field in the PTP packet.
PathDelay—configured ingress PTP delay (measured by software).
Subtract_add(x,y,z) means z += (x–y)
Table 7 • Actions as a Function of Operation Modes
E2E
E2E
E2E
E2EE2E P2P
P2P
P2P
P2PP2P
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 10
E2E
E2E
E2E
E2EE2E P2P
P2P
P2P
P2PP2P
BC
/OC
One-
step
Ingress{Sync};write(RX_timestamp, Reserved); add
(Asymmetry, correctionField)
Ingress{DelayReq};write(RX_timestamp, Reserved)
Egress {Sync}; write(TX_timestamp, originTimestamp)
Egress{DelayReq};save (TX_timestamp, TXFiFo);sub
((Asymmetry, correctionField)
Ingress{Sync};write(RX_timestamp, Reserved); add
(PathDelay+Asymmetry, correctionField)
Egress {Sync}; write(TX_timestamp, originTimestamp)
{Pdelay_Req, Pdelay_Resp} same as TC
BC
/OC
Two-
step
Ingress{Sync};write(RX_timestamp, Reserved); add
(Asymmetry, correctionField)
Ingress{DelayReq};write(RX_timestamp, Reserved)
Egress {Sync}; save(TX_timestamp, TXFifo)
Egress{DelayReq};save (TX_timestamp, TXFiFo);sub
((Asymmetry, correctionField)
Ingress{Sync};write(RX_timestamp, Reserved); add
(Asymmetry, correctionField)
Egress {Sync}; save(TX_timestamp, TXFifo)
{Pdelay_Req, Pdelay_Resp} same as TC
TC
One-
step
Ingress {Sync, PdelayResp }: write(RX_timestamp,
Reserved); add(Asymmetry, correctionField)
Ingress { DelayReq, PdelayReq }: write(RX_timestamp,
Reserved)
Egress {Sync, PdelayResp }: Subtract_add(TX_timestamp,
Reserved, correctionField)
Egress { DelayReq, PdelayReq }: Subtract_add
(TX_timestamp - Asymmetry, Reserved, correctionField)
Ingress {Sync}: write(RX_timestamp, Reserved); add
(PathDelay + Asymmetry, correctionField);
Ingress {Pdelay_Req}: write(RX_timestamp, Reserved)
Ingress {Pdelay_Resp}: write(RX_timestamp,
Reserved); add (Asymmetry, correctionField);
Egress {Sync, Pdelay_Resp }: Subtract_add
(TX_timestamp, Reserved, correctionField)
Egress {Pdelay_Req} save(TX_timestamp -
Asymmetry, TXFiFo)
TC
Two-
step
Ingress {Sync, DelayReq, PdelayReq, PdelayResp }: write
(RX_timestamp, Reserved)
Egress {Sync, DelayReq, PdelayReq, PdelayResp}: save
(TX_timestamp, TXFiFo)
Ingress {Sync, Pdelay_Req, Pdelay_Resp }: write
(RX_timestamp, Reserved);
Egress { Sync, Pdelay_Resp, Pdelay_Req} save
(TX_timestamp, TXFiFo)
In a 2-step transparent clock, the PTP engine does the asymmetry corrections.
In the previous table, the RX_timestamp is stored in the reserved field. Other options exist that are not
shown in the table. For example, RX_timestamp can overwrite the FCS field and append a new FSC field.
When a timestamp is saved in the timestamp FIFO, a configuration specific (this is configured in the
analyzer) identifier is assigned to the timestamp. The following illustrations show the previously
described process.
IEEE 1588v2 Support in the Microsemi PHY API
VPPD-02802 ENT-AN1005 Application Note Revision 1.1 11
Figure 5 • One-Step Boundary Clock
Figure 6 • Two-Step Boundary Clock
The Dealy_Req operations in the previous two illustrations are only valid for E2E mode.

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Model: VSC8582

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