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© 2011 Microchip Technology Inc. DS61126F-page 27-1
USB On-The-Go
(OTG)
27
Section 27. USB On-The-Go (OTG)
HIGHLIGHTS
This section of the manual contains the following major topics:
27.1 Introduction .................................................................................................................. 27-2
27.2 Control Registers ......................................................................................................... 27-4
27.3 Operation ................................................................................................................... 27-36
27.4 Host Mode Operation................................................................................................. 27-51
27.5 Interrupts.................................................................................................................... 27-59
27.6 I/O Pins ...................................................................................................................... 27-62
27.7 Operation in Debug and Power-Saving Modes.......................................................... 27-64
27.8 Effects of a Reset....................................................................................................... 27-66
27.9 Related Application Notes.......................................................................................... 27-67
PIC32 Family Reference Manual
DS61126F-page 27-2 © 2011 Microchip Technology Inc.
27.1 INTRODUCTION
The PIC32 USB OTG module includes the following features:
USB Full-Speed Support for Host and Device
Low-Speed Host Support
USB On-The-Go (OTG) Support
Integrated Signaling Resistors
Integrated Analog Comparators for VBUS Monitoring
Integrated USB Transceiver
Transaction Handshaking Performed by Hardware
Endpoint Buffering Anywhere in System RAM
Integrated Bus Master to Access System RAM and Flash
USB OTG module does not require the PIC32 DMA module for its operation
The USB OTG module contains analog and digital components to provide a USB 2.0 full-speed
and low-speed embedded host, full-speed device, or OTG implementation with a minimum of
external components. This module in Host mode is intended for use as an embedded host and
therefore does not implement a UHCI or OHCI controller.
The USB OTG module consists of the clock generator, the USB voltage comparators, the trans-
ceiver, the Serial Interface Engine (SIE), a dedicated USB Bus Master, pull-up and pull-down
resistors and the register interface. A block diagram of the USB OTG module is presented in
Figure 27-1.
The clock generator provides the 48 MHz clock, which is required for USB full-speed and
low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to
determine the state of the bus. The transceiver provides the analog translation between the USB
bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint
buffers, and generates the hardware protocol for data transfers. The USB Bus Master transfers
data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors
eliminate the need for external signaling components. The register interface allows the CPU to
configure and communicate with the module.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “USB On-The-Go (OTG)” chapter
in the current device data sheet to check whether this document supports the device
you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
IMPORTANT: The implementation and use of the USB specifications, as well as other
third-party specifications or technologies, may require licensing; including,
but not limited to, USB Implementers Forum, Inc. (also referred to as
USB-IF). The user is fully responsible for investigating and satisfying any
applicable licensing obligations.
© 2011 Microchip Technology Inc. DS61126F-page 27-3
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
Figure 27-1: PIC32 USB OTG Interface Diagram
Note 1: PB clock is only available on this pin for select EC modes.
2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz UFIN 5 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB OTG module is disabled.
9: Pin is pulled high internally when USB OTG module is enabled.
OSC1
OSC2
Primary Oscillator
8 MHz Typical
FRC
Oscillator
TUN<5:0>(4)
PLL
48 MHz USB Clock(7)
Div x
UPLLEN(6)
(PBOUT)(1)
UFRCEN(3)
(POSC)
FUPLLIDIV(6)
UFIN(5)
Div 2
VUSB
D+(2)
D-(2)
ID(8,9)
VBUS
Transceiver
SIE
VBUSON(8)
Comparators
USB
SRP Charge
SRP Discharge
Registers
and
Control
Interface
Transceiver Power 3.3V
To Clock Generator for Core and Peripherals
Sleep or Idle
Sleep
USBEN
USB Suspend
CPU Clock Not POSC
USB OTG Module
Voltage
System
RAM
USB Suspend
Full-Speed Pull-up
Host Pull-down
Low-Speed Pull-up
Host Pull-down
ID Pull-up
Bus
Master
24xPLL
PIC32 Family Reference Manual
DS61126F-page 27-4 © 2011 Microchip Technology Inc.
27.2 CONTROL REGISTERS
The USB OTG module includes the following Special Function Registers (SFRs):
U1OTGIR: USB OTG Interrupt Status Register
This register records changes on the ID, data and VBUS pins, enabling software to determine
which event caused an interrupt. The interrupt bits are cleared by writing a 1 to the corresponding
interrupt.
U1OTGIE: USB OTG Interrupt Enable Register
This register enables the corresponding interrupt status bits defined in the U1OTGIR register
to generate an interrupt.
U1OTGSTAT: USB OTG Status Register
This register provides access to the status of the VBUS voltage comparators and the
debounced status of the ID pin.
U1OTGCON: USB OTG Control Register
This register controls the operation of the VBUS pin, and the pull-up and pull-down resistors.
U1PWRC: USB Power Control Register
This register controls the power-saving modes, as well as the module enable/disable
control.
U1IR: USB Interrupt Register
This register contains information on pending interrupts. Once an interrupt bit is set, it can
be cleared by writing a ‘1’ to the corresponding bit.
U1IE: USB Interrupt Enable Register(1)
The values in this register provide gating of the various interrupt signals onto the USB inter-
rupt signal. These values do not interact with the USB OTG module. Setting any of these
bits enables the corresponding interrupt source in the U1IR register.
U1EIR: USB Error Interrupt Status Register
This register contains information on pending error interrupt values. Once an interrupt bit is
set, it can be cleared by writing a ‘1’ to the corresponding bit.
U1EIE: USB Error Interrupt Enable Register(1)
The values in this register provide gating of the various interrupt signals onto the USB
interrupt signal. These values do not interact with the USB OTG module. Setting any of
these bits enables the respective interrupt source in the U1EIR register, if the UERRIE bit
(U1IE<1>) is also set.
U1STAT: USB Status Register(1)
U1STAT is a 16-deep First In, First Out register (FIFO). It is read-only by the CPU and
read/write by the USB OTG module. U1STAT is only valid when the TRNIF bit (U1IR<3>) is
set.
U1CON: USB Control Register
This register provides miscellaneous control and information about the module.
U1ADDR: USB Address Register
U1ADDR is a read/write register from the CPU side and read-only from the USB OTG mod-
ule side. Although the register values affect the settings of the USB OTG module, the
content of the registers does not change during access.
In Device mode, this address defines the USB device address as assigned by the host dur-
ing the SETUP phase. The firmware writes the address in response to the SETUP request.
The address is automatically reset when a USB bus Reset is detected. In Host mode, the
module transmits the address provided in this register with the corresponding token packet.
This allows the USB OTG module to uniquely address the connected device.
© 2011 Microchip Technology Inc. DS61126F-page 27-5
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
U1FRML: USB Frame Number Low Register and U1FRMH: USB Frame Number High
Register
U1FRML and U1FRMH are read-only registers. The frame number is formed by concatenat-
ing the two 8-bit registers. The high-order byte is in the U1FRMH register, and the low-order
byte is in U1FRML.
U1TOK: USB Token Register
U1TOK is a read/write register required when the module operates as a host. It is used to
specify the token type, PID<3:0> (Packet ID), and the endpoint, EP<3:0>, being addressed
by the host processor. Writing to this register triggers a host transaction.
U1SOF: USB SOF Threshold Register
U1SOF is a read/write register that contains the count bits of the Start of Frame (SOF)
threshold value, and are used in Host mode only.
To prevent colliding a packet data with the SOF token that is sent every 1 ms, the USB OTG
module will not send any new transactions within the last U1SOF byte times. The USB OTG
module will complete any transactions that are in progress. In Host mode, the SOF interrupt
occurs when this threshold is reached, not when the SOF occurs. In Device mode, the inter-
rupt occurs when a SOF is received. Transactions started within the SOF threshold are held
by the USB OTG module until after the SOF token is sent.
U1BDTP1: USB BDT Register, U1BDTP2: USB BDT PAGE 2 Register, and U1BDTP3:
USB BDT PAGE 3 Register
These registers are read/write registers that define the upper 23 bits of the 32-bit base
address of the Buffer Descriptor Table (BDT) in the system memory. The BDT is forced to
be 512 byte-aligned. This register allows relocation of the BDT in real time.
U1CNFG1: USB Configuration 1 Register
U1CNFG1 is a read/write register that controls the Debug and Idle behavior of the module.
The register must be preprogrammed prior to enabling the module.
U1EP0-U1EP15: USB Endpoint Control Registers
These registers control the behavior of the corresponding endpoint.
27.2.1 Associated Registers
Refer to Section 6. “Oscillators” (DS61112) for information on the register bits used to enable
the USB PLL and/or USB FRC clock sources.
Refer to Section 8. “Interrupts” (DS61108) for information on the register bits used to enable
and identify the USB OTG module interrupts.
Refer to Section 32. “Configuration” (DS61124) for information on the configuration bits used
to enable the USB PLL and set the appropriate divisor. This section also describes the bits that
can be used to reclaim the USBID and VBUSON pins if the USB OTG module will only be operated
in a mode that does not require them.
27.2.2 Clearing USB OTG Interrupts
Unlike other device-level interrupts, the USB OTG interrupt status flags are not freely writable in
software. All USB OTG flag bits are implemented as hardware-set-only bits. These bits can only
be cleared in software by writing a ‘1’ to their locations. Writing a ‘0’ to a flag bit has no effect.
Note: Throughout this section, a bit that can only be cleared by writing a ‘1’ to its location
is referred to as “Write to clear bit”. In register 1descriptions, this function is
indicated by the descriptor ‘K’.
PIC32 Family Reference Manual
DS61126F-page 27-6 © 2011 Microchip Technology Inc.
27.2.3 Register Summary
All USB OTG registers are summarized in Table 27-1.
Table 27-1: USB OTG Register Summary(1)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U1OTGIR 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF VBUSVDIF
U1OTGIE 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE VBUSVDIE
U1OTGSTAT 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 ID LSTATE SESVD SESEND VBUSVD
U1OTGCON 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS
U1PWRC 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 UACTPND USLPGRD USBBUSY(2) — USUS-
PEND
USBPWR
U1IR 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF
DETACHIF
U1IE 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE URSTIE
DETACHIE
U1EIR 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF CRC5EF PIDEF
EOFEF
U1EIE 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE PIDEE
EOFEE
U1STAT 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 ENDPT<3:0> DIR PPBI —
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
© 2011 Microchip Technology Inc. DS61126F-page 27-7
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
U1CON 31:24 —
23:16 — — — —
15:8 — — — —
7:0 JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN
TOKBUSY SOFEN
U1ADDR 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 LSPDEN DEVADDR<6:0>
U1BDTP1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRL<15:9>
U1FRML 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 FRML<7:0>
U1FRMH 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 — FRMH<2:0>
U1TOK 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 PID<3:0> EP<3:0>
U1SOF 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 CNT<7:0>
U1BDTP2 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRH<23:16>
U1BDTP3 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRU<31:24>
U1CNFG1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 UTEYE UOEMON USBFRZ USBSIDL UASUSPND(2)
U1EP0 31:24 —
23:16 — — — —
15:8 — — — —
7:0 LSPD RETRYDIS EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Table 27-1: USB OTG Register Summary(1) (Continued)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
PIC32 Family Reference Manual
DS61126F-page 27-8 © 2011 Microchip Technology Inc.
U1EP2 31:24 —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP3 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP4 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP5 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP6 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP7 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP8 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP9 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP10 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP11 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP12 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP13 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Table 27-1: USB OTG Register Summary(1) (Continued)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
© 2011 Microchip Technology Inc. DS61126F-page 27-9
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
U1EP14 31:24 —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP15 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Table 27-1: USB OTG Register Summary(1) (Continued)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
PIC32 Family Reference Manual
DS61126F-page 27-10 © 2011 Microchip Technology Inc.
27.2.4 Register Definitions
This section provides a detailed description of each USB OTG register.
Register 27-1: U1OTGIR: USB OTG Interrupt Status Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 31 bit 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 15 bit 8
R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 U-0 R/K-0
IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF VBUSVDIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-8 Unimplemented: Read as ‘0
bit 7 IDIF: ID State Change Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = Change in ID state detected
0 = No change in ID state detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
Write a ‘1’ to this bit to clear the interrupt.
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3 SESVDIF: Session Valid Change Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2 SESENDIF: B-Device VBUS Change Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1 Unimplemented: Read as ‘0
bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit
Write a ‘1’ to this bit to clear the interrupt.
1 = Change on the session valid input detected
0 = No change on the session valid input detected
© 2011 Microchip Technology Inc. DS61126F-page 27-11
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
Register 27-2: U1OTGIE: USB OTG Interrupt Enable Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — —
bit 31 bit 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE VBUSVDIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-8 Unimplemented: Read as ‘0
bit 7 IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5 LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state interrupt disabled
bit 4 ACTVIE: Bus Activity Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 3 SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2 SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 1 Unimplemented: Read as ‘0
bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt enabled
0 = A-VBUS valid interrupt disabled
PIC32 Family Reference Manual
DS61126F-page 27-12 © 2011 Microchip Technology Inc.
Register 27-3: U1OTGSTAT: USB OTG Status Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 31 bit 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
————————
bit 15 bit 8
R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0
ID LSTATE SESVD SESEND VBUSVD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-8 Unimplemented: Read as ‘0
bit 7 ID: ID Pin State Indicator bit
1 = No cable is attached or a type B cable has been plugged into the USB receptacle
0 = A “type A” OTG cable has been plugged into the USB receptacle
bit 6 Unimplemented: Read as ‘0
bit 5 LSTATE: Line State Stable Indicator bit
1 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has been stable for the previous 1 ms
0 = USB line state (U1CON<SE0> and U1CON<JSTATE>) has not been stable for the previous 1 ms
bit 4 Unimplemented: Read as ‘0
bit 3 SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2 SESEND: B-Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 1 Unimplemented: Read as ‘0
bit 0 VBUSVD: A-VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device
© 2011 Microchip Technology Inc. DS61126F-page 27-15
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
Register 27-6: U1IR: USB Interrupt Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
bit 31 bit 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — —
bit 15 bit 8
R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0 R/K-0
STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) URSTIF(5)
DETACHIF(6)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit K = Write ‘1’ to clear -n = Bit Value at POR: (0, 1, x = unknown)
bit 31-8 Unimplemented: Read as ‘0
bit 7 STALLIF: STALL Handshake Interrupt bit
Write a ‘1’ to this bit to clear the interrupt.
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction
In Device mode a STALL handshake was transmitted during the handshake phase of the transaction.
0 = STALL handshake has not been sent
bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)
Write a ‘1’ to this bit to clear the interrupt.
1 = Peripheral attachment was detected by the USB OTG module
0 = Peripheral attachment was not detected
bit 5 RESUMEIF: Resume Interrupt bit
(2)
Write a ‘1’ to this bit to clear the interrupt.
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4 IDLEIF: Idle Detect Interrupt bit
Write a ‘1’ to this bit to clear the interrupt.
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
Note 1: This bit is valid only if the HOSTEN bit is set (see Register 27-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.


Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: PIC32MX274F256D

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