Microchip PIC32MX274F256D Handleiding


Lees hieronder de 📖 handleiding in het Nederlandse voor Microchip PIC32MX274F256D (72 pagina's) in de categorie Niet gecategoriseerd. Deze handleiding was nuttig voor 39 personen en werd door 2 gebruikers gemiddeld met 4.5 sterren beoordeeld

Pagina 1/72
© 2011 Microchip Technology Inc. DS61126F-page 27-1
USB On-The-Go
(OTG)
27
Section 27. USB On-The-Go (OTG)
HIGHLIGHTS
This section of the manual contains the following major topics:
27.1 Introduction .................................................................................................................. 27-2
27.2 Control Registers ......................................................................................................... 27-4
27.3 Operation ................................................................................................................... 27-36
27.4 Host Mode Operation................................................................................................. 27-51
27.5 Interrupts.................................................................................................................... 27-59
27.6 I/O Pins ...................................................................................................................... 27-62
27.7 Operation in Debug and Power-Saving Modes.......................................................... 27-64
27.8 Effects of a Reset....................................................................................................... 27-66
27.9 Related Application Notes.......................................................................................... 27-67
PIC32 Family Reference Manual
DS61126F-page 27-2 © 2011 Microchip Technology Inc.
27.1 INTRODUCTION
The PIC32 USB OTG module includes the following features:
USB Full-Speed Support for Host and Device
Low-Speed Host Support
USB On-The-Go (OTG) Support
Integrated Signaling Resistors
Integrated Analog Comparators for VBUS Monitoring
Integrated USB Transceiver
Transaction Handshaking Performed by Hardware
Endpoint Buffering Anywhere in System RAM
Integrated Bus Master to Access System RAM and Flash
USB OTG module does not require the PIC32 DMA module for its operation
The USB OTG module contains analog and digital components to provide a USB 2.0 full-speed
and low-speed embedded host, full-speed device, or OTG implementation with a minimum of
external components. This module in Host mode is intended for use as an embedded host and
therefore does not implement a UHCI or OHCI controller.
The USB OTG module consists of the clock generator, the USB voltage comparators, the trans-
ceiver, the Serial Interface Engine (SIE), a dedicated USB Bus Master, pull-up and pull-down
resistors and the register interface. A block diagram of the USB OTG module is presented in
Figure 27-1.
The clock generator provides the 48 MHz clock, which is required for USB full-speed and
low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to
determine the state of the bus. The transceiver provides the analog translation between the USB
bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint
buffers, and generates the hardware protocol for data transfers. The USB Bus Master transfers
data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors
eliminate the need for external signaling components. The register interface allows the CPU to
configure and communicate with the module.
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “USB On-The-Go (OTG)” chapter
in the current device data sheet to check whether this document supports the device
you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
IMPORTANT: The implementation and use of the USB specifications, as well as other
third-party specifications or technologies, may require licensing; including,
but not limited to, USB Implementers Forum, Inc. (also referred to as
USB-IF). The user is fully responsible for investigating and satisfying any
applicable licensing obligations.
© 2011 Microchip Technology Inc. DS61126F-page 27-3
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
Figure 27-1: PIC32 USB OTG Interface Diagram
Note 1: PB clock is only available on this pin for select EC modes.
2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz UFIN 5 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB OTG module is disabled.
9: Pin is pulled high internally when USB OTG module is enabled.
OSC1
OSC2
Primary Oscillator
8 MHz Typical
FRC
Oscillator
TUN<5:0>(4)
PLL
48 MHz USB Clock(7)
Div x
UPLLEN(6)
(PBOUT)(1)
UFRCEN(3)
(POSC)
FUPLLIDIV(6)
UFIN(5)
Div 2
VUSB
D+(2)
D-(2)
ID(8,9)
VBUS
Transceiver
SIE
VBUSON(8)
Comparators
USB
SRP Charge
SRP Discharge
Registers
and
Control
Interface
Transceiver Power 3.3V
To Clock Generator for Core and Peripherals
Sleep or Idle
Sleep
USBEN
USB Suspend
CPU Clock Not POSC
USB OTG Module
Voltage
System
RAM
USB Suspend
Full-Speed Pull-up
Host Pull-down
Low-Speed Pull-up
Host Pull-down
ID Pull-up
Bus
Master
24xPLL
PIC32 Family Reference Manual
DS61126F-page 27-4 © 2011 Microchip Technology Inc.
27.2 CONTROL REGISTERS
The USB OTG module includes the following Special Function Registers (SFRs):
U1OTGIR: USB OTG Interrupt Status Register
This register records changes on the ID, data and VBUS pins, enabling software to determine
which event caused an interrupt. The interrupt bits are cleared by writing a 1 to the corresponding
interrupt.
U1OTGIE: USB OTG Interrupt Enable Register
This register enables the corresponding interrupt status bits defined in the U1OTGIR register
to generate an interrupt.
U1OTGSTAT: USB OTG Status Register
This register provides access to the status of the VBUS voltage comparators and the
debounced status of the ID pin.
U1OTGCON: USB OTG Control Register
This register controls the operation of the VBUS pin, and the pull-up and pull-down resistors.
U1PWRC: USB Power Control Register
This register controls the power-saving modes, as well as the module enable/disable
control.
U1IR: USB Interrupt Register
This register contains information on pending interrupts. Once an interrupt bit is set, it can
be cleared by writing a ‘1’ to the corresponding bit.
U1IE: USB Interrupt Enable Register(1)
The values in this register provide gating of the various interrupt signals onto the USB inter-
rupt signal. These values do not interact with the USB OTG module. Setting any of these
bits enables the corresponding interrupt source in the U1IR register.
U1EIR: USB Error Interrupt Status Register
This register contains information on pending error interrupt values. Once an interrupt bit is
set, it can be cleared by writing a ‘1’ to the corresponding bit.
U1EIE: USB Error Interrupt Enable Register(1)
The values in this register provide gating of the various interrupt signals onto the USB
interrupt signal. These values do not interact with the USB OTG module. Setting any of
these bits enables the respective interrupt source in the U1EIR register, if the UERRIE bit
(U1IE<1>) is also set.
U1STAT: USB Status Register(1)
U1STAT is a 16-deep First In, First Out register (FIFO). It is read-only by the CPU and
read/write by the USB OTG module. U1STAT is only valid when the TRNIF bit (U1IR<3>) is
set.
U1CON: USB Control Register
This register provides miscellaneous control and information about the module.
U1ADDR: USB Address Register
U1ADDR is a read/write register from the CPU side and read-only from the USB OTG mod-
ule side. Although the register values affect the settings of the USB OTG module, the
content of the registers does not change during access.
In Device mode, this address defines the USB device address as assigned by the host dur-
ing the SETUP phase. The firmware writes the address in response to the SETUP request.
The address is automatically reset when a USB bus Reset is detected. In Host mode, the
module transmits the address provided in this register with the corresponding token packet.
This allows the USB OTG module to uniquely address the connected device.
© 2011 Microchip Technology Inc. DS61126F-page 27-7
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
U1CON 31:24 —
23:16 — — — —
15:8 — — — —
7:0 JSTATE SE0 PKTDIS USBRST HOSTEN RESUME PPBRST USBEN
TOKBUSY SOFEN
U1ADDR 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 LSPDEN DEVADDR<6:0>
U1BDTP1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRL<15:9>
U1FRML 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 FRML<7:0>
U1FRMH 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 — FRMH<2:0>
U1TOK 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 PID<3:0> EP<3:0>
U1SOF 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 CNT<7:0>
U1BDTP2 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRH<23:16>
U1BDTP3 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 BDTPTRU<31:24>
U1CNFG1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 UTEYE UOEMON USBFRZ USBSIDL UASUSPND(2)
U1EP0 31:24 —
23:16 — — — —
15:8 — — — —
7:0 LSPD RETRYDIS EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP1 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Table 27-1: USB OTG Register Summary(1) (Continued)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
© 2011 Microchip Technology Inc. DS61126F-page 27-9
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
U1EP14 31:24 —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
U1EP15 31:24 — — — —
23:16 — — — —
15:8 — — — —
7:0 EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Table 27-1: USB OTG Register Summary(1) (Continued)
Register
Name
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
Legend: — = unimplemented, read as0. Address offset values are shown in hexadecimal.
Note 1: Not all registers may have associated SET, CLR, INV registers. Refer to the specific device data sheet for details.
2: This bit is not available on all devices. Refer to the specific device data sheet for details.
© 2011 Microchip Technology Inc. DS61126F-page 27-11
Section 27. USB On-The-Go (OTG)
USB On-The-Go
(OTG)
27
Register 27-2: U1OTGIE: USB OTG Interrupt Enable Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — —
bit 31 bit 24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE VBUSVDIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-8 Unimplemented: Read as ‘0
bit 7 IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5 LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state interrupt disabled
bit 4 ACTVIE: Bus Activity Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 3 SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2 SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 1 Unimplemented: Read as ‘0
bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt enabled
0 = A-VBUS valid interrupt disabled


Product specificaties

Merk: Microchip
Categorie: Niet gecategoriseerd
Model: PIC32MX274F256D

Heb je hulp nodig?

Als je hulp nodig hebt met Microchip PIC32MX274F256D stel dan hieronder een vraag en andere gebruikers zullen je antwoorden




Handleiding Niet gecategoriseerd Microchip

Handleiding Niet gecategoriseerd

Nieuwste handleidingen voor Niet gecategoriseerd