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 2007-2020 Microchip Technology Inc. DS70000185D-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 CAN Message Formats..................................................................................................... 4

3.0 Register Maps................................................................................................................... 8

4.0 CAN Registers ................................................................................................................ 15

5.0 CAN Message Buffers .................................................................................................... 34

6.0 Bit Timing ........................................................................................................................ 38

7.0 CAN Operating Modes.................................................................................................... 42

8.0 Transmitting CAN Messages .......................................................................................... 43

9.0 Receiving CAN Messages .............................................................................................. 50

10.0 DMA Controller Configuration ......................................................................................... 63

11.0 CAN Error Management ................................................................................................. 66

12.0 CAN Interrupts ................................................................................................................ 69

13.0 CAN Low-Power Modes.................................................................................................. 72

14.0 CAN Time Stamping Using Input Capture ...................................................................... 72

15.0 Related Application Notes............................................................................................... 73

16.0 Revision History .............................................................................................................. 74

Enhanced Controller Area Network (CAN)

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 2  2007-2020 Microchip Technology Inc.

1.0 INTRODUCTION

The dsPIC33F/PIC24H Enhanced Controller Area Network (CAN) module implements the CAN

Protocol 2.0B, used primarily in industrial and automotive applications. This asynchronous serial

data communication protocol provides reliable communications in electrically noisy environ-

ments. The dsPIC33F device family integrates up to two CAN modules. Figure 1-1 illustrates a

typical CAN bus topology.

Figure 1-1: Typical CAN Bus Network

The CAN module supports the following key features:

Standards Compliance:

• Full CAN 2.0B compliance

• Programmable bit rate up to 1 Mbps

Message Reception:

• 32 message buffers – all of them can be used for reception

• 16 acceptance filters for message filtering

• Three acceptance filter mask registers for message filtering

• Automatic response to Remote Transmit Request

• Up to 32-message deep First-In First-Out (FIFO) buffer

• DeviceNet™ addressing support

• DMA interface for message reception

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all dsPIC33/PIC24 devices.

Please consult the note at the beginning of the “Direct Memory Access (DMA)”

chapter in the current device data sheet to check whether this document supports

the device you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Website at: http://www.microchip.com

CAN

bus

CAN1

PIC® MCU

with Integrated

CAN

Transceiver

dsPIC33F/PIC24H

with Integrated

CAN™

dsPIC33/PIC24

with Integrated

CAN

Transceiver

CAN Transceiver

CAN

Transceiver

CAN

CAN2

CAN

Transceiver

dsPIC33F/PIC24H

 2007-2020 Microchip Technology Inc. DS70000185D-page 3

Enhanced CAN Module

Message Transmission:

• Eight message buffers configurable for message transmission

• User-defined priority levels for message buffers used for transmission

• DMA interface for message transmission

Others:

• Loopback, Listen All Messages and Listen Only modes for self-test, system diagnostics

and bus monitoring

• Low-power operating modes

Figure 1-2 illustrates the general structure of the CAN module and its interaction with the DMA

Controller and DMA RAM.

Figure 1-2: CAN Interaction with DMA

1.1 CAN Module

The CAN module consists of a protocol engine, message acceptance filters, and separate trans-

mit and receive DMA interfaces. The protocol engine transmits and receives messages to and

from the CAN bus (as per CAN bus 2.0B protocol). The user-configurable acceptance filters are

used by the module to examine the received message to determine if it should be stored in the

DMA message buffer or discarded.

For received messages, the receive DMA interface generates a receive data interrupt to initiate

a DMA cycle. The receive DMA channel reads data from the CxRXD register and writes them

into the message buffer.

For transmit messages, the transmit DMA interface generates a transmit data interrupt to start a

DMA cycle. The transmit DMA channel reads from the message buffer and writes to the CxTXD

1.2 Message Buffers

The CAN module supports up to 32 message buffers for storing data transmitted or received on

the CAN bus. These buffers are located in DMA RAM. Message Buffers 0-7 can be configured

for either transmit or receive operation. Message Buffers 8-31 are receive-only buffers and

cannot be used for message transmission.

1.3 DMA Controller

The DMA controller acts as an interface between the message buffers and CAN to transfer data

back and forth without CPU intervention. The DMA controller supports up to eight channels for

transferring data between DMA RAM and the dsPIC33F peripherals. Two separate DMA

channels are needed to support CAN message transmission and CAN message reception.

Each DMA channel has a DMA Request (DMAxREQ) register, which is used by the user

application to assign an interrupt event to trigger a DMA-based message transfer.

CxTX

CxRX

Message Buffer 0

Message Buffer 7

Message Buffer 8

Message Buffer 31

CAN

Protocol

Engine

CAN

Transmit

(CxTXD)

Acceptance

Filter 0-15

CAN

Receive

(CxRXD)

TX DMA

Interface

RX DMA

Interface

DMA

Channel

DMA

Channel

Message Buffer 1

CAN Module Message Buffer

(DMA RAM)

Request

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 4  2007-2020 Microchip Technology Inc.

2.0 CAN MESSAGE FORMATS

The CAN bus protocol uses asynchronous communication. Information is passed from transmit-

ters to receivers in data frames, which are composed of byte fields that define the contents of the

data frame, as shown in Figure 2-1.

Each frame begins with a Start-of-Frame (SOF) bit and terminates with an End-of-Frame (EOF)

bit field. The Start-of-Frame is followed by Arbitration and Control fields, which identify the

message type, format, length and priority. This information allows each node on the CAN bus to

respond appropriately to the message. The Data field conveys the message content and is vari-

able length, ranging from 0 to 8 bytes. Error protection is provided by the Cyclic Redundancy

Check (CRC) and Acknowledgement (ACK) fields.

Figure 2-1: CAN Bus Message Frame

The CAN bus protocol supports five frame types:

•Data Frame – carries data from transmitter to the receivers

•Remote Frame – transmitted by a node on the bus, to request transmission of a data

frame with the same identifier from another node

•Error Frame – transmitted by any node when it detects an error

•Overload Frame – provides an extra delay between successive data or remote frames

•Interframe Space – provides a separation between successive frames

The CAN 2.0B specification defines two additional data formats:

•Standard Data Frame – intended for standard messages that use 11 identifier bits

•Extended Data Frame – intended for extended messages that use 29 identifier bits

There are three versions of CAN bus specifications:

•2.0A – considers a 29-bit identifier as an error

• 2.0B Passive – ignores 29-bit identifier messages

•2.0B Active – handles both 11-bit and 29-bit identifiers

The dsPIC33F CAN module is compliant with the CAN 2.0B active specification, while providing

enhanced message filtering capabilities.

Note: Refer to the Bosch CAN bus specification for detailed information on the CAN

protocol.

ARBITRATION CONTROL DATA E

ACKCRC

 2007-2020 Microchip Technology Inc. DS70000185D-page 5

Enhanced CAN Module

2.1 Standard Data Frame

The standard data frame message begins with a Start-of-Frame bit followed by a 12-bit Arbitra-

tion field, as shown in Figure 2-2. The Arbitration field contains an 11-bit identifier and the

Remote Transmit Request (RTR) bit. The identifier defines the type of information contained in

the message and is used by each receiving node to determine if the message is of interest to it.

The RTR bit distinguishes a data frame from a remote frame. For a standard data frame, the RTR

bit is clear.

Following the Arbitration field is a 6-bit Control field, which provides more information about the

contents of the message. The first bit in the Control field is an Identifier Extension (IDE) bit, which

distinguishes the message as either a standard or extended data frame. A standard data frame

is indicated by a dominant state (logic level ‘0’) during transmission of the IDE bit. The second

bit in the Control field is a Reserved (RB0) bit, which is in the Dominant state (logic level ‘0’). The

last four bits in the Control field represent the Data Length Code (DLC), which specifies the

number of data bytes present in the message.

The Data field follows the Control field. This field carries the message data – the actual payload

of the data frame. This field is variable length, ranging from 0 to 8 bytes. The number of bytes is

user-selectable.

The Data field is followed by the Cyclic Redundancy Check field, which is a 15-bit CRC sequence

with one delimiter bit.

The Acknowledgement (ACK) field is sent as a recessive bit (logic level ‘1’) and is overwritten as

a dominant bit by any receiver that has received the data correctly. The message is

Acknowledged by the receiver, irrespective of the result of the acceptance filter comparison.

The last field is the End-of-Frame (EOF) field, which consists of seven recessive bits that indicate

the end of the message.

Figure 2-2: Format of the Standard Data Frame

SID10 SID1

IDENTIFIER

11 Bits

RB0 DLC

4 Bits

DATA

8 Bytes

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID0

11-Bit Identifier

Interframe Space

Data

Frame Interframe Space

IDE is Dominant (Logical ‘0’)

RTR is Dominant (Logical ‘0’)

RB0 is Dominant (Logical ‘0’)

Arbitration

Field

Control

Field

CRC

Field

ACK

Field

End-of-

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 6  2007-2020 Microchip Technology Inc.

2.2 Extended Data Frame

The extended data frame begins with a SOF bit, followed by a 31-bit Arbitration field, as shown

in Figure 2-3. The Arbitration field for the extended data frame contains 29 identifier bits in two

fields separated by a Substitute Remote Request (SRR) bit and an IDE bit. SRR = 1 for extended

data frames. The IDE bit indicates the data frame type. For the extended data frame, IDE = 1.

The extended data frame Control field consists of seven bits. The first bit is the RTR. For the

extended data frame, RTR = 0. The next two bits, RB1 and RB0, are reserved bits that are in the

Dominant state (logic level ‘0’). The last four bits in the Control field are the Data Length Code,

which specifies the number of data bytes present in the message.

The remaining fields in an extended data frame are identical to a standard data frame.

Figure 2-3: Format of the Extended Data Frame

SID10 SID1

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID0

Field

29-Bit Identifier

Control CRC

IDENTIFIER

18 Bits

EID17 EID1 EID0

IDE is Recessive (Logical ‘1’)

SRR is Recessive (Logical ‘1’)

RTR is Dominant (Logical ‘0’)

RB0 is Dominant (Logical ‘0’)

RB1 is Dominant (Logical ‘0’)

ACK End-of-

Frame

Data

DATA

8 Bytes

Arbitration

Field Field Field Field

 2007-2020 Microchip Technology Inc. DS70000185D-page 7

Enhanced CAN Module

2.3 Remote Frame

A node expecting to receive data from another node can initiate transmission of the respective

data by the source node by sending a remote frame. A remote frame can be in standard format

(see Figure 2-4) or extended format (see Figure 2-5).

A remote frame is similar to a data frame, with the following exceptions:

• The RTR bit is recessive (RTR = 1)

• There is no Data field

• The value of the DLC bits is 0  DLC 8

Figure 2-4: Format of the Standard Remote Frame

Figure 2-5: Format of the Extended Remote Frame

SID10 SID1

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID0

11-Bit Identifier

RB0

IDE is Dominant (Logical ‘0’)

RTR is Recessive (Logical ‘1’)

RB0 is Dominant (Logical ‘0’)

Arbitration Field Control Field CRC Field ACK Field End-of-Frame

SID10 SID0

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID1

Arbitration Field

29-Bit Identifier

Control Field CRC Field

IDENTIFIER

18 Bits

EID17 EID1 EID0

IDE is Recessive (Logical ‘1’)

SRR is Recessive (Logical ‘1’)

RTR is Recessive (Logical ‘1’)

RB0 is Dominant (Logical ‘0’)

RB1 is Dominant (Logical ‘0’)

ACK Field

End-of-

Frame

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 8  2007-2020 Microchip Technology Inc.

2.4 Error Frame

An error frame is generated by any node that detects a bus error. An error frame consists of an

Error Flag field followed by an Error Delimiter field. The Error Delimiter consists of eight recessive

bits and allows the bus nodes to restart communications cleanly after an error has occurred.

There are two types of Error Flag fields depending on the error status of the node that detects

the error:

•Error Active Flag – contains six consecutive dominant bits, which forces all other

nodes on the network to generate error echo flags, thereby resulting in a series of 6 to

12 dominant bits on the bus.

•Error Passive Flag – contains six consecutive recessive bits, with the result that unless

the bus error is detected by the transmitting node, the transmission of an Error Passive flag

will not affect the communications of any other node on the network.

2.5 Overload Frame

An overload frame can be generated by a node, either when a dominant bit is detected during

Interframe Space, or when a node is not yet ready to receive the next message (for example, if

it is still reading the previous received message). An overload frame has the same format as an

error frame with an active error flag, but can only be generated during Interframe Space. It con-

sists of an Overload Flag field with six dominant bits followed by an Overload Delimiter field with

eight recessive bits. A node can generate a maximum of two sequential overload frames to delay

the start of the next message.

2.6 Interframe Space

Interframe Space separates successive frames being transmitted on the CAN bus. It consists of

at least three recessive bits, referred to as ‘Intermission’. The Interframe Space allows nodes

time to internally process the previously received message before the start of the next frame. If

the transmitting node is in the Error Passive state, an additional eight recessive bits are inserted

in the Interframe Space before any other message is transmitted by the node. This period is

called a Suspend Transmit field and allows time for other transmitting nodes to take control of the

bus.

3.0 REGISTER MAPS

The following are the register maps related to CAN:

• )CAN1 Register Map When C1CTRL1.WIN = 0 1 or (see Table 3-1

•CAN1 Register Map When C1CTRL1.WIN = 0 (see Table 3-2)

•CAN1 Register Map When C1CTRL1.WIN = 1 (see Table 3-3)

• )CAN2 Register Map When C2CTRL1.WIN = 0 1 or (see Table 3-4

•CAN2 Register Map When C2CTRL1.WIN = 0 (see Table 3-5)

•CAN2 Register Map When C2CTRL1.WIN = 1 (see Table 3-6)

 2007-2020 Microchip Technology Inc. DS70000185D-page 9

Table 3-1: CAN1 Register Map When C1CTRL1.WIN = 0 or 1

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

C1CTRL1 — — CSIDL ABAT — REQOP[2:0] OPMODE[2:0] — CANCAP —

C1CTRL2 — — — — — — — — — — — DNCNT[4

C1VEC — — — FILHIT[4:0] — ICODE[6:0]

C1FCTRL DMABS[2:0] — — — — — — — — FSA[4:0

C1FIFO — —— FBP[5:0] — FNRB[5:0]

C1INTF — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOV

C1INTE — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOV

C1EC TERRCNT[7:0] RERRCNT[7:0]

C1CFG1 — — — — — — — — SJW[1:0] BRP[5:0]

C1CFG2 — WAKFIL — — — SEG2PH[2:0] SEG2PHTS SAM SEG1PH[2:0]

C1FEN1

FLTEN[15:0]

C1FMSKSEL1

F7MSK[1:0] F6MSK[1:0] F5MSK[1:0] F4MSK[1:0] F3MSK[1:0] F2MSK[1:0] F1MSK[1:0]

C1FMSKSEL2

F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0] F11MSK[1:0] F10MSK[1:0] F9MSK[1:0]

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Table 3-2: CAN1 Register Map When C1CTRL1.WIN = 0

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

See definition when WIN = x

C1RXFUL1

RXFUL[15:0]

C1RXFUL2

RXFUL[31:16]

C1RXOVF1

RXOVF[15:0]

C1RXOVF2

RXOVF[31:16]

C1TR01CON TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI[1:0] TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN

C1TR23CON TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI[1:0] TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN

C1TR45CON TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI[1:0] TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN

C1TR67CON TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI[1:0] TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN

C1RXD Receive Data Word

C1TXD Transmit Data Word

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DS70000185D-page 10  2007-2020 Microchip Technology Inc.

Table 3-3: CAN1 Register Map When C1CTRL1.WIN = 1

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

See definition when WIN = x

C1BUFPNT1 F3BP[3:0] F2BP[3:0] F1BP[3:0] F0B

C1BUFPNT2 F7BP[3:0] F6BP[3:0] F5BP[3:0] F4B

C1BUFPNT3 F11BP[3:0] F10BP[3:0] F9BP[3:0] F8B

C1BUFPNT4 F15BP[3:0] F14BP[3:0] F13BP[3:0] F12B

C1RXM0SID SID[10:3] SID[2:0] — MIDE —

C1RXM0EID EID[15:8] EID[7:0]

C1RXM1SID SID[10:3] SID[2:0] — MIDE —

C1RXM1EID EID[15:8] EID[7:0]

C1RXM2SID SID[10:3] SID[2:0] — MIDE —

C1RXM2EID EID[15:8] EID[7:0]

C1RXF0SID SID[10:3] SID[2:0] — EXIDE —

C1RXF0EID EID[15:8] EID[7:0]

C1RXF1SID SID[10:3] SID[2:0] — EXIDE —

C1RXF1EID EID[15:8] EID[7:0]

C1RXF2SID SID[10:3] SID[2:0] — EXIDE —

C1RXF2EID EID[15:8] EID[7:0]

C1RXF3SID SID[10:3] SID[2:0] — EXIDE —

C1RXF3EID EID[15:8] EID[7:0]

C1RXF4SID SID[10:3] SID[2:0] — EXIDE —

C1RXF4EID EID[15:8] EID[7:0]

C1RXF5SID SID[10:3] SID[2:0] — EXIDE —

C1RXF5EID EID[15:8] EID[7:0]

C1RXF6SID SID[10:3] SID[2:0] — EXIDE —

C1RXF6EID EID[15:8] EID[7:0]

C1RXF7SID SID[10:3] SID[2:0] — EXIDE —

C1RXF7EID EID[15:8] EID[7:0]

C1RXF8SID SID[10:3] SID[2:0] — EXIDE —

C1RXF8EID EID[15:8] EID[7:0]

C1RXF9SID SID[10:3] SID[2:0] — EXIDE —

C1RXF9EID EID[15:8] EID[7:0]

C1RXF10SID SID[10:3] SID[2:0] — EXIDE —

C1RXF10EID EID[15:8] EID[7:0]

C1RXF11SID SID[10:3] SID[2:0] — EXIDE —

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2007-2020 Microchip Technology Inc. DS70000185D-page 11

C1RXF11EID EID[15:8] EID[7:0]

C1RXF12SID SID[10:3] SID[2:0] — EXIDE —

C1RXF12EID EID[15:8] EID[7:0]

C1RXF13SID SID[10:3] SID[2:0] — EXIDE —

C1RXF13EID EID[15:8] EID[7:0]

C1RXF14SID SID[10:3] SID[2:0] — EXIDE —

C1RXF14EID EID[15:8] EID[7:0]

C1RXF15SID SID[10:3] SID[2:0] — EXIDE —

C1RXF15EID EID[15:8] EID[7:0]

Table 3-3: CAN1 Register Map When C1CTRL1.WIN = 1 (Continued)

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DS70000185D-page 12  2007-2020 Microchip Technology Inc.

Table 3-4: CAN2 Register Map When C2CTRL1.WIN = 0 or 1

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

C2CTRL1 — — CSIDL ABAT — REQOP[2:0] OPMODE[2:0] —

CANCAP

—

C2CTRL2 — — — — — — — — — — — DNCNT[4

C2VEC — — — FILHIT[4:0] — ICODE[6:0]

C2FCTRL DMABS[2:0] — — — — — — — — FSA[4:0

C2FIFO — —— FBP[5:0] — FNRB[5:0]

C2INTF — — TXBO TXBP RXBP TXWAR RXWAR

EWARN

IVRIF WAKIF ERRIF — FIFOIF RBOVIF

C2INTE — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE

C2EC TERRCNT[7:0] RERRCNT[7:0]

C2CFG1 — — — — — — — — SJW[1:0] BRP[5:0]

C2CFG2 — WAKFIL — — — SEG2PH[2:0]

SEG2PHTS

SAM SEG1PH[2:0]

C2FEN1 FLTEN[15:0]

C2FMSKSEL1

F7MSK[1:0] F6MSK[1:0] F5MSK[1:0] F4MSK[1:0] F3MSK[1:0] F2MSK[1:0] F1MSK[1:0]

C2FMSKSEL2

F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0] F11MSK[1:0] F10MSK[1:0] F9MSK[1:0]

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Table 3-5: CAN2 Register Map When C2CTRL1.WIN = 0

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

See definition when WIN = x

C2RXFUL1

RXFUL[15:0]

C2RXFUL2

RXFUL[31:16]

C2RXOVF1

RXOVF[15:0]

C2RXOVF2

RXOVF[31:16]

C2TR01CON TXEN1 TXABAT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI[1:0] TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0

C2TR23CON TXEN3 TXABAT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI[1:0] TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2

C2TR45CON TXEN5 TXABAT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI[1:0] TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4

C2TR67CON TXEN7 TXABAT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI[1:0] TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6

C2RXD Recieved Data Word

C2TXD Transmit Data Word

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

 2007-2020 Microchip Technology Inc. DS70000185D-page 13

Table 3-6: CAN2 Register Map When C2CTRL1.WIN = 1

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

See definition when WIN = x

C2BUFPNT1 F3BP[3:0] F2BP[3:0] F1BP[3:0] F0B

C2BUFPNT2 F7BP[3:0] F6BP[3:0] F5BP[3:0] F4B

C2BUFPNT3 F11BP[3:0] F10BP[3:0] F9BP[3:0] F8B

C2BUFPNT4 F15BP[3:0] F14BP[3:0] F13BP[3:0] F12B

C2RXM0SID SID[10:3] SID[2:0] — MIDE —

C2RXM0EID EID[15:8] EID[7:0]

C2RXM1SID SID[10:3] SID[2:0] — MIDE —

C2RXM1EID EID[15:8] EID[7:0]

C2RXM2SID SID[10:3] SID[2:0] — MIDE —

C2RXM2EID EID[15:8] EID[7:0]

C2RXF0SID SID[10:3] SID[2:0] — EXIDE —

C2RXF0EID EID[15:8] EID[7:0]

C2RXF1SID SID[10:3] SID[2:0] — EXIDE —

C2RXF1EID EID[15:8] EID[7:0]

C2RXF2SID SID[10:3] SID[2:0] — EXIDE —

C2RXF2EID EID[15:8] EID[7:0]

C2RXF3SID SID[10:3] SID[2:0] — EXIDE —

C2RXF3EID EID[15:8] EID[7:0]

C2RXF4SID SID[10:3] SID[2:0] — EXIDE —

C2RXF4EID EID[15:8] EID[7:0]

C2RXF5SID SID[10:3] SID[2:0] — EXIDE —

C2RXF5EID EID[15:8] EID[7:0]

C2RXF6SID SID[10:3] SID[2:0] — EXIDE —

C2RXF6EID EID[15:8] EID[7:0]

C2RXF7SID SID[10:3] SID[2:0] — EXIDE —

C2RXF7EID EID[15:8] EID[7:0]

C2RXF8SID SID[10:3] SID[2:0] — EXIDE —

C2RXF8EID EID[15:8] EID[7:0]

C2RXF9SID SID[10:3] SID[2:0] — EXIDE —

C2RXF9EID EID[15:8] EID[7:0]

C2RXF10SID SID[10:3] SID[2:0] — EXIDE —

C2RXF10EID EID[15:8] EID[7:0]

C2RXF11SID SID[10:3] SID[2:0] — EXIDE —

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

DS70000185D-page 14  2007-2020 Microchip Technology Inc.

C2RXF11EID EID[15:8] EID[7:0]

C2RXF12SID SID[10:3] SID[2:0] — EXIDE —

C2RXF12EID EID[15:8] EID[7:0]

C2RXF13SID SID[10:3] SID[2:0] — EXIDE —

C2RXF13EID EID[15:8] EID[7:0]

C2RXF14SID SID[10:3] SID[2:0] — EXIDE —

C2RXF14EID EID[15:8] EID[7:0]

C2RXF15SID SID[10:3] SID[2:0] — EXIDE —

C2RXF15EID EID[15:8] EID[7:0]

Table 3-6: CAN2 Register Map When C2CTRL1.WIN = 1 (Continued)

File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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Enhanced CAN Module

4.0 CAN REGISTERS

The CAN module has a large number of Special Function Registers (SFRs) that are used to con-

figure message acceptance filters and message buffers. To enable effective use of data RAM

space, multiple sets of SFRs are mapped onto the same set of memory addresses. The SFR Map

Window Select (WIN) bit in CAN Control Register 1 (CxCTRL1[0]) is used to selectively access

one of these sets of SFRs.

If WIN (CxCTRL1[0]) = 1, the message acceptance filters, masks and Filter Buffer Pointer

registers are accessed by the user application.

If WIN (CxCTRL1[0]) = 0, the Buffer Control and Status registers and the Transmit and Receive

Data registers are accessed by the user application.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SJW[1:0] BRP[5:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7-6 SJW[1:0]: Synchronization Jump Width bits

11 = Length is 4 x TQ

10 = Length is 3 x TQ

01 = Length is 2 x TQ

00 = Length is 1 x TQ

bit 5-0 BRP[5:0]: Baud Rate Prescaler bits

11 1111 = TQ = 2 x 64 x 1/FCAN

•

00 0010 = TQ = 2 x 3 x 1/FCAN

00 0001 = TQ = 2 x 2 x 1/FCAN

00 0000 = TQ = 2 x 1 x 1/FCAN

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Enhanced CAN Module

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

FLTEN[15:8]

bit 15 bit 8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

FLTEN[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 FLTEN[15:0]: Enable Filter x bits

1 = Enables filter x to accept messages

0 = Disables filter x

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID[10:3]

bit 15 bit 8

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID[2:0] — EXIDE — EID[17:16]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 SID[10:0]: Standard Identifier bits

1 = Message address bit SIDx must be ‘1’ to match filter

0 = Message address bit SIDx must be ‘0’ to match filter

bit 4 Unimplemented: Read as ‘0’

bit 3 EXIDE: Extended Identifier Enable bit

If MIDE = 1:

1 = Matches only messages with Extended Identifier addresses

0 = Matches only messages with Standard Identifier addresses

If MIDE = 0:

Ignores EXIDE bit.

bit 2 Unimplemented: Read as ‘0’

bit 1-0 EID[17:16]: Extended Identifier bits

1 = Message address bit EIDx must be ‘1’ to match filter

0 = Message address bit EIDx must be ‘0’ to match filter

Note: If no mask is applied to a filter, the filter will only accept standard frames. The filter will not accept extended

frames even if the EXIDE bit is set to ‘1’.

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R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[15:8]

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 EID[15:0]: Extended Identifier bits

1 = Message address bit EIDx must be ‘1’ to match filter

0 = Message address bit EIDx must be ‘0’ to match filter

CAN

Acceptance Filter Mask Standard Identifier Register n (n = 0-2)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID[10:3]

bit 15 bit 8

R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID[2:0] — MIDE — EID[17:16]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 SID[10:0]: Standard Identifier bits

1 = Includes bit SIDx in filter comparison

0 = Bit SIDx is “don’t care” in filter comparison

bit 4 Unimplemented: Read as ‘0’

bit 3 MIDE: Identifier Receive Mode bit

1 = Matches only message types (standard or extended address) that correspond to EXIDE bit in filter

0 = Matches either standard or extended address message if filters match

(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))

bit 2 Unimplemented: Read as ‘0’

bit 1-0 EID[17:16]: Extended Identifier bits

1 = Includes bit EIDx in filter comparison

0 = Bit EIDx is a “don’t care” in filter comparison

 2007-2020 Microchip Technology Inc. DS70000185D-page 19

Enhanced CAN Module

CAN

Acceptance Filter Mask Extended Identifier Register n (n = 0-2)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[15:8]

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 EID[15:0]: Extended Identifier bits

1 = Includes bit EIDx in filter comparison

0 = Bit EIDx is “don’t care” in filter comparison

CAN

Filter 7-0 Mask Selection Register 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F7MSK[1:0] F6MSK[1:0] F5MSK[1:0] F4MSK[1:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F3MSK[1:0] F2MSK[1:0] F1MSK[1:0] F0MSK[1:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 F7MSK[1:0]: Mask Source for Filter 7 bits

11 = Reserved

10 = Acceptance Mask 2 registers contain mask

01 = Acceptance Mask 1 registers contain mask

00 = Acceptance Mask 0 registers contain mask

bit 13-12 F6MSK[1:0]: Mask Source for Filter 6 bits (same values as bits 15-14)

bit 11-10 F5MSK[1:0]: Mask Source for Filter 5 bits (same values as bits 15-14)

bit 9-8 F4MSK[1:0]: Mask Source for Filter 4 bits (same values as bits 15-14)

bit 7-6 F3MSK[1:0]: Mask Source for Filter 3 bits (same values as bits 15-14)

bit 5-4 F2MSK[1:0]: Mask Source for Filter 2 bits (same values as bits 15-14)

bit 3-2 F1MSK[1:0]: Mask Source for Filter 1 bits (same values as bits 15-14)

bit 1-0 F0MSK[1:0]: Mask Source for Filter 0 bits (same values as bits 15-14)

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CAN

Filter 15-8 Mask Selection Register 2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F15MSK[1:0] F14MSK[1:0] F13MSK[1:0] F12MSK[1:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F11MSK[1:0] F10MSK[1:0] F9MSK[1:0] F8MSK[1:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 F15MSK[1:0]: Mask Source for Filter 15 bits

11 = Reserved

10 = Acceptance Mask 2 registers contain mask

01 = Acceptance Mask 1 registers contain mask

00 = Acceptance Mask 0 registers contain mask

bit 13-12 F14MSK[1:0]: Mask Source for Filter 14 bits (same values as bits 15-14)

bit 11-10 F13MSK[1:0]: Mask Source for Filter 13 bits (same values as bits 15-14)

bit 9-8 F12MSK[1:0]: Mask Source for Filter 12 bits (same values as bits 15-14)

bit 7-6 F11MSK[1:0]: Mask Source for Filter 11 bits (same values as bits 15-14)

bit 5-4 F10MSK[1:0]: Mask Source for Filter 10 bits (same values as bits 15-14)

bit 3-2 F9MSK[1:0]: Mask Source for Filter 9 bits (same values as bits 15-14)

bit 1-0 F8MSK[1:0]: Mask Source for Filter 8 bits (same values as bits 15-14)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F3BP[3:0] F2BP[3:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F1BP[3:0] F0BP[3:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F3BP[3:0]: RX Buffer Mask for Filter 3 bits

1111 = Filter hits received in RX FIFO buffer

1110 = Filter hits received in RX Buffer 14

•

0001 = Filter hits received in RX Buffer 1

0000 = Filter hits received in RX Buffer 0

bit 11-8 F2BP[3:0]: RX Buffer mask for Filter 2 bits (same values as bits 15-12)

bit 7-4 F1BP[3:0]: RX Buffer mask for Filter 1 bits (same values as bits 15-12)

bit 3-0 F0BP[3:0]: RX Buffer mask for Filter 0 bits (same values as bits 15-12)

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Enhanced CAN Module

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F7BP[3:0] F6BP[3:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F5BP[3:0] F4BP[3:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F7BP[3:0]: RX Buffer Mask for Filter 7 bits

1111 = Filter hits received in RX FIFO buffer

1110 = Filter hits received in RX Buffer 14

•

0001 = Filter hits received in RX Buffer 1

0000 = Filter hits received in RX Buffer 0

bit 11-8 F6BP[3:0]: RX Buffer mask for Filter 6 bits (same values as bits 15-12)

bit 7-4 F5BP[3:0]: RX Buffer mask for Filter 5 bits (same values as bits 15-12)

bit 3-0 F4BP[3:0]: RX Buffer mask for Filter 4 bits (same values as bits 15-12)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F11BP[3:0] F10BP[3:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F9BP[3:0] F8BP[3:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F11BP[3:0]: RX Buffer Mask for Filter 11

1111 = Filter hits received in RX FIFO buffer

1110 = Filter hits received in RX Buffer 14

•

0001 = Filter hits received in RX Buffer 1

0000 = Filter hits received in RX Buffer 0

bit 11-8 F10BP[3:0]: RX Buffer mask for Filter 10 (same values as bit 15-12)

bit 7-4 F9BP[3:0]: RX Buffer mask for Filter 9 (same values as bit 15-12)

bit 3-0 F8BP[3:0]: RX Buffer mask for Filter 8 (same values as bit 15-12)

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F15BP[3:0] F14BP[3:0]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

F13BP[3:0] F12BP[3:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 F15BP[3:0]: RX Buffer Mask for Filter 15 bits

1111 = Filter hits received in RX FIFO Buffer

1110 = Filter hits received in RX Buffer 14

•

0001 = Filter hits received in RX Buffer 1

0000 = Filter hits received in RX Buffer 0

bit 11-8 RX Buffer mask for Filter 14 bits (same values as bits 15-12)F14BP[3:0]:

bit 7-4 F13BP[3:0]: RX Buffer mask for Filter 13 bits (same values as bits 15-12)

bit 3-0 F12BP[3:0]: RX Buffer mask for Filter 12 bits (same values as bits 15-12)

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL[15:8]

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL[7:0]

bit 7 bit 0

Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXFUL[15:0]: Receive Buffer n Full bits

1 = Buffer is full (set by module)

0 = Buffer is empty

 2007-2020 Microchip Technology Inc. DS70000185D-page 23

Enhanced CAN Module

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL[31:24]

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXFUL[23:16]

bit 7 bit 0

Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXFUL[31:16]: Receive Buffer n Full bits

1 = Buffer is full (set by module)

0 = Buffer is empty

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF[15:8]

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF[7:0]

bit 7 bit 0

Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXOVF[15:0]: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)

0 = No overflow condition

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R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF[31:24]

bit 15 bit 8

R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0

RXOVF[23:16]

bit 7 bit 0

Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 RXOVF[31:16]: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)

0 = No overflow condition

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Enhanced CAN Module

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

DMABS[2:0] — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FSA[4:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 DMABS[2:0]: DMA Buffer Size bits

111 = Reserved

110 = 32 buffers in DMA RAM

101 = 24 buffers in DMA RAM

100 = 16 buffers in DMA RAM

011 = 12 buffers in DMA RAM

010 = 8 buffers in DMA RAM

001 = 6 buffers in DMA RAM

000 = 4 buffers in DMA RAM

bit 12-5 Unimplemented: Read as ‘0’

bit 4-0 FSA[4:0]: FIFO Start Area bits

11111 = Reads buffer RB31

11110 = Reads buffer RB30

•

00010 = TX/RX buffer TRB2

00001 = TX/RX buffer TRB1

00000 = TX/RX buffer TRB0

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U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — FBP[5:0]

bit 15 bit 8

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — FNRB[5:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-8 FBP[5:0]: FIFO Buffer Pointer bits

011111 = RB31 buffer

011110 = RB30 buffer

•

000001 = TRB1 buffer

000000 = TRB0 buffer

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 FNRB[5:0]: FIFO Next Read Buffer Pointer bits

011111 = RB31 buffer

011110 = RB30 buffer

•

000001 = TRB1 buffer

000000 = TRB0 buffer

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Enhanced CAN Module

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — TXBO TXBP RXBP TXWAR RXWAR EWARN

bit 15 bit 8

R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0

IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF

bit 7 bit 0

Legend: C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13 TXBO: Transmitter in Error State Bus Off bit

1 = Transmitter is in Bus Off state

0 = Transmitter is not in Bus Off state

bit 12 TXBP: Transmitter in Error State Bus Passive bit

1 = Transmitter is in Bus Passive state

0 = Transmitter is not in Bus Passive state

bit 11 RXBP: Receiver in Error Bus Passive bit

1 = Receiver is in Bus Passive state

0 = Receiver is not in Bus Passive state

bit 10 TXWAR: Transmitter in Error State Warning bit

1 = Transmitter is in Error Warning state

0 = Transmitter is not in Error Warning state

bit 9 RXWAR: Receiver in Error State Warning bit

1 = Receiver is in Error Warning state

0 = Receiver is not in Error Warning state

bit 8 EWARN: Transmitter or Receiver in Error State Warning bit

1 = Transmitter or receiver is in Error Warning state

0 = Transmitter or receiver is not in Error Warning state

bit 7 IVRIF: Invalid Message Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF[13:8] register)

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 4 Unimplemented: Read as ‘0’

bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 1 RBIF: RX Buffer Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

bit 0 TBIF: TX Buffer Interrupt Flag bit

1 = Interrupt request has occurred

0 = Interrupt request has not occurred

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U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 IVRIE: Invalid Message Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 6 WAKIE: Bus Wake-up Activity Interrupt Flag bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 5 ERRIE: Error Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 4 Unimplemented: Read as ‘0’

bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 1 RBIE: RX Buffer Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

bit 0 TBIE: TX Buffer Interrupt Enable bit

1 = Interrupt request enabled

0 = Interrupt request not enabled

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Enhanced CAN Module

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — FILHIT[4:0]

bit 15 bit 8

U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE[6:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT[4:0]: Filter Hit Number bits

10000-11111 = Reserved

01111 = Filter 15

•

00001 = Filter 1

00000 = Filter 0

bit 7 Unimplemented: Read as ‘0’

bit 6-0 ICODE[6:0]: Interrupt Flag Code bits

1000101-1111111 = Reserved

1000100 = FIFO almost full interrupt

1000011 = Receiver overflow interrupt

1000010 = Wake-up interrupt

1000001 = Error interrupt

1000000 = No interrupt

•

0100000-0111111 = Reserved

0011111 = RB31 buffer interrupt

0011110 = RB30 buffer interrupt

•

0001001 = RB9 buffer interrupt

0001000 = RB8 buffer interrupt

0000111 = TRB7 buffer interrupt

0000110 = TRB6 buffer interrupt

0000101 = TRB5 buffer interrupt

0000100 = TRB4 buffer interrupt

0000011 = TRB3 buffer interrupt

0000010 = TRB2 buffer interrupt

0000001 = TRB1 buffer interrupt

0000000 = TRB0 buffer interrupt

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U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — DNCNT[4:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5 Unimplemented: Read as ‘0’

bit 4-0 DNCNT[4:0]: DeviceNet™ Filter Bit Number bits

10011-11111 = Invalid selection

10010 = Compares bits [7:0] of byte 0 and bits [7:0] of byte 1 and bits [7:6] of byte 2 with EID[17:0]

10001 = Compares bits [7:0] of byte 0 and bits [7:0] of byte 1 and bit [7] of byte 2 with EID[17:1]

10000 = Compares bits [7:0] of data byte 0 and bits [7:0] of data byte 1 with EID[17:2]

01111 = Compares bits [7:0] of data byte 0 and bits [7:1] of data byte 1 with EID[17:3]

01110 = Compares bits [7:0] of data byte 0 and bits [7:2] of data byte 1 with EID[17:4]

01101 = Compares bits [7:0] of data byte 0 and bits [7:3] of data byte 1 with EID[17:5]

01100 = Compares bits [7:0] of data byte 0 and bits [7:4] of data byte 1 with EID[17:6]

01011 = Compares bits [7:0] of data byte 0 and bits [7:5] of data byte 1 with EID[17:7]

01001 = Compares bits [7:0] of data byte 0 and bit [7] of data byte 1 with EID[17:9]

01010 = Compares bits [7:0] of data byte 0 and bits [7:6] of data byte 1 with EID[17:8]

01000 = Compares bits [7:0] of data byte 0 with EID[17:10]

00111 = Compares bits [7:1] of data byte 0 with EID[17:11]

00110 = Compares bits [7:2] of data byte 0 with EID[17:12]

00101 = Compares bits [7:3] of data byte 0 with EID[17:13]

00100 = Compares bits [7:4] of data byte 0 with EID[17:14]

00011 = Compares bits [7:5] of data byte 0 with EID[17:15]

00010 = Compares bits [7:6] of data byte 0 with EID[17:16]

00001 = Compares bit 7 of data byte 0 with EID[17]

00000 = Does not compare data bytes

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R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI[1:0]

bit 15 bit 8

R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENm TXABTm( )1TXLARBm( )1TXERRm( )1TXREQm RTRENm TXmPRI[1:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Refer to definition for bits 7-0, Controls Buffer n

bit 7 TXENm: TX/RX Buffer Selection bit

1 = Buffer TRBn is a transmit buffer

0 = Buffer TRBn is a receive buffer

bit 6 TXABTm: Message Aborted bit( )1

1 = Message was aborted

0 = Message completed transmission successfully

bit 5 TXLARBm: Message Lost Arbitration bit( )1

1 = Message lost arbitration while being sent

0 = Message did not lose arbitration while being sent

bit 4 TXERRm: Error Detected During Transmission bit( )1

1 = A bus error occurred while the message was being sent

0 = A bus error did not occur while the message was being sent

bit 3 TXREQm: Message Send Request bit

1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent

0 = Clearing the bit to ‘0’ while set requests a message abort

bit 2 RTRENm: Auto-Remote Transmit Enable bit

1 = When a remote transmit is received, TXREQ is set

0 = When a remote transmit is received, TXREQ is unaffected

bit 1-0 TXmPRI[1:0]: Message Transmission Priority bits

11 = Highest message priority

10 = High intermediate message priority

01 = Low intermediate message priority

00 = Lowest message priority

Note 1: This bit is cleared when TXREQ is set.

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R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

TERRCNT[7:0]

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 TERRCNT[7:0]: Transmit Error Count bits

bit 7-0 RERRCNT[7:0]: Receive Error Count bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA[15:8]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 DATA[15:0]: Received Data Word bits

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA[15:8]

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATA[7:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 DATA[15:0]: Transmitted Data Word bits

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5.0 CAN MESSAGE BUFFERS

CAN message buffers are located in DMA RAM. They are not CAN Special Function Registers.

The user application must directly write into the DMA RAM area that is configured for CAN

message buffers. The location and size of the buffer area is defined by the user application.

This section provides information on how the message buffer words are organized for transmission

and reception. (Refer to Section 2.0 “CAN Message Formats” for message buffer layout details

and Section 10.0 “DMA Controller Configuration” for details on how to configure CAN message

buffers in DMA RAM.)

Buffer 5-1:

CAN

Message Buffer Word 0

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — SID[10:6]

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

SID[5:0] SRR IDE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-2 SID[10:0]: Standard Identifier bits

bit 1 SRR: Substitute Remote Request bit

When IDE = :0

1 = Message will request remote transmission

0 = Normal message

When IDE = :1

The SRR bit must be set to ‘1’

bit 0 IDE: Extended Identifier bit

1 = Message will transmit Extended Identifier

0 = Message will transmit Standard Identifier

Buffer 5-2:

CAN

Message Buffer Word 1

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — EID[17:14]

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[13:6]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 EID[17:6]: Extended Identifier bits

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Enhanced CAN Module

(

Buffer 5-3:

CAN

Message Buffer Word 2

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EID[5:0] RTR RB1

bit 15 bit 8

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — RB0 DLC[3:0]

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-10 EID[5:0]: Extended Identifier bits

bit 9 RTR: Remote Transmission Request bit

When TXIDE = 1:

1 = Message will request remote transmission

0 = Normal message

When TXIDE = 0:

The RTR bit is ignored.

bit 8 RB1: Reserved Bit 1

User must set this bit to ‘0’ per CAN protocol.

bit 7-5 Unimplemented: Read as ‘0’

bit 4 RB0: Reserved Bit 0

User must set this bit to ‘0’ per CAN protocol.

bit 3-0 DLC[3:0]: Data Length Code bits

Buffer 5-4: CAN Message Buffer Word 3

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 1

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CAN Message Byte 1

bit 7-0 CAN Message Byte 0

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Buffer 5-5: CAN Message Buffer Word 4

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 3

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CAN Message Byte 3

bit 7-0 CAN Message Byte 2

Buffer 5-6: CAN Message Buffer Word 5

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 5

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 4

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CAN Message Byte 5

bit 7-0 CAN Message Byte 4

Buffer 5-7: CAN Message Buffer Word 6

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 7

bit 15 bit 8

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

Byte 6

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 CAN Message Byte 7

bit 7-0 CAN Message Byte 6

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Buffer 5-8:

CAN

Message Buffer Word 7

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — FILHIT[4:0]

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT[4:0]: Filter Hit Code bits

Encodes number of filter that resulted in writing this buffer (only written by module for receive buffers,

unused for transmit buffers).

bit 7-0 Unimplemented: Read as ‘0’

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6.0 BIT TIMING

The nominal bit rate is the number of bits per second transmitted on the CAN bus: Nominal Bit

Time = 1 ÷ Nominal Bit Rate.

There are four time segments in a bit time to compensate for any phase shifts due to oscillator

drifts or propagation delays. These time segments do not overlap each other and are represented

in terms of Time Quantum (TQ). One TQ is a fixed unit of time derived from the oscillator clock.

The total number of time quanta in a nominal bit time must be programmed between 8 and 25 TQ.

Figure 6-1 shows how the Time Quanta Clock (F

TQ) is obtained from the system clock and also

how the different time segments are programmed.

Figure 6-1: CAN Bit Timing

6.1 Bit Segments

Each bit transmission time consists of four time segments:

•Synchronization Segment – This time segment synchronizes the different nodes

connected on the CAN bus. A bit edge is expected to be within this segment. Based on

CAN protocol, the Synchronization Segment is assumed to be one TQ.

•Propagation Segment – This time segment compensates for any time delay that may

occur due to the bus line or due to the various transceivers connected on that bus.

•Phase Segment 1 – This time segment compensates for errors that may occur due to

phase shift in the edges. The time segment may be lengthened during resynchronization to

compensate for the phase shift.

•Phase Segment 2 – This time segment compensates for errors that may occur due to

phase shift in the edges. The time segment may be shortened during resynchronization to

compensate for the phase shift. The Phase Segment 2 time can be configured to be either

programmable or specified by the Phase Segment 1 time.

CAN Nominal Bit Time

Time Quanta

Time Segments Propagation Segment Phase Segment 1 Phase Segment 2

Sync

Seg

1 TQ 1-8 TQ 1-8 TQ 1-8 TQ

Sample Point

BAUD RATE

PRESCALER

FCY 2

Prop Seg

Phase Seg1

Phase Seg2

Sync Seg

FTQ

Time Quanta

BRPx (CxCFG1[5:0])

PRSEGx (CxCFG2[2:0])

SEG1PHx (CxCFG2[5:3])

SEG2PH (CxCFG2[10:8])

SJWx (CxFG1[7:6])

1-8 TQ

1:1

1:2

1:64

(TQ)

1-8 TQ

1 TQ

8-25 TQ

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Enhanced CAN Module

6.2 Sample Point

The sample point is the point in a CAN bit time interval where the sample is taken and the bus

state is read and interpreted. It is situated between Phase Segment 1 and Phase Segment 2.

The CAN bus can be sampled once or three times at the sample point, as configured by the

Sample CAN (SAM) Bus Line bit in the CAN Baud Rate Configuration Register (CxCFG2[6]).

• If SAM (CxCFG2[6]) = 1, the CAN bus is sampled three times at the sample point. The

most common of the three samples determines the bit value.

• If SAM (CxCFG2[6]) = 0, the CAN bus is sampled only once at the sample point.

6.3 Synchronization

Two types of synchronization are used: Hard Synchronization and Resynchronization. A Hard

Synchronization occurs once at the start of a frame. Resynchronization occurs inside a frame.

•Hard Synchronization takes place on the recessive-to-dominant transition of the Start bit.

The bit time is restarted from that edge.

•Resynchronization takes place when a bit edge does not occur within the Synchronization

Segment in a message. One of the Phase Segments is shortened or lengthened by an

amount that depends on the phase error in the signal. The maximum amount that can be

used is determined by the Synchronization Jump Width parameter (SJW[1:0] CxCFG1[7:6]).

The length of Phase Segment 1 and Phase Segment 2 can be changed depending on oscillator

tolerances of the transmitting and receiving node. Resynchronization compensates for any

phase shifts that may occur due to the different oscillators used by the transmitting and receiving

nodes.

•Bit Lengthening – If the transmitting node in CAN has a slower oscillator than the receiv-

ing node, the next falling edge, and hence the sample point, can be delayed by lengthening

Phase Segment 1 in the bit time.

•Bit Shortening – If the transmitting node in CAN has a faster oscillator than the receiving

node, then the next falling edge, and hence the sample point of the next bit, can be reduced

by shortening Phase Segment 2 in the bit time.

•Synchronization Jump Width (SJW) – The SJW[1:0] bits in the CAN Baud Rate

Configuration Register 1 (CxCFG1[7:6]) determine the synchronization jump width by

limiting the amount of lengthening or shortening that can be applied to Phase Segment 1

and Phase Segment 2 time intervals. This segment should not be longer than Phase

Segment 2 time. The width can be 1-4 TQ.

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Enhanced CAN Module

Example 6-2 illustrates code for configuring CAN bit timing parameters.

Example 6-2: Code Example for Configuring CAN Bit Timing Parameters

/* Set the Operating Frequency of the device to be 40MHz */

#define FCY 40000000

/* Set the CAN module for Configuration Mode before writing into the Baud

Rate Control Registers*/

C1CTRL1bits.REQOP = 4;

/* Wait for the CAN module to enter into Configuration Mode */

while(C1CTRL1bits.OPMODE! = 4);

/* Phase Segment 1 time is 8 TQ */

C1CFG2bits.SEG1PH = 0x7;

/* Phase Segment 2 time is set to be programmable */

C1CFG2bits.SEG2PHTS = 0x1;

/* Phase Segment 2 time is 6 TQ */

C1CFG2bits.SEG2PH = 0x5;

/* Propagation Segment time is 5 TQ */

C1CFG2bits.PRSEG = 0x4;

/* Bus line is sampled three times at the sample point */

C1CFG2bits.SAM = 0x1;

/* Synchronization Jump Width set to 4 TQ */

C1CFG1bits.SJW = 0x3;

/* Baud Rate Prescaler bits set to 1:1, i.e., TQ = (2*1*1)/ FCAN */

C1CFG1bits.BRP = 0x0 ;

/* Put the CAN Module into Normal Mode Operating Mode*/

C1CTRL1bits.REQOP = 0;

/* Wait for the CAN module to enter into Normal Operating Mode */

while(C1CTRL1bits.OPMODE! = 0);

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7.0 CAN OPERATING MODES

The CAN module can operate in one of several modes selected by the user application. These

modes include:

• Configuration mode

• Normal Operation mode

• Listen-Only mode

• Listen All Messages mode

• Loopback mode

• Disable mode

Operating modes are requested by the user application writing to the Request Operation mode

(REQOP[2:0]) bits in the CAN Control Register 1 (CxCTRL1[10:8]). CAN Acknowledges entry

into the requested mode by the Operation Mode (OPMODE[2:0]) bits (CxCTRL1[7:5]). Mode

transition is performed in synchronization with the CAN network. That is, the CAN controller waits

until it detects a bus Idle sequence (11 recessive bits) before it changes mode.

7.1 Configuration Mode

After a hardware Reset, the CAN module is in the Configuration mode (OPMODE[2:0] = 100).

The error counters are cleared and all registers contain the Reset values. In order to modify the

CAN Baud Rate Configuration registers (CxCFG1 and CxCFG2), the CAN module must be in

Configuration mode.

7.2 Normal Operation Mode

In Normal Operation mode, the CAN module can transmit and receive CAN messages. Normal

Operation mode is requested after initialization by programming the REQOP[2:0] bits

(CxCTRL1[10:8]) to ‘000’. When OPMODE[2:0] = 000, the module proceeds with normal operation.

7.3 Listen-Only Mode

Listen-Only mode is used mainly for bus monitoring without actually participating in the

transmission process. The node in Listen-Only mode does not generate an Acknowledge or error

frames – one of the other nodes must do it. The Listen-Only mode can be used for detecting the

baud rate on the CAN bus.

7.4 Listen All Messages Mode

Listen All Messages mode is used for system debugging. Basically, all messages are received,

irrespective of their identifier, even when there is an error. If the Listen All Messages mode is acti-

vated, transmission and reception operate the same as Normal Operation mode, except that if a

message is received with an error, it is still transferred to a message buffer.

7.5 Loopback Mode

Loopback mode is used for self-test to allow the CAN module to receive its own message. In this

mode, the CAN transmit path is connected to the receive path internally. A “dummy”

Acknowledge is provided, thereby eliminating the need for another node to provide the

Acknowledge bit.

7.6 Disable Mode

Disable mode is used to ensure a safe shutdown before putting the device in Sleep or Idle mode.

That is, the CAN controller waits until it detects a bus Idle sequence (11 recessive bits) before it

changes mode. When the module is in Disable mode, it stops its own clocks, having no effect on

the CPU or other modules. The module wakes up when bus activity occurs or when the CPU sets

OPMODE[2:0] to ‘000’.

The CxTX pin stays in the Recessive state while the module is in Disable mode.

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Figure 8-1: CAN Transmission

Word 0

SRR IDE

Word 1 0

Word 2 10

EID[5:0] DLC[3:0]

RTR RB1

SID[10:0]

EID[17:6]

FILHIT[4:0]

Data Byte 1

Data Byte 3

Data Byte 5

Data Byte 7

Data Byte 0

Data Byte 2

Data Byte 4

Data Byte 6

Word 7

SID SRR EID RTR

SID RTR DLC

DLC

Message Buffer 0

Message Buffer 1

Message Buffer 2

Message Buffer 3

(TX)

Message Buffer 4

Message Buffer 5

Message Buffer 6

Message Buffer 7

Extended

Standard

CAN Data Frames

Word 3

Word 4

Word 5

Word 6

RB0

DMA RAM

TRANSMIT MESSAGE

Transmit

Priority

Arbitration

1215

Identifier

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Example 8-2 illustrates code to transmit an extended frame using Message Buffer 2.

Example 8-2: Code for Extended Data Frame Transmission

/* Assign 32x8word Message Buffers for CAN1 in DMA RAM */

unsigned int CAN1MsgBuf[32][8] __attribute__(space(dma));

DMA1STA = __builtin_dmaoffset(CAN1MsgBuf);

/* Configure Message Buffer 2for Transmission and assign priority*/

C1TR23CONbits.TXEN2 = 0x1;

C1TR23CONbits.TX2PRI = 0x2;

/* WRITE TO MESSAGE BUFFER 2 */

/* CiTRBnSID = 0bxxx1 0010 0011 1101

IDE = 0b1

SRR = 0b0

SID<10:0> : 0b100 1000 1111 */

CAN1MsgBuf[2][0] = 0x123D;

/* CiTRBnEID = 0bxxxx 1111 0000 0000

EID<17:6> = 0b1111 0000 0000 */

CAN1MsgBuf[2][1] = 0x0F00;

/* CiTRBnDLC = 0b0000 1100 xxx0 1111

EID<17:6> = 0b000011

RTR = 0b0

RB1 = 0b0

RB0 = 0b0

DLC = 0b1000 */

CAN1MsgBuf[2][2] = 0x0C08;

/* WRITE MESSAGE DATA BYTES */

CAN1MsgBuf[2][3] = 0xabcd;

CAN1MsgBuf[2][4] = 0xabcd;

CAN1MsgBuf[2][5] = 0xabcd;

CAN1MsgBuf[2][6] = 0xabcd;

/* REQUEST MESSAGE BUFFER 2 TRANSMISSION */

C1TR23CONbits.TXREQ2 = 0x1;

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Enhanced CAN Module

8.2 Aborting a Transmit Message

Setting the Abort All Pending Transmissions (ABAT) bit in the CAN Control Register 1

(CxCTRL1[12]) requests an abort of all pending messages. To abort a specific message, the

Message Send Request (TXREQm) bit (CxTRmnCON[3]) associated with that message buffer

must be cleared. In either case, the message is only aborted if the CAN module has not started

transmitting the message on the bus or the message has been started, but it is interrupted by

loss of arbitration or an error.

8.3 Remote Transmit Request/Response

8.3.1 REMOTE TRANSMIT REQUEST

A node expecting to receive a data frame with a specific identifier value can initiate the transmis-

sion of the respective data by another node by sending the remote frame. The remote frame can

be either in a standard or extended format.

A remote frame is similar to a data frame, with the following exceptions:

• The RTR bit is recessive (RTR = 1)

• There is no Data field

• The value of the DLC[3:0] bits is 0  DLC  8

To transmit a remote frame, the user application must perform these tasks:

• Configure the message buffer for transmission and assign a priority to the buffer.

• Write the remote frame in the appropriate message buffer. The transmitted identifier must

be identical to the identifier of the data frame to be received.

• Set the transmit request bit for the buffer to initiate transmission of the remote frame.

8.3.2 REMOTE TRANSMIT RESPONSE

The node that is acting as the source to respond to the remote frame request needs to configure

an acceptance filter to match the identifier of the remote request frame. Message Buffers 0-7 can

respond to remote requests; therefore, the Acceptance Filter Buffer Pointer (FnBP) should point

to one of the eight message buffers. The TX/RX Buffer Selection (TXENn) and Auto-Remote

Transmit Enable (RTRENn) bits in the CAN TX/RX Buffer Control register (CxTRmnCON) must

be set to respond to the remote request frame.

This is the only case where the Acceptance Filter Buffer Pointer (FnBP) points to a message

buffer that is configured for transmission (TXENn = 1).

Figure 8-2 illustrates the remote frame handling process:

4. CAN Node 1 sends a Remote Transmit Request (using Message Buffer 1).

5. CAN Node 2 receives the request and responds by sending the data frame (using

Message Buffer 7).

6. The data frame is received by CAN Node 1.

7. The data frame is stored in Message Buffer 14 of CAN Node 1.

Note: When configured for automatic response to remote requests (RTRENn = 1), the

CAN module ignores the value of the DLCx bits in the incoming RTR message. If

the application needs to transmit a data payload size specified by the DLCx bits in

the received RTR message, it should not enable an automatic RTR response. The

user application should process the RTR message like any other received

message, check if the RTR bit is set, and then transmit a message whose payload

size is equal to the DLCx bits in the received RTR message.

DS70000185D-page 48  2007-2020 Microchip Technology Inc.

Figure 8-2: Remote Transmit Request/Response

MASK 2

MASK 1

MASK 0

Filter 15

MASK 2

MASK 1

MASK 0

Remote Frame

Data Frame

SID

SRR =

EID

RTR =

DLC

SID

RTR =

DLC

SID

SRR =

EID

RTR =

SID

RTR =

DLC

Extended Message

Standard Message

DLC Filter

Filter 0

Message Buffer 0

Message Buffer 1 (TX)

Message Buffer 14 (RX)

Message Buffer 31

Messa

CAN NODE 1 CAN NODE 2

1. The node transmitting the remote frame must have a transmit buffer from which to send the remote frame and one receive buffer to receive the d

2. The node receiving the remote frame must have a transmit buffer from which to transmit a data frame in response to the received remote frame.

3. FnBPx (CxBUFPNTm) should be pointing to a transmit buffer in case of remote transmission.

4. RTREN (CxTRmnCON) should be set so that when a remote transmit is received, the TXREQ (CxTRmnCON) bit will be automatically set.

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Enhanced CAN Module

Example 8-3 illustrates the code required to transmit an extended remote frame using Message

Buffer 2.

Example 8-3: Code Example for Transmitting Extended Remote Frame

/* Assign 32x8word Message Buffers for CAN1 in DMA RAM */

unsigned int CAN1MsgBuf[32][8] __attribute__(space(dma));

DMA1STA = __builtin_dmaoffset(CAN1MsgBuf);

/* Configure Message Buffer 0 for Transmission and assign priority*/

C1TR23CONbits.TXEN0 = 0x1;

C1TR23CONbits.TX0PRI = 0x2;

/* WRITE TO MESSAGE BUFFER 0 */

/* CiTRBnSID = 0bxxx1 0010 0011 1111

IDE = 0b1

SRR = 0b1

SID<10:0> : 0b100 1000 1111 */

CAN1MsgBuf[2][0] = 0x123F;

/* CiTRBnEID = 0bxxxx 1111 0000 0000

EID<17:6> = 0b1111 0000 0000 */

CAN1MsgBuf[2][1] = 0x0F00;

/* CiTRBnDLC = 0b0000 1110 xxx0 1111

EID<17:6> = 0b000011

RTR = 0b1

RB1 = 0b0

RB0 = 0b0

DLC = 0b0 */

CAN1MsgBuf[2][2] = 0x0E00;

/* THERE ARE NO DATA BYTES FOR A REMOTE MESSAGE */

/* REQUEST MESSAGE BUFFER 2 TRANSMISSION */

C1TR23CONbits.TXREQ2 = 0x1;

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9.0 RECEIVING CAN MESSAGES

The CAN module can receive both standard and extended frames on the CAN bus node.

Moreover, it has the additional capability of automatically transferring received messages to user-

defined buffers in DMA RAM, thereby eliminating the need for the user application to explicitly

copy messages from hardware registers to user-defined buffers. The storage format of each

message within the DMA buffer is identical to that of transmit buffers, with each message

(including the associated status register) occupying eight words in DMA RAM.

The two main stages that constitute the CAN reception process are described in the following

section. Figure 9-1 and Figure 9-4 are examples of a simplified reception process.

9.1 Message Reception and Acceptance Filtering

As shown in Figure 9-1, every incoming message on the bus is received into a Message

Assembly Buffer and its identifier field is compared with a set of 16 user-defined acceptance

filters. Each received standard data frame contains an 11-bit Standard Identifier (SID), and each

extended data frame contains an 11-bit SID and an 18-bit Extended Identifier (EID). If all bits in

the incoming identifier completely match the corresponding bits in any of the acceptance filters,

the CAN module generates a DMA transfer request to the DMA Controller so that the message

can be received into the appropriate buffer in DMA RAM.

Figure 9-1: Message Reception and Acceptance Filtering

SID EID

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

Filter 0

Filter 1

Filter 2

Filter 3

Filter 4

Filter 5

Filter 6

Filter 7

Filter 8

Filter 9

Filter 10

Filter 11

Filter 12

Filter 13

Filter 14

Filter 15

Identifier

Comparison

CAN Data Frames

Filter Match (DMA Transfer Request)

Message

Assembly

Buffer

Acceptance

Filters (0-15)

User-Defined

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9.1.1 ACCEPTANCE FILTERS

Figure 9-2 shows the incoming message identifier in comparison with filter/mask bits for standard

frames. Figure 9-3 shows the incoming message identifier in comparison with filter/mask bits for

extended frames.

Figure 9-2: Acceptance Filtering for a Standard Message

Figure 9-3: Acceptance Filtering for an Extended Message

Acceptance Filters 0-15 can be individually enabled or disabled using the Enable Filter (FLTENx)

bits in the CAN Acceptance Filter Enable (CxFEN1[15:0]) register. The value of ‘x’ signifies the

Acceptance Filters 0-15 specify identifiers that must be contained in an incoming message for its

contents to be passed to a receive buffer. Each of these filters consists of two registers: one for

Standard Identifiers and the other for Extended Identifiers. These registers are identified as:

•CxRXFnSID: CAN Acceptance Filter n Standard Identifier register (where n = 0-15)

•CxRXFnEID: CAN Acceptance Filter n Extended Identifier register (where n = 0-15)

SID10 SID9

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 B

its

ACK

2 Bits

EOF

7 Bits

IFS

3 Bits

SID1

11-Bit Identifier

RB0 DATA

8 Bits

SID0

SID10 SID9 SID1 SID0 EXIDE CxRXFnSID

CxRXMnSIDSID10 SID9 SID1 SID0 MIDE

Accept/Reject Message

SID10 SID1

IDENTIFIER

11 Bits

DLC

4 Bits

CRC

16 Bits

ACK EOF

7 Bits

IFS

3 Bits

SID0 29-Bit Identifier

IDENTIFIER

18 Bits

EID17 EID1 EID0

CxRXMnSID

CxRXFnSID

EID15 EID14 EID0

CxRXMnEID

SID10 SID0 EID16EXIDE EID17

SID10 SID0 EID16 EID14 EID0MIDE EID17 EID15

CxRXFnEID

Accept/Reject Message

2 Bits

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9.1.2 ACCEPTANCE FILTER MASKS

As shown in Figure 9-2 and Figure 9-3, an acceptance filter mask determines which bits in the

incoming message identifiers are examined with the acceptance filters.

Acceptance filters optionally select one of the acceptance filter masks using the Mask Source for

Filter n (FnMSK[1:0]) bits in the CxFMSKSEL1 and CxFMSKSEL2 registers:

•CxFMSKSEL1[FnMSK]: Mask Selection for Filters 0-7

•CxFMSKSEL2[FnMSK]: Mask Selection for Filters 8-15

The selection values for the FnMSK[1:0] bits are shown in Table 9-1.

Table 9-1: FnMSK[1:0] Selections and Values

Table 9-2 is a truth table that indicates how each bit in the identifier is compared to the masks

and filters to determine if the message should be accepted or rejected. The mask bit essentially

determines which bits to apply the filter to. If any mask bit is set to a zero, that bit is automatically

accepted, regardless of the filter bit.

9.1.3 MESSAGE TYPE SELECTION

The Extended Identifier Enable (EXIDE) bit in the CAN Acceptance Filter Standard Identifier

messages. The Identifier Receive Mode (MIDE) bit in the CAN Acceptance Filter Mask Standard

Identifier Register n (CxRXMnSID[3]) enables the EXIDE (CxRXFnSID[3]) bit. If the MIDE

(CxRXMnSID[3]) bit is set, only the type of message selected by the EXIDE bit is accepted. If

MIDE is clear, the EXIDE bit is ignored and all messages that match the filter are accepted.

Table 9-3 shows the bit settings and resulting selection.

Table 9-3: EXIDE and MIDE Selections

Value Selection

00 Select Acceptance Filter Mask 0

01 Select Acceptance Filter Mask 1

10 Select Acceptance Filter Mask 2

11 Reserved

Table 9-2: Acceptance Filter/Mask Truth Table

Mask (SIDx/EIDx) Filter (SIDx/EIDx) Message (SIDx/EIDx) Accept or Reject Bit x

0 x x Accept

1 0 0 Accept

1 0 1 Reject

1 1 0 Reject

1 1 1 Accept

EXIDE MIDE Selection

0 1 Acceptance filter to check for Standard Identifier.

1 1 Acceptance filter to check for Extended Identifier.

x 0 Acceptance filter to check for Standard/Extended Identifier.

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9.1.4 ACCEPTANCE FILTER CONFIGURATION

Example 9-1 illustrates the code to configure Acceptance Filter 0 to receive Standard Identifier

messages using the Acceptance Filter Mask register to mask the SID[2:0] bits.

Example 9-1: Code Example for Filtering Standard Data Frame

/* Enable Window to Access Acceptance Filter Registers */

C1CTRL1bits.WIN=0x1;

/* Select Acceptance Filter Mask 0 for Acceptance Filter 0 */

C1FMSKSEL1bits.F0MSK=0x0;

/* Configure Acceptance Filter Mask 0 register to mask SID<2:0>

Mask Bits (11-bits) : 0b000 0000 0111 */

C1RXM0SIDbits.SID = 0x0007;

/* Configure Acceptance Filter 0 to match standard identifier

Filter Bits (11-bits): 0b011 1010 xxx */

C1RXF0SIDbits.SID = 0x01D0;

/* Acceptance Filter 0 to check for Standard Identifier */

C1RXM0SIDbits.MIDE = 0x1;

C1RXF0SIDbits.EXIDE= 0x0;

/* Acceptance Filter 0 to use Message Buffer 10 to store message */

C1BUFPNT1bits.F0BP = 0xA;

/* Filter 0 enabled for Identifier match with incoming message */

C1FEN1bits.FLTEN0=0x1;

/* Clear Window Bit to Access CAN Control Registers */

C1CTRL1bits.WIN=0x0;

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Example 9-2 illustrates the code to configure Acceptance Filter 2 to receive Extended Identifier

messages using the Acceptance Filter Mask register to mask the EID[5:0] bits.

Example 9-2: Code Example for Filtering Extended Data Frame

/* Enable window to access acceptance filter registers */

C1CTRL1bits.WIN = 0x1;

/* Select Acceptance Filter Mask 1 for Acceptance Filter 2 */

C1FMSKSEL1bits.F2MSK=0x1;

/* Configure Acceptance Filter Mask 1 register to mask EID<5:0>

Mask Bits (29-bits) : 0b0 0000 0000 0000 0000 0000 0011 1111

SID<10:0> : 0b00000000000 ..SID<10:0> or EID<28:18>

EID<17:16> : 0b00 ..EID<17:16>

EID<15:0> : 0b0000000000111111 ..EID<15:0> */

C1RXM1SIDbits.SID 0x0; =

C1RXM1SIDbits.EID 0x0; =

C1RXM1EIDbits.EID 0x3F; =

/* Configure Acceptance Filter 2 to match extended identifier

Filter Bits (29-bits) : 0b1 1110 0000 00 1111 0101 10xx xxxx11

SID<10:0> : 0b11110000000 ..SID<10:0> or EID<28:18>

EID<17:16> : 0b ..EID<17:16>11

EID<15:0> : 0b1111010110xxxxxx ..EID<15:0> */

C1RXF2SIDbits.SID = 0x780;

C1RXF2SIDbits.EID = 0x3;

C1RXM2EIDbits.EID 0xF680; =

/* Acceptance Filter 2 to check for Extended Identifier */

C1RXM1SIDbits.MIDE = 0x1;

C1RXF2SIDbits.EXIDE= 0x1;

/* Acceptance Filter 2 to use Message Buffer 5 to store message */

C1BUFPNT1bits.F2BP = 0x6;

/* Enable Acceptance Filter 2 */

C1FEN1bits.FLTEN1=0x1;

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9.2 Buffer Selection and DMA Transfer

As shown in Figure 9-4, if a filter match occurs, a DMA transfer request is generated by the CAN

module to the DMA Controller to automatically copy the received message into the appropriate

message buffer in a user-defined DMA RAM area. The CAN module supports up to 32 message

buffers. The user application can use the DMA Buffer Size (DMABS[2:0]) bits in the CAN FIFO

Control (CxFCTRL[15:13]) register to select either 4, 6, 8, 12, 16, 24 or 32 message buffers. The

selection of the receive buffer index (and therefore, the DMA RAM addresses in which a

message is written by the DMA Controller) is dependent on which filter matched the incoming

identifier and is user-configurable. The DMA Controller moves the data into the appropriate

addresses in the DMA RAM area and generates a DMA interrupt after the user-specified number

of words are transferred. Please refer to Section 10.0 “DMA Controller Configuration” for

more details on DMA channel configuration for CAN data transfers.

Figure 9-4: Buffer Selection and DMA Transfer

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

Filter 0

Filter 1

Filter 2

Filter 3

Filter 4

Filter 5

Filter 6

Filter 7

Filter 8

Filter 9

Filter 10

Filter 11

Filter 12

Filter 13

Filter 14

Filter 15

Identifier

Comparison

Filter Match

Message

Assembly

Buffer

Acceptance

Filters

(0-15)

User-Defined

F0BP[3:0]

F1BP[3:0]

F2BP[3:0]

F3BP[3:0]

F4BP[3:0]

F5BP[3:0]

F6BP[3:0]

F7BP[3:0]

F8BP[3:0]

F9BP[3:0]

F10BP[3:0]

F11BP[3:0]

F12BP[3:0]

F13BP[3:0]

F14BP[3:0]

F15BP[3:0]

F1BP[3:0] = 0111

Message Buffer 0

Message Buffer 1

Message Buffer 7

Message Buffer 31

CAN Buffers in DMA RAM

DMA

Transfer

Start of CAN Buffers

x16

Message Stored Here

Filter Buffer Pointers (0-15)

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9.2.1 BUFFER SELECTION

There are four Acceptance Filter Buffer Pointer registers that select which message buffer the

received message is stored into for Acceptance Filters 0 to 15.

•CxBUFPNT1[FnBP]: Buffer pointer for Acceptance Filters 0-3

•CxBUFPNT2[FnBP]: Buffer pointer for Acceptance Filters 4-7

•CxBUFPNT3[FnBP]: Buffer pointer for Acceptance Filters 8-11

•CxBUFPNT4[FnBP]: Buffer pointer for Acceptance Filters 12-15

When the incoming message identifier is matched by one of the acceptance filters, the internal

logic looks up the buffer pointer (FnBP[3:0]) and uses that as an address for the corresponding

message buffer. The address is provided to the DMA channel by the peripheral. Hence, the DMA

channel must be configured in Peripheral Indirect mode.

The values for FnBP[3:0] are interpreted as follows:

9.2.2 RECEIVING MESSAGES INTO MESSAGE BUFFERS 0-7

Message Buffers 0-7 can be configured to transmit or receive CAN messages using the TX/RX

Buffer Selection (TXENm) bit in the CAN TX/RX Buffer m Control Register (CxTRmnCON[7]).

The Acceptance Filter Buffer Pointer (FnBP) selects one of the message buffers to store a

received message, provided it is configured as a receive buffer (TXENm = 0).

If a message buffer is set up as a transmitter with the RTRENn (CxTRmnCON[10]) bit set, and

an acceptance filter pointing to that message buffer detects a message, the message buffer will

handle the RTR rather than store the message. This is the only case where the Acceptance Filter

Buffer Pointer (FnBP) points to a message buffer that is configured for transmission (TXENn = 1).

9.2.3 RECEIVING MESSAGES INTO MESSAGE BUFFERS 8-14

Message Buffers 8-14 are receive buffers. The Acceptance Filter Buffer Pointer (FnBP)

determines which message buffer to use.

9.2.4 RECEIVING MESSAGES INTO MESSAGE BUFFERS 15-31

Message Buffers 15-31 are receive buffers and are only usable as FIFO buffers because the

Acceptance Filter Buffer Pointer (FnBP[3:0]) bits can only directly address 16 entities. When

FnBP[3:0] = 1111, the results of a hit on that filter will write to the next available buffer location

within the FIFO.

0000 Message is received in Message Buffer 0

0001 Message is received in Message Buffer 1

•

1110 Message is received in Message Buffer 14

1111 Message is received in Receive FIFO Buffer

Note: Multi-message buffering can be implemented by a user application by configuring

multiple acceptance filters with the same value. In this case, a received message may

match multiple filters and the CAN module will assign the message to the lowest

numbered matching filter pointing to an empty buffer.

Note: The user application should not set the Transmit Request (TXREQ) bit in the

CxTRmnCON register when the buffer is configured for receive operation

(TXEN = 0). This could result in unpredictable module behavior.

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9.3.1 RECEIVING MESSAGES INTO FIFO AREA

The acceptance filter stores the received message in the FIFO area when FnBP[3:0] = 1111. It

uses a simple buffer pointer, beginning with the start of the FIFO as defined above, and

incrementing sequentially through the set of buffers within the FIFO area. When the end of the

buffer is reached, the counter wraps and points to the start of the FIFO area.

The Write Pointer value is accessible and (only) readable by the application software in the FBPx

(CxFIFO[13:8]) bits. When the message is stored in the buffer, the RXFULx bit associated with

the buffer is set and the FIFO buffer counter increments.

If the FBP[5:0] bits value points to a buffer, and the RXFULx bit associated with that buffer is

already ‘1’ at the time of the filter hit and before writing of the message contents, the RXOVLx bit

associated with that buffer is set and the message is lost. After the message is lost, the FBP[5:0]

bits value increments normally.

If the FBP[5:0] value points to a transmit/receive buffer that is selected as a transmit buffer at the

time of the filter hit and before writing of the message contents, the RXOVLx bit associated with

that buffer is set and the message is lost. After the message is lost, the FBP[5:0] value

increments normally.

The application software unloads the FIFO by reading the contents of a buffer. Once the buffer

location is read, the application software clears the RXFULx bit corresponding to that buffer.

When an RXFULx bit is cleared, the number of that corresponding buffer, plus one, is written to

the FNRBx (CxFIFO[5:0]) bits by the module. Application software can (only) read this value, left

shift it by four bits and use it as an address offset for the next buffer to be read. The application

software should read the buffers and clear the corresponding RXFULx bit sequentially. If not, and

an RXFULx flag is set within a section of the FIFO intended to be available for writing, the

RXOVLx bit associated with that buffer is set and the message is lost. After the message is lost,

the FBP[5:0] value will increment, but FNRB[5:0] will not get incremented.

The module generates an interrupt condition if the FIFO is about to fill. This condition is computed

mathematically, as shown in Equation 9-4.

Equation 9-4: FIFO Interrupt Calculation

The interrupt is generated as the RXFULx bit is set for the buffer just written and after the FBPx

bit has been updated. The computation uses the updated FBPx value.

FNRB – FBP = 1

(FNRB = START) AND (FBP = END)

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9.4 FIFO Example

Figure 9-6 illustrates seven examples of FIFO operation. The cases illustrated assume that the

start of FIFO is set to Message Buffer 5 (FSAx (CxFCTRL[4:0]) = 101) and the end of FIFO is

set to Message Buffer 11 (DMABSx (CxFCTRL[15:13]) = 011).

•Case 1 is the initialized case of the FIFO before any messages are received. The FIFO

Buffer Pointer points to Message Buffer 5 (FRBx = 5) and the FIFO Next Read Buffer

Pointer points to Message Buffer 6 (FNRBx = 5).

•Case 2 shows the FIFO after one message is received and transferred to Message Buffer 5.

The FIFO Buffer Pointer is incremented (FBPx = 6) and the RXFULx status bit for Message

Buffer 5 is set (RXFULx = 1).

•Case 3 shows the FIFO after the sixth received message. The FIFO Buffer Pointer points to

the last location in the FIFO area (FBPx = 5 + 6 = 11) and the FIFO Next Read Pointer

points to the start of FIFO (FNRB = 5). In this case, FIFO is almost full and generates a

FIFO interrupt.

•Case 4 shows the FIFO after the application software reads the first received message.

When the application software clears the RXFULx status bit for Message Buffer 5, the

module writes the FIFO Next Read Buffer Pointer with MB5 plus 1 (FNRBx = 5 + 1 = 6).

•Case 5 shows the FIFO after the seventh message is received and written to Message

Buffer 11. The RXFUL status bit for Message Buffer 11 is set (RXFULx = 1). Instead of

incrementing, the FIFO Buffer Pointer is reloaded with the FIFO start address

(FBPx = FSAx = 5). Note that FBPx is now mathematically one less than FNRBx, which is the

condition that generates the FIFO interrupt at the time the RXFULx status bit is set for

Message Buffer 11.

•Case 6 shows the FIFO after the eighth message is received and written to Message

Buffer 5. Now the FIFO is full. There is no interrupt signal for this condition.

•Case 7 shows the FIFO after the ninth received message. Now the FIFO has overflowed.

The module sets the RXOVLx bit for the buffer intended for writing. The message is lost.

The module generates a receive overflow interrupt.

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Figure 9-6: Example of FIFO Operation

MB 11 – RXFULx = 0

MB 10 – RXFULx = 0

MB 9 – RXFULx = 0

MB 8 – RXFULx = 0

MB 7 – RXFULx = 0

MB 6 – RXFULx = 0

MB 5 – RXFULx = 0

MB 11 – RXFULx = 0

MB 10 – RXFULx = 0

MB 9 – RXFULx = 0

MB 8 – RXFULx = 0

MB 7 – RXFULx = 0

MB 6 – RXFULx = 0

MB 5 – RXFULx = 1

MB 11 – RXFULx = 0

MB 10 – RXFULx = 1

MB 9 – RXFULx = 1

MB 8 – RXFULx = 1

MB 7 – RXFULx = 1

MB 6 – RXFULx = 1

MB 5 – RXFULx = 1

MB 11 – RXFULx = 0

MB 10 – RXFULx = 1

MB 9 – RXFULx = 1

MB 8 – RXFULx = 1

MB 7 – RXFULx = 1

MB 6 – RXFULx = 1

MB 5 – RXFULx = 0

MB 11 – RXFULx = 1

MB 10 – RXFULx = 1

MB 9 – RXFULx = 1

MB 8 – RXFULx = 1

MB 7 – RXFULx = 1

MB 6 – RXFULx =

RXOVL

MB 5 – RXFULx = 1

MB 11 – RXFULx = 1

MB 10 – RXFULx = 1

MB 9 – RXFULx = 1

MB 8 – RXFULx = 1

MB 7 – RXFULx = 1

MB 6 – RXFULx = 1

MB 5 – RXFULx = 1

MB 11 – RXFUL = 1

MB 10 – RXFUL = 1

MB 9 – RXFUL = 1

MB 8 – RXFUL = 1

MB 7 – RXFUL = 1

MB 6 – RXFUL = 1

MB 5 – RXFUL = 0

Case 1: FIFO at Start

Case 5: FIFO 7th Write

(About to Fill)

Case 6: FIFO 8th Write FIFO Full

FNRBx = 6

FBPx = 5

FNRBx = 6

Case 7: FIFO 9th Write

FIFO Overflow

FBPx = 7

FNRBx = 6

FBPx = 11

Case 4: FIFO 1st Read

FNRBx = 5

FBPx = 11

FBPx = 6

FNRBx = 5

Case 2: FIFO 1st Write

Case 3: FIFO 6th Write

(About to Fill)

Legend: Shaded message buffers indicate the presence of a received message ready to be read by the user application.

MB n represents Message Buffers 5-11.

Write signifies that a message is stored in the FIFO message buffer and the RXFULx flag associated with that buffer

is set.

Read signifies that the application software unloads the FIFO message buffer by reading the contents of that buffer.

Once the buffer location is read, the application software clears the RXFULx bit corresponding to that buffer.

FBPx = 5

FBPx = 6

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9.5 DeviceNet™ Filtering

The DeviceNet filtering feature is based on CAN 2.0A protocol in which up to 18 bits of the Data

field can be compared with the EID of the message acceptance filter in addition to the SID.

The DeviceNet feature is enabled or disabled by the DeviceNet Filter Bit Number (DNCNT[4:0])

control bits in the CAN Control Register 2 (CxCTRL2[4:0]). The value specified in the DNCNTx

field determines the number of data bits to be used for comparison with the EID bits of the

message acceptance filter. If the DNCNTx (CxCTRL2[4:0]) bits are cleared, the DeviceNet

feature is disabled.

For a message to be accepted, the 11-bit SID must match the SID[10:0] bits in the message

acceptance filter and the first ‘n’ data bits in the message should match the EID[17:0] bits in the

message acceptance filter. For example, as shown in Figure 9-7, the first 18 data bits of the

received message are compared with the corresponding identifier bits (EID[17:0]) of the

message acceptance filter.

Figure 9-7: CAN Operation with DeviceNet™ Filtering

Note: The DeviceNet filtering feature will only function when all of the following are true:

• The message IDE bit = 0, which means the message is a Standard ID message

• The EXIDE bit in the CxRXFn register = 0

• The MIDE bit in the CxRXMn register = 1

• The value of the DNCNTx bits is non-zero

SID10 SID9

Identifier

11 Bits

EOF

7 Bits 3 Bits

SID0

Accept/Reject Message

IFS

Data Byte 0 Data Byte 1 Data Byte 2

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Data Byte 0 Data Byte 1 Data Byte 2Message SID[10:0]

SID10 SID9 SID0

EID17 EID16 EID10

EID9 EID8 EID2 EID1 EID0

Standard Message Data Frame

Message Acceptance Filter

SID[10:0]

Message Acceptance Filter

EID[0:17]

Note: The DeviceNet™ filtering configuration shown for the EIDx bits is DNCNT[4:0] = 10010.

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 62  2007-2020 Microchip Technology Inc.

9.5.1 FILTER COMPARISONS

Table 9-5 shows the filter comparisons configured by the DNCNT[4:0] (CxCTRL2[4:0]) control

bits. For example, if DNCNT[4:0] = 00011, only a message in which the 11-bit Standard Identifier

matches the SID acceptance filter (SID[10:0]) and bits 7, 6 and 5 of Data Byte 0 matching the

Extended Identifier filter (EID[0:2]) is accepted.

9.5.2 SPECIAL CASES

There may be special cases when the message contains fewer data bits than are called for by

the DeviceNet filter configuration.

•Case 1 – If the DNCNT[4:0] bits are greater than 18, indicating that the user application

selected a number of bits greater than the total number of EID bits, the filter comparison

terminates with the 18th bit of the data (bit 6 of Data Byte 2). If the SID and all 18 data bits

match, the message is accepted.

•Case 2 – If the DNCNT[4:0] bits are greater than 16, and the received message Data

Length Code (DLC) is 2 (indicating a payload of two data bytes), the filter comparison

terminates with the 16th bit of data (bit 0 of Data Byte 1). If the SID and all 16 bits match,

the message is accepted.

•Case 3 – If the DNCNT[4:0] bits are greater than 8, and the received message has

DLC = 1 (indicating a payload of one data byte), the filter comparison terminates with the

8th bit of data (bit 0 of Data Byte 0). If the SID and all 8 bits match, the message is

accepted.

•Case 4 – If the DNCNT[4:0] bits are greater than 0, and the received message has

DLC = 0, indicating no data payload, the filter comparison terminates with the Standard

Identifier. If the SID matches, the message is accepted.

Table 9-5: DeviceNet™ Filter Bit Configurations

DeviceNet™ Filter

Configuration

(DNCNT[4:0])

Received Message Data Bits to be Compared

(Byte[bits])

EID Bits Used for

Acceptance

Filter

00000 No Comparison No Comparison

00001 Data Byte 0[7] EID[17]

00010 Data Byte 0[7:6] EID[17:16]

00011 Data Byte 0[7:5] EID[17:15]

00100 Data Byte 0[7:4] EID[17:14]

00101 Data Byte 0[7:3] EID[17:13]

00110 Data Byte 0[7:2] EID[17:12]

00111 Data Byte 0[7:1] EID[17:11]

01000 Data Byte 0[7:0] EID[17:10]

01001 Data Byte 0[7:0] and Data Byte 1[7] EID[17:9]

01010 Data Byte 0[7:0] and Data Byte 1[7:6] EID[17:8]

01011 Data Byte 0[7:0] and Data Byte 1[7:5] EID[17:7]

01100 Data Byte 0[7:0] and Data Byte 1[7:4] EID[17:6]

01101 Data Byte 0[7:0] and Data Byte 1[7:3] EID[17:5]

01110 Data Byte 0[7:0] and Data Byte 1[7:2] EID[17:4]

01111 Data Byte 0[7:0] and Data Byte 1[7:1] EID[17:3]

10000 Data Byte 0[7:0] and Data Byte 1[7:0] EID[17:2]

10001 Byte 0[7:0] and Byte 1[7:0] and Byte 2[7] EID[17:1]

10010 Byte 0[7:0] and Byte 1[7:0] and Byte 2[7:6] EID[17:0]

10011 11111 to Invalid Selection Invalid Selection

 2007-2020 Microchip Technology Inc. DS70000185D-page 63

Enhanced CAN Module

10.0 DMA CONTROLLER CONFIGURATION

The CAN module uses a portion of DMA RAM for message buffers to support both transmission

and reception of CAN messages. The number of message buffers to be used by the CAN module

is specified by the DMA Buffer Size (DMABS[2:0]) bits in the CAN FIFO Control

(CxFCTRL[15:13]) register. The DMAxSTA register in the DMA controller defines the start of the

CAN buffer area. The DMA Controller moves data between CAN and the DMA message buffers

without CPU intervention.

The DMA Controller provides eight channels for data transfer between DMA RAM and the

dsPIC33F peripherals that are DMA ready. Two DMA channels are needed to support both CAN

message transmission and reception. Each channel has a DMA Request Register (DMAxREQ)

to assign an event based on which message transfer occurs, as shown in Table 10-1.

Table 10-1: DMA Channel Request

An example showing the use of DMA Channel 4 to access the CAN buffers is illustrated in

Figure 10-1.

Figure 10-1: CAN Message Buffer Memory Usage

Event IRQ Number to Initialize

DMAxREQ Register

CAN1 Reception 34

CAN1 Transmission 70

CAN2 Reception 55

CAN2 Transmission 71

16 Bits

MSb LSb

&_DMA_BASE

Message Buffer 0

Message Buffer 31

&_DMA_BASE + DMA4STA

Data Memory Map DMA RAM

SFR Space

X Data RAM

Y Data RAM

DMA RAM

X Data

Unimplemented

Note: Refer to the specific device data sheet for information on the DMA base address.

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 64  2007-2020 Microchip Technology Inc.

10.1 DMA Operation for Transmitting Data

The user application selects a message for transmission by setting the Message Send Request

(TXREQ) bit in the CAN TX/RX Buffer m Control (CxTRmnCON[3]) register. The CAN controller

uses DMA to read the message from the message buffer and transmit the message. The CAN

module generates a transmit data interrupt to start a DMA cycle. In response to the interrupt, the

DMA channel that is configured for CAN message transmission reads from the message buffer

in DMA RAM and stores the message in the CAN Transmit Data (CxTXD) register. Eight words

are transferred for every message transmitted by the CAN controller. Section 2.0 “CAN Mes-

sage Formats” provides the detailed layout of the transmit message buffer. Sample code for

configuring the DMA channel for CAN1 transmission is shown in Example 10-1.

Example 10-1: DMA Channel 0 Configuration for CAN1 Transmission

Note: Please refer to “Direct Memory Access (DMA)” (www.microchip.com/70182) in

the “dsPIC33/PIC24 Family Reference Manual” for more information for configuring

the DMA Controller.

/* Assign 32x8 Word Message Buffers for CAN1 in DMA RAM */

unsigned int CAN1MsgBuf[32][8] __atribute__((space(dma)));

/* Data Transfer Size: Word Transfer Mode */

DMA0CONbits.SIZE = 0x0;

/* Data Transfer Direction: DMA RAM to Peripheral */

DMA0CONbits.DIR = 0x1;

/* DMA Addressing Mode: Peripheral Indirect Addressing mode */

DMA0CONbits.AMODE = 0x2;

/* Operating Mode: Continuous, Ping-Pong modes disabled */

DMA0CONbits.MODE = 0x0;

/* Assign CAN1 Transmit event for DMA Channel 0 */

DMA0REQ = 70;

/* Set Number of DMA Transfer per CAN message to 8 words */

DMA0CNT = 7;

/* Peripheral Address: CAN1 Transmit Register */

DMA0PAD = &C1TXD;

/* Start Address Offset for CAN1 Message Buffer 0x0000 */

DMA0STA = __builtin_dmaoffset(CAN1MsgBuf);

/* Channel Enable: Enable DMA Channel 0 */

DMA0CONbits.CHEN = 0x1;

/* Channel Interrupt Enable: Enable DMA Channel 0 Interrupt */

IEC0bits DMA0IE = 1;

 2007-2020 Microchip Technology Inc. DS70000185D-page 65

Enhanced CAN Module

10.1.1 DMA Operation for Receiving Data

When the CAN controller completes a received message (eight words), the completed message

is transferred to a message buffer in DMA RAM by the DMA. The CAN module generates a

receive data interrupt to start a DMA cycle. In response to this interrupt, the DMA channel that is

configured for CAN message reception reads from the CAN Receive Data (CxRXD) register and

stores the message in the DMA RAM buffer. Eight words are transferred for every message that

is received by the CAN controller. The detailed layout of the received message is provided in

Section 2.0 “CAN Message Formats”. Sample code for configuring the DMA channel for CAN1

reception is shown in Example 10-1.

Example 10-1: DMA Channel 1 Configuration for CAN1 Reception

Note: Please refer to “Direct Memory Access (DMA)” (www.microchip.com/70182) in

the “dsPIC33/PIC24 Family Reference Manual” for more information for configuring

the DMA Controller.

/* Data Transfer Size: Word Transfer Mode */

DMA1CONbits.SIZE = 0x0;

/* Data Transfer Direction: Peripheral to DMA RAM */

DMA1CONbits.DIR = 0x0;

/* DMA Addressing Mode: Peripheral Indirect Addressing mode */

DMA1CONbits.AMODE = 0x2;

/* Operating Mode: Continuous, Ping-Pong modes disabled */

DMA1CONbits.MODE = 0x0;

/* Assign CAN1 Receive event for DMA Channel 0 */

DMA1REQ = 34;

/* Set Number of DMA Transfer per CAN message to 8 words */

DMA1CNT = 7;

/* Peripheral Address: CAN1 Receive Register */

DMA1PAD = &C1RXD;

/* Start Address Offset for CAN1 Message Buffer 0x0000 */

DMA1STA = 0x0000;

/* Channel Enable: Enable DMA Channel 1 */

DMA1CONbits.CHEN = 0x1;

/* Channel Interrupt Enable: Enable DMA Channel 1 Interrupt */

IEC0bits.DMA1IE = 1;

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 66  2007-2020 Microchip Technology Inc.

11.0 CAN ERROR MANAGEMENT

11.1 CAN Bus Errors

The CAN protocol defines five different ways of detecting errors.

• Bit Error

• Acknowledge Error

• Form Error

• Stuffing Error

• CRC Error

The bit error and the Acknowledge error occur at the bit level; the other three errors occur at the

message level.

11.1.1 BIT ERROR

A node that is sending a bit on the bus also monitors the bus. A bit error is detected when the

monitored bit value monitored is different from the sent bit value. An exception is when a

recessive bit is sent during the stuffed bit stream of the Arbitration field or during the ACK slot. In

this case, no bit error occurs when a dominant bit is monitored. A transmitter sending a passive

error frame and detecting a dominant bit does not interpret this as a bit error.

11.1.2 ACKNOWLEDGE ERROR

In the Acknowledge field of a message, the transmitter checks if the Acknowledge slot (which it

has sent out as a recessive bit) contains a dominant bit. If not, this implies that no other node has

received the frame correctly. An Acknowledge error has occurred, and as a result, the message

must be repeated.

11.1.3 FORM ERROR

A form error is detected when a fixed form bit field (EOF, Interframe Space, Acknowledge

Delimiter or CRC Delimiter) contains one or more illegal bits. For a receiver, a dominant bit during

the last bit of End-of-Frame is not treated as a form error.

11.1.4 STUFFING ERROR

A stuffing error is detected at the bit time of the 6th consecutive equal bit level in a message field

that should be coded by the method of bit stuffing.

11.1.5 CRC ERROR

The node transmitting a message computes and transmits the CRC corresponding to the

transmitted message. Every receiver on the bus performs the same CRC calculation as the

transmitter. A CRC error is detected if the calculated result is not the same as the CRC value

obtained from the received message.

11.2 Fault Confinement

Every CAN controller on a bus tries to detect the errors outlined above within each message. If

an error is found, the discovering node transmits an error frame, thus destroying the bus traffic.

The other nodes detect the error caused by the error frame (if they have not already detected the

original error) and take appropriate action (i.e., discard the current message).

The CAN module maintains two error counters:

• Transmit Error Counter: TERRCNT[7:0] (CxEC[15:8])

• Receive Error Counter: RERRCNT[7:0] (CxEC[7:0])

There are several rules governing how these counters are incremented and/or decremented. In

essence, a transmitter detecting a Fault increments its transmit error counter faster than the

listening nodes can increment their receive error counter. This is because there is a good chance

that it is the transmitter that is at Fault.

Note: The error counters are modified according to the CAN 2.0B specification.

 2007-2020 Microchip Technology Inc. DS70000185D-page 67

Enhanced CAN Module

A node starts out in Error Active mode. When any one of the two error counters equals or

exceeds a value of 127, the node enters a state known as Error Passive. When the transmit error

counter exceeds a value of 255, the node enters the Bus Off state.

• An Error Active node transmits an Active Error frame when it detects errors.

• An Error Passive node transmits a Passive Error frame when it detects errors.

• A node that is Bus Off transmits nothing on the bus.

In addition, the CAN module employs an error warning feature that warns the user application

(when the transmit error counter equals or exceeds 96) before the node enters the Error Passive

state, as illustrated in Figure 11-1.

Figure 11-1: Error Modes

Bus

Off

Error

Active

Error

Passive

RERRCNT > 127 or

TERRCNT > 127

RERRCNT < 127 and

TERRCNT < 127

TERRCNT > 255

128 Occurrences of

11 Consecutive

“Recessive” Bits

Reset

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 68  2007-2020 Microchip Technology Inc.

11.2.1 TRANSMITTER IN ERROR PASSIVE STATE

The Transmitter in Error State Bus Passive bit, TXBP (CxINTF[12]), is set when the transmit error

counter equals or exceeds 128 and generates an error interrupt, ERRIF (CxINTF[5]), upon entry

into the Error Passive state. The Transmit Error Passive flag is cleared automatically by the

hardware if the transmit error counter becomes less than 128.

11.2.2 RECEIVER IN ERROR PASSIVE STATE

The Receiver in Error Bus Passive bit, RXBP (CxINTF[11]), is set when the receive error counter

equals or exceeds 128 and generates an error interrupt, ERRIF, upon entry into the Error Passive

state. The Receive Error Passive flag is cleared automatically by the hardware if the receive error

counter becomes less than 128.

11.2.3 TRANSMITTER IN BUS OFF STATE

The Transmitter in Error State Bus Off bit, TXBO (CxINTF[13]), is set when the transmit error

counter equals or exceeds 256 and generates an error interrupt, ERRIF.

11.2.4 TRANSMITTER IN ERROR WARNING STATE

The Transmitter in Error State Warning bit, TXWAR (CxINTF[10]), is set when the transmit error

counter is in the range of 96 and 127 (inclusive), and generates an error interrupt, ERRIF, upon

entry into the Error Warning state. The Transmitter in Error State Warning flag is cleared auto-

matically by the hardware if the transmit error counter becomes less than 96 or more than 127

(i.e., the CAN module has entered a Bus Passive state).

11.2.5 RECEIVER IN ERROR WARNING STATE

The Receiver in Error State Warning bit, RXWAR (CxINTF[9]), is set when the receive error

counter is in the range of 96 and 127 (inclusive), and generates an error interrupt, ERRIF, upon

entry into the Error Warning state. The Receiver in Error State Warning flag is cleared automati-

cally by the hardware if the receive error counter becomes less than 96 or more than 127 (i.e.,

the CAN module has entered a Bus Passive state).

Additionally, there is an Error State Warning flag, EWARN (CxINTF[8]), which is set if at least one

of the error counters equals or exceeds the error warning limit of 96. EWARN is Reset if both

error counters are less than the error warning limit.

 2007-2020 Microchip Technology Inc. DS70000185D-page 69

Enhanced CAN Module

12.0 CAN INTERRUPTS

The CAN module generates three different interrupts, each with its own interrupt vector, interrupt

enable control bit, interrupt status flag and interrupt priority control bit. These interrupts are:

•CxTX – CAN Transmit Data Request Interrupt

•CxRX – CAN Receive Data Ready Interrupt

•Cx – CAN Event Interrupt

12.1 CAN Transmit Data Request Interrupt

The transmit data request interrupt represents the transmission of a single word in a CAN mes-

sage through the CAN Transmit Data (CxTXD) register. The user application needs to assign the

CAN transmit data request interrupt to a DMA channel to automatically transfer messages from

the appropriate DMA RAM buffers to the CAN module (CxTXD register).

12.2 CAN Receive Data Ready Interrupt

The receive data request interrupt represents the reception of a single word of an CAN message

through the CAN Receive Data (CxRXD) register. The user application needs to assign the CAN

receive data ready interrupt to a DMA channel to automatically transfer messages from the CAN

module (CxRXD register) to the appropriate DMA RAM buffers.

12.3 CAN Event Interrupt

The CAN event interrupt has seven main sources, each of which can be individually enabled. The

CAN Interrupt Flag (CxINTF) register contains the interrupt flags and the CAN Interrupt Enable

(CxINTE) register contains the enable bits. The Interrupt Flag Code bits (ICODE[6:0]) in the CAN

Interrupt Code (CxVEC[6:0]) register can be used in combination with a jump table for efficient

handling of interrupts. All interrupts have one source, with the exception of the error interrupt. Any

of five error interrupt sources (TX Error Warning, RX Error Warning, TX Error Passive, RX Error

Passive and TX Bus Off) can set an Error Interrupt Flag (ERRIF). The source of the error interrupt

is determined by reading the CxINTF register. The CAN module will generate an CAN event

interrupt (Cx interrupt) only if at least one of the conditions in the CxINTF register is active, and the

corresponding interrupt is enabled in the CxINTE register. The CPU will vector to the CAN event

Interrupt Service Routine if the CxIF and the CxIE bits are set. To clear the interrupt, the ERRIF flag

must be cleared. Clearing the ERRIF flag will not affect the status of TX Error Warning, RX Error

Warning, TX Error Passive, RX Error Passive and TX Bus Off flags. These bits are read-only bits

and cannot be cleared by software.

Figure 12-1 shows CAN event interrupt generation from various interrupt sources:

12.3.1 TRANSMIT BUFFER INTERRUPT

The Message Buffers 0 to 7 that are configured for message transmission generate the Transmit

Buffer Interrupt bit, TBIF (CxINTF[0]), after the CAN message is transmitted. The ICODEx bits

indicate the specific message buffer that generated the transmit buffer interrupt. Transmit buffer

interrupts must be cleared in the Interrupt Service Routine by clearing the TBIF bit.

12.3.2 RECEIVE BUFFER INTERRUPT

When a message is successfully received and loaded into one of the receive buffers (Message

Buffers 0 to 31), the Receive Buffer Interrupt bit, RBIF (CxINTF[1]) is activated after the module

sets the RXFULx bit (CxRXFULn). The ICODEx bits indicate the particular buffer which gener-

ated the interrupt. The receive buffer interrupt must be cleared in the Interrupt Service Routine

by clearing the RBIF bit.

Note: The ICODE[6:0] bits will reflect the highest priority CAN interrupt condition that is

active. The interrupt should be enabled (the IE bit in the CxINTE register should be

set) and the interrupt condition should be active (the IF bit in the CxINTF register

should be set).

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 70  2007-2020 Microchip Technology Inc.

12.3.3 RECEIVE BUFFER OVERFLOW INTERRUPT

When a message is successfully received but the designated buffer is full, the RX Buffer Over-

flow Interrupt Flag, RBOVIF (CxINTF[2]), is activated after the module sets the RXOVFx bit

(CxRXOVFn). The Interrupt Flag Code (ICODE[6:0]) bits in the CAN Interrupt Code (CxVEC[6:0])

be cleared in the Interrupt Service Routine by clearing RBOVIF bit.

12.3.4 FIFO ALMOST FULL INTERRUPT

When the FIFO has only one remaining available buffer, the FIFO Almost Full Interrupt Flag,

FIFOIF (CxINTF[3]), is activated after the module sets the RXFULx bit for the next to last avail-

able buffer. The ICODEx bits indicate the FIFO overflow condition. The FIFO Almost Full Interrupt

must be cleared in the Interrupt Service Routine by clearing the FIFOIF bit.

12.3.5 ERROR INTERRUPT

The Error Interrupt, ERRIF (CxINTF[5]), is generated by five sources:

• TX Error Warning

• RX Error Warning

• TX Error Passive

• RX Error Passive

• TX Bus Off

The ICODEx bits indicate the error condition. The error interrupt must be cleared in the Interrupt

Service Routine by clearing the ERRIF bit.

12.3.6 WAKE-UP INTERRUPT

In Sleep mode, the device monitors the CAN Receive pin (CxRX) for bus activity. A wake-up

(WAKIF (CxINTF[6])) interrupt is generated when bus activity is detected. The ICODEx bits

indicate the wake-up condition. The wake-up interrupt must be cleared in the Interrupt Service

Routine by clearing the WAKIF bit.

12.3.7 INVALID MESSAGE RECEIVED INTERRUPT

The invalid message received interrupt is generated for any other type of errors during message

reception.

 2007-2020 Microchip Technology Inc. DS70000185D-page 71

Enhanced CAN Module

Figure 12-1: CAN Event Interrupts

TX0

TX7

TX Error Warn (TXWAR)

RX Error Warn (RXWAR)

RX Error Passive (RXBP)

TX Error Passive (TXBP)

TX Bus Off (TXBO)

TBIF

RBIF

RBOVIF

ERRIF

FIFO Interrupt

Wake-up

Invalid Message

FIFOIF

WAKIF

IVRIF

CxINTF

CAN Event Interrupt

Transmit Buffer Interrupt

Receive Buffer Interrupt

Receive Buffer Overflow Interrupt

Error Interrupt

RxFUL0

RxFUL31

RxOVF0

RxOVF31

dsPIC33F/PIC24H Family Reference Manual

DS70000185D-page 72  2007-2020 Microchip Technology Inc.

13.0 CAN LOW-POWER MODES

The CAN module can respond to the CPU PWRSAV instruction.

13.1 Sleep Mode

A CPU PWRSAV,1 instruction stops the crystal oscillator and shuts down all system clocks. The

user application must ensure that the module is not active when the CPU goes into Sleep mode.

To protect the CAN bus system from fatal consequences due to violations of the above rule, the

module drives the CxTX pin into the Recessive state while sleeping. The recommended

procedure is to bring the module into Disable mode before executing the CPU PWRSAV

instruction.

13.2 Idle Mode

A CPU PWRSAV,0 instruction signals the module to optionally shut down clocks. The module

powers down if the CAN Stop in Idle Mode (CSIDL) bit in CAN Control Register 1 (CxCTRL1[13])

is ‘1’. The user application must ensure that the module is not active when the CPU goes into

Idle mode. To protect the CAN bus system from fatal consequences due to violations of the

above rule, the module drives the CxTX pin into the Recessive state while sleeping. The

recommended procedure is to bring the module into Disable mode before executing the CPU

PWRSAV instruction.

13.3 Wake-up Functions

The module monitors the RX line for activity while the device is sleeping. If the WAKIE bit is set,

the module generates an interrupt if bus activity is detected. Due to the delays in starting up the

oscillator and CPU, the message activity that caused the wake-up is lost.

After the CPU wakes up from Sleep, the CPU executes the CAN event Interrupt Service Routine

(if interrupts are enabled); however, the CAN module itself would still be disabled. The CAN bus

wake-up feature only works when the device is in Sleep mode.

The module features a low-pass filter on the CxRX input line, which should be enabled when the

module is in CPU Sleep mode. This filter protects the module from wake-up due to short glitches

on the CAN bus. The filter is enabled by setting the WAKFIL bit (CxCFG2[14]).

14.0 CAN TIME STAMPING USING INPUT CAPTURE

The CAN module generates a signal that can be sent to a timer capture input whenever a valid

frame is accepted. This is useful for time stamping and network synchronization. Because the

CAN specification defines a frame to be valid if no errors occurred before the EOF field has been

transmitted successfully, the timer signal is generated immediately after the EOF. A pulse of one

bit time is generated.

Time stamping is enabled by the CAN Message Receive Timer Capture Event Enable bit,

CANCAP (CxCTRL1[3]). The IC2 capture input is used for time stamping.

Note: If the CAN capture is enabled, the IC2 pin becomes unusable as a general input

capture pin. In this mode, the IC2 channel derives its input signal from the C1RX or

C2RX pin instead of the IC2 pin.

 2007-2020 Microchip Technology Inc. DS70000185D-page 73

Enhanced CAN Module

15.0 RELATED APPLICATION NOTES

This section lists application notes that are related to this section of the manual. These

application notes may not be written specifically for the dsPIC33F/PIC24H product family, but the

concepts are pertinent and could be used with modification and possible limitations. The current

application notes related to the Enhanced Controller Area Network (Enhanced CAN Module)

module are:

Title Application Note #

No application notes at this time. N/A

Note: Please visit the Microchip website (www.microchip.com) for additional Application

Notes and code examples for the dsPIC33F/PIC24H family of devices.

Product specificaties

Merk:	Microchip
Categorie:	Niet gecategoriseerd
Model:	dsPIC33FJ256GP510

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