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 2008-2017 Microchip Technology Inc. DS70000323H-page 1

HIGHLIGHTS

This section of the manual contains the following major topics:

1.0 Introduction ....................................................................................................................... 2

2.0 Features............................................................................................................................ 3

3.0 Control Registers .............................................................................................................. 4

4.0 Architecture Overview..................................................................................................... 34

5.0 Module Description ......................................................................................................... 37

6.0 PWM Generator .............................................................................................................. 48

7.0 PWM Triggers ................................................................................................................. 62

8.0 PWM Interrupts............................................................................................................... 69

9.0 PWM Operating Modes................................................................................................... 70

10.0 PWM Fault Pins .............................................................................................................. 75

11.0 Special Features ............................................................................................................. 87

12.0 PWM Output Pin Control................................................................................................. 95

13.0 Immediate Update of PWM Duty Cycle .......................................................................... 98

14.0 Power-Saving Modes...................................................................................................... 99

15.0 External Control of Individual Time Base(s) (Current Reset Mode) .............................. 100

16.0 Application Information ................................................................................................. 101

17.0 PWM Interconnects with Other Peripherals .................................................................. 115

18.0 Related Application Notes............................................................................................. 118

19.0 Revision History............................................................................................................ 119

High-Speed PWM Module

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 2  2008-2017 Microchip Technology Inc.

1.0 INTRODUCTION

This section describes the High-Speed PWM module and its associated operational modes. The

High-Speed PWM module supports a wide variety of PWM modes and is ideal for power

conversion applications. Some of the common applications that the High-Speed PWM module

supports are:

• AC-to-DC Converters

• Power Factor Correction (PFC)

• Interleaved Power Factor Correction (IPFC)

• Inverters

• DC-to-DC Converters

• Battery Chargers

• Digital Lighting

• Uninterruptable Power Supply (UPS)

• AC and DC Motors

• Resonant Converters

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all dsPIC33/PIC24 devices.

Please consult the note at the beginning of the “High-Speed PWM” chapter in the

current device data sheet to check whether this document supports the device you

are using.

Device data sheets and family reference manual sections are available for download

from the Microchip Worldwide Web site at: http://www.microchip.com.

 2008-2017 Microchip Technology Inc. DS70000323H-page 3

High-Speed PWM Module

2.0 FEATURES

The High-Speed PWM module consists of the following major features:

• Up to Nine PWM Generators

• Two PWM Outputs per PWM Generator

• Individual Time Base and Duty Cycle Control for Each PWM Output

• Duty Cycle, Dead Time, Phase Shift and a Frequency Resolution of 1.04 ns

• Independent Fault and Current-Limit Inputs for All PWM Outputs

• Redundant Output

• True Independent Output

• Center-Aligned PWM mode

• Output Override Control

• Special Event Trigger

• Prescaler for Input Clock

• Dual Trigger to Analog-to-Digital Converter (ADC) per PWM Period

• PWM

L and PWM

H Output Pin Swapping

• Independent PWM Frequency, Duty Cycle and Phase-shift Changes

• Leading-Edge Blanking (LEB) Functionality

• PWM Capture Functionality

• Up to Two Master Time Bases

• Dead-Time Compensation

• PWM Chopping

• Support for Class B Protection of Fault Control Registers

Note: Duty cycle, dead time, phase shift and frequency resolution is 8.32 ns in Center-Aligned

PWM mode.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 4  2008-2017 Microchip Technology Inc.

3.0 CONTROL REGISTERS

This section outlines the specific functions of each register that controls the operation of the

High-Speed PWM module.

•PTCON: PWMx Time Base Control Register

- Enables or disables the High-Speed PWM module

- Sets the Special Event Trigger for the Analog-to-Digital Converter (ADC) and enables

or disables the primary Special Event Trigger interrupt

- Enables or disables immediate period updates

- Selects the synchronizing source for the master time base

- Specifies synchronization settings

•PTCON2: PWMx Clock Divider Select Register

- Provides the clock prescaler to all PWM time bases

•PTPER: PWMx Master Time Base Period Register

- Provides the PWM time period value

•SEVTCMP: PWMx Special Event Trigger Compare Register

- Provides the compare value that is used to trigger the ADC module and generates the

primary Special Event Trigger interrupt

•STCON: PWMx Secondary Master Time Base Control Register

- Sets the secondary Special Event Trigger for the ADC and enables or disables the

secondary Special Event Trigger interrupt

- Enables or disables immediate period updates for the secondary master time base

- Selects synchronizing source for the secondary master time base

- Specifies synchronization settings for the secondary master time base

•STCON2: PWMx Secondary Clock Divider Select Register

- Provides the clock prescaler to the PWM secondary master time base

•STPER: PWMx Secondary Master Time Base Period Register

- Provides the PWM time period value for the secondary master time base

•SSEVTCMP: PWMx Secondary Special Event Compare Register

- Provides the compare value for the secondary master time base that is used to trigger

the ADC module and generates the secondary Special Event Trigger interrupt

•CHOP: PWMx Chop Clock Generator Register

- Enables and disables the chop signal used to modulate the PWM outputs

- Specifies the period for the chop signal

•MDC: PWMx Master Duty Cycle Register

- Provides the PWM master duty cycle value

•PWMCONx: PWMx Control Register

- Enables or disables the Fault interrupt, current-limit interrupt and primary trigger interrupt

- Provides the interrupt status for the Fault interrupt, current-limit interrupt and primary

trigger interrupt

- Selects the type of time base (master time base or Independent Time Base, ITB)

- Selects the type of duty cycle (master duty cycle or independent duty cycle)

- Controls Dead-Time mode

- Enables or disables Center-Aligned mode

- Controls external PWM Reset operation

- Enables or disables immediate updates of the duty cycle, phase offset and

Independent Time Base period

•PDCx: PWMx Generator Duty Cycle Register

- Provides the duty cycle value for the PWMxH and PWMxL outputs if the master time

base is selected

- Provides the duty cycle value for the PWMxH output if the Independent Time Base is

selected

 2008-2017 Microchip Technology Inc. DS70000323H-page 5

High-Speed PWM Module

•PHASEx: PWMx Primary Phase-Shift Register

- Provides the phase-shift value for the PWMxH and/or PWMxL outputs if the master

time base is selected

- Provides the Independent Time Base period for the PWMxH and/or PWMxL outputs if

the Independent Time Base is selected

• DTRx: PWMx Dead-Time Register

- Provides the dead-time value for the PWMxH output if positive dead time is selected

- Provides the dead-time value for the PWMxL output if negative dead time is selected

•ALTDTRx: PWMx Alternate Dead-Time Register

- Provides the dead-time value for the PWMxL output if positive dead time is selected

- Provides the dead-time value for the PWMxH output if negative dead time is selected

•SDCx: PWMx Secondary Duty Cycle Register

- Provides the duty cycle value for the PWMxL output if Independent Time Base is

selected

•SPHASEx: PWMx Secondary Phase-Shift Register

- Provides the phase shift for the PWMxL output if the master time base and Independent

Output mode are selected

- Provides the Independent Time Base period value for the PWMxL output if the

Independent Time Base and Independent Output mode are selected

•TRGCONx: PWMx Trigger Control Register

- Enables the PWMx trigger postscaler start event

- Specifies the number of PWM cycles to skip before generating the first trigger

- Enables or disables the primary PWM trigger event with the secondary PWM trigger

event

•IOCONx: PWMx I/O Control Register

- Enables or disables the PWM pin control feature (PWM control or GPIO)

- Controls the PWMxH and PWMxL output polarity

- Controls the PWMxH and PWMxL output if any of the following modes are selected:

• Complementary mode

• Push-Pull mode

• True Independent mode

•FCLCONx: PWMx Fault Current-Limit Control Register

- Selects the current-limit control signal source

- Selects the current-limit polarity

- Enables or disables the Current-Limit mode

- Selects the Fault control signal source

- Configures the Fault polarity

- Enables or disables the Fault mode

•TRIGx: PWMx Primary Trigger Compare Value Register

- Provides the compare value to generate the primary PWM trigger

•STRIGx: PWMx Secondary Trigger Compare Value Register

- Provides the compare value to generate the secondary PWM trigger

•LEBCONx: PWMx Leading-Edge Blanking Control Register (Version 1)

- Selects the rising or falling edge of the PWM output for LEB

- Enables or disables LEB for Fault and current-limit inputs

•LEBCONx: PWMx Leading-Edge Blanking Control Register (Version 2)

- Selects the rising or falling edge of the PWM output for Leading-Edge Blanking (LEB)

- Enables or disables LEB for Fault and current-limit inputs

- Specifies the state of blanking for the Fault input and current-limit signals when the

selected blanking signal (PWMxH, PWMxL or other specified signal by the PWM State

Blank Source Select bits (BLANKSEL<3:0>) in the PWMx Auxiliary Control

(AUXCONx<11:8>) register) is high or low

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 6  2008-2017 Microchip Technology Inc.

•LEBDLYx: PWMx Leading-Edge Blanking Delay Register

- Specifies the blanking time for the selected Fault input and current-limit signals

•AUXCONx: PWMx Auxiliary Control Register

- Enables or disables the high-resolution PWM period and the duty cycle in order to

reduce the system power consumption

- Selects the state blanking signal for the current-limit signals and the Fault inputs

•PWMCAPx: PWMx Primary Time Base Capture Register

- Provides the captured Independent Time Base value when a leading-edge is detected

on the current-limit input

•PWMKEY: PWMx Protection Lock/Unlock Key Register

- Enables write protection of the PWMx Fault Control registers, IOCONx and FCLCONx,

for providing Class B Fault protection

 2008-2017 Microchip Technology Inc. DS70000323H-page 7

High-Speed PWM Module

R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0

PTEN

(3)

— PTSIDL SESTAT SEIEN EIPU

(1)

SYNCPOL

(1, )2

SYNCOEN

(1, )2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SYNCEN

(1, )2

SYNCSRC<2:0>

(1, )2

SEVTPS<3:0>

(1)

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PTEN: PWM Module Enable bit

( )3

1 = PWM module is enabled

0 = PWM module is disabled

bit 14 Unimplemented: Read as ‘0’

bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit

1 = PWM time base halts in CPU Idle mode

0 = PWM time base runs in CPU Idle mode

bit 12 SESTAT: Special Event Trigger Interrupt Status bit

1 = Special Event Trigger interrupt is pending

0 = Special Event Trigger interrupt is not pending

This bit is cleared by setting SEIEN = 0.

bit 11 SEIEN: Special Event Trigger Interrupt Enable bit

1 = Special Event Trigger interrupt is enabled

0 = Special Event Trigger interrupt is disabled

bit 10 EIPU: Enable Immediate Period Updates bit

( )1

1 = Active Period register is updated immediately

0 = Active Period register updates occur on PWM cycle boundaries

bit 9 SYNCPOL: Synchronize Input and Output Polarity bit

( , )1 2

1 = SYNCIx/SYNCOx polarity is inverted (active-low)

0 = SYNCIx/SYNCOx is active-high

bit 8 SYNCOEN: Primary Time Base Sync Enable bit

( , )1 2

1 = SYNCOx output is enabled

0 = SYNCOx output is disabled

bit 7 SYNCEN: External Time Base Synchronization Enable bit

( , )1 2

1 = External synchronization of primary time base is enabled

0 = External synchronization of primary time base is disabled

bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits

( , )1 2

011 = SYNCI4

010 = SYNCI3

001 = SYNCI2

000 = SYNCI1

Note 1: These bits should be changed only when PTEN = 0.

2: The PWM time base synchronization must only be used in the master time base with no phase shifting.

3: When the PWM module is enabled by setting PTCON<15> = 1, a delay will be observed before the PWM

outputs start switching. This delay is equal to:

PWM Turn-on Delay = (2/ACLK) + (3  (PCLKDIV<2:0> Setting)/ACLK) + 15 ns

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 8  2008-2017 Microchip Technology Inc.

bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits

( )1

1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event

•

0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event

0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event

Note 1: These bits should be changed only when PTEN = 0.

2: The PWM time base synchronization must only be used in the master time base with no phase shifting.

3: When the PWM module is enabled by setting PTCON<15> = 1, a delay will be observed before the PWM

outputs start switching. This delay is equal to:

PWM Turn-on Delay = (2/ACLK) + (3  (PCLKDIV<2:0> Setting)/ACLK) + 15 ns

 2008-2017 Microchip Technology Inc. DS70000323H-page 9

High-Speed PWM Module

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>

( )1,2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits

( )1,2

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

2: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty

cycle, phase shift, dead time, triggers, Leading-Edge Blanking (LEB) and PWM capture.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 10  2008-2017 Microchip Technology Inc.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

PTPER<15:8>

( , )1 2

bit 15 bit 8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0

PTPER<7:0>

( , )1 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PTPER<15:0>: PWM Master Time Base (PMTMR) Period Value bits

( , )1 2

Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.

2: Any period value that is less than 0x0028 must have the Least Significant 3 bits (LSbs) set to ‘0’. This

yields a period resolution of 8.32 ns (at the fastest Auxiliary Clock rate) for these very short PWM period

pulses.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SEVTCMP<12:5>

( , , )123

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SEVTCMP<4:0>

( , , )123

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 SEVTCMP<12:0>: Primary Special Event Trigger Compare Count Value bits

( , , )123

bit 2-0 Unimplemented: Read as ‘0’

Note 1: 1 LSb = 1.04 ns; therefore, the minimum SEVTCMP resolution is 8.32 ns at the fastest PWM clock divider

setting (PTCON2<2:0> = 000).

2: The Special Event Trigger is generated on a compare match with the PWM Master Time Base Counter

(PMTMR).

3: The SEVTCMP<12:0> bits are used in conjunction with the PTCON<3:0> bits field.

 2008-2017 Microchip Technology Inc. DS70000323H-page 11

High-Speed PWM Module

U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — SESTAT SEIEN EIPU

( )1

SYNCPOL

( , )1 2

SYNCOEN

(1, )2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SYNCEN

(1,2)

SYNCSRC<2:0>

(1)

SEVTPS<3:0>

(1)

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-13 Unimplemented: Read as ‘0’

bit 12 SESTAT: Special Event Trigger Interrupt Status bit

1 = Secondary Special Event Trigger interrupt is pending

0 = Secondary Special Event Trigger interrupt is not pending

This bit is cleared by setting SEIEN = 0.

bit 11 SEIEN: Special Event Trigger Interrupt Enable bit

1 = Secondary Special Event Trigger interrupt is enabled

0 = Secondary Special Event Trigger interrupt is disabled

bit 10 EIPU: Enable Immediate Period Updates bit

( )1

1 = Active Secondary Period register is updated immediately.

0 = Active Secondary Period register updates occur on PWM cycle boundaries

bit 9 SYNCPOL: Synchronize Input and Output Polarity bit

( , )1 2

1 = The falling edge of SYNCEN resets the SMTMR and the SYNCO2 output is active-low

0 = The rising edge of SYNCEN resets the SMTMR and the SYNCO2 output is active-high

bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit

( , )1 2

1 = SYNCO2 output is enabled

0 = SYNCO2 output is disabled

bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit

( , )1 2

1 = External synchronization of secondary time base is enabled

0 = External synchronization of secondary time base is disabled

bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits

( )1

011 = SYNCI4

010 = SYNCI3

001 = SYNCI2

000 = SYNCI1

bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits

( )1

1111 = 1:16 Postcale

•

0001 = 1:2 Postcale

0000 = 1:1 Postscale

Note 1: These bits should be changed only when PTEN = 0.

2: The PWM time base synchronization must only be used in the master time base with no phase shifting.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 12  2008-2017 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>

( ,1 2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Secondary Clock Prescaler (Divider) Select bits

( , )1 2

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

2: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty

cycle, phase shift, dead time, triggers, Leading-Edge Blanking (LEB) and PWM capture.

 2008-2017 Microchip Technology Inc. DS70000323H-page 13

High-Speed PWM Module

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

STPER<15:8>

( , )1 2

bit 15 bit 8

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0

STPER<7:0>

( , )1 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 STPER<15:0>: PWM Secondary Master Time Base (SMTMR) Period Value bits

( , )1 2

Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.

2: Any period value that is less than 0x0028 must have the Least Significant 3 bits (LSbs) set to ‘0’. This

yields a period resolution of 8.32 ns (at the fastest Auxiliary Clock rate) for these very short PWM period

pulses.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SSEVTCMP<12:5>

( , , )123

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SSEVTCMP<4:0>

( , , )123

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 SSEVTCMP<12:0>: PWM Secondary Special Event Compare Count Value bits

( , , )123

bit 2-0 Unimplemented: Read as ‘0’

Note 1: 1 LSb = 1.04 ns; therefore, the minimum SSEVTCMP resolution is 8.32 ns at the fastest PWM clock

divider setting (STCON2<2:0> = 000).

2: The secondary Special Event Trigger is generated on a compare match with the PWM Secondary Master

Time Base Counter (SMTMR).

3: The SSEVTCMP<12:0> bits are used in conjunction with the STCON<3:0> bits field.

dsPIC33/PIC24 Family Reference Manual

DS70000323H-page 14  2008-2017 Microchip Technology Inc.

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

CHPCLKEN — — — — — CHOPCLK<6:5>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CHOPCLK<4:0> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 CHPCLKEN: Enable Chop Clock Generator bit

1 = Chop clock generator is enabled

0 = Chop clock generator is disabled

bit 14-10 Unimplemented: Read as ‘0’

bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits

Value in 8.32 ns increments. The frequency of the chop clock signal is calculated as follows:

Chop Frequency = 1/(16.64 * (CHOP<6:0> + 1) * Primary Master PWM Input Clock/PCLKDIV<2:0>)

bit 2-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MDC<15:8>

( , , )123

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

MDC<7:0>

( , , )123

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 MDC<15:0>: PWM Master Duty Cycle Value bits

( , , )123

Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of: Period + 0x0008.

2: MDC<15:0> < 0x0008 will produce a 0% duty cycle. MDC<15:0> > Period + 0x0008 will produce a

100% duty cycle.

3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns to 40 ns, depending on the mode of

operation), the PWM duty cycle resolution will reduce from 1 LSb to 3 LSbs.

 2008-2017 Microchip Technology Inc. DS70000323H-page 15

High-Speed PWM Module

HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTSTAT

( )1

CLSTAT

( )1

TRGSTAT FLTIEN CLIEN TRGIEN ITB

( )3

MDCS

( )3

bit 15 bit 8

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

DTC<1:0>

( )3

DTCP

( , )3 6

— MTBS CAM

( , , )235

XPRES

( , )4 7

IUE

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 FLTSTAT: Fault Interrupt Status bit

( )1

1 = Fault interrupt is pending

0 = Fault interrupt is not pending

This bit is cleared by setting FLTIEN = 0.

bit 14 CLSTAT: Current-Limit Interrupt Status bit

( )1

1 = Current-limit interrupt is pending

0 = Current-limit interrupt is not pending

This bit is cleared by setting CLIEN = 0.

bit 13 TRGSTAT: Trigger Interrupt Status bit

1 = Trigger interrupt is pending

0 = Trigger interrupt is not pending

This bit is cleared by setting TRGIEN = 0.

bit 12 FLTIEN: Fault Interrupt Enable bit

1 = Fault interrupt is enabled

0 = Fault interrupt is disabled and the FLTSTAT bit is cleared

bit 11 CLIEN: Current-Limit Interrupt Enable bit

1 = Current-limit interrupt is enabled

0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared

bit 10 TRGIEN: Trigger Interrupt Enable bit

1 = A trigger event generates an IRQ

0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared

bit 9 ITB: Independent Time Base Mode bit

( )3

1 = PHASEx/SPHASEx registers provide the time base period for this PWM Generator

0 = PTPER/STPER registers provide timing for this PWM Generator

bit 8 MDCS: Master Duty Cycle Register Select bit

( )3

1 = MDC register provides duty cycle information for this PWM Generator

0 = PDCx and SDCx registers provide duty cycle information for this PWM Generator

Note 1: Software must clear the interrupt status and the corresponding IFSx bit in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled (PTEN = 1).

4: Configure FCLCONx<8> = 0 and PWMCONx<9> = 1 to operate in External Period Reset mode.

5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase-Shift and Dead-Time

registers. The highest CAM resolution available is 8.32 ns with the clock prescaler set to the fastest clock.

6: DTC<1:0> = 11 for DTCP to be effective or else, the DTCP bit is ignored.

7: In the True Independent PWM Output mode (PMOD<1:0> = 11 and ITB = 1) with XPRES = 1, the PWM

Generator still requires the signal arriving at the PWMxH pin to be inactive to reset the PWM counter.

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DS70000323H-page 16  2008-2017 Microchip Technology Inc.

bit 7-6 DTC<1:0>: Dead-Time Control bits

( )3

11 = Dead-Time Compensation mode

10 = Dead-time function is disabled

01 = Negative dead time is actively applied for all output modes

00 = Positive dead time is actively applied for all output modes

bit 5 DTCP: Dead-Time Compensation Polarity bit

( , )3 6

When Set to ‘1’:

If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.

If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.

When Set to ‘0’:

If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.

If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.

bit 4 Unimplemented: Read as ‘0’

bit 3 MTBS: Master Time Base Select bit

1 = PWM Generator uses the secondary master time base for synchronization and as the clock

source for the PWM generation logic (if secondary time base is available)

0 = PWM Generator uses the primary master time base for synchronization and as the clock source

for the PWM generation logic

bit 2 CAM: Center-Aligned Mode Enable bit

( , , )235

1 = Center-Aligned mode is enabled

0 = Edge-Aligned mode is enabled

bit 1 XPRES: External PWM Reset Control bit

( , )4 7

1 = Current-limit source resets the time base for this PWM Generator if it is in Independent Time Base

(ITB) mode

0 = External pins do not affect the PWM time base

bit 0 IUE: Immediate Update Enable bit

1 = Updates to the active MDC/PDCx/SDCx/PHASEx/SPHASEx registers are immediate

0 = Updates to the active MDC/PDCx/SDCx/PHASEx/SPHASEx registers are synchronized to the

local PWM time base.

Note 1: Software must clear the interrupt status and the corresponding IFSx bit in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled (PTEN = 1).

4: Configure FCLCONx<8> = 0 and PWMCONx<9> = 1 to operate in External Period Reset mode.

5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase-Shift and Dead-Time

registers. The highest CAM resolution available is 8.32 ns with the clock prescaler set to the fastest clock.

6: DTC<1:0> = 11 for DTCP to be effective or else, the DTCP bit is ignored.

7: In the True Independent PWM Output mode (PMOD<1:0> = 11 and ITB = 1) with XPRES = 1, the PWM

Generator still requires the signal arriving at the PWMxH pin to be inactive to reset the PWM counter.

 2008-2017 Microchip Technology Inc. DS70000323H-page 17

High-Speed PWM Module

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<15:8>

(,,,)1234

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PDCx<7:0>

(,,,)1234

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PDCx<15:0>: PWM Generator Duty Cycle Value bits

(,,,)1234

Note 1: In Independent Output mode, the PDCx bits control the PWMxH duty cycle only. In Complementary,

Redundant and Push-Pull PWM modes, the PDCx bits control the duty cycle of PWMxH and PWMxL.

2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of: Period + 0x0008.

3: PDC<15:0> < 0x0008 produces a 0% duty cycle. PDC<15:0> > Period + 0x0008 produces a

100% duty cycle.

4: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns to 40 ns, depending on the mode of

operation), the PWM duty cycle resolution will reduce from 1 LSb to 3 LSbs.

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DS70000323H-page 18  2008-2017 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SDCx<15:8>

(,,,)1234

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SDCx<7:0>

(,,,)1234

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 SDCx<15:0>: PWM Secondary Duty Cycle for the PWMxL Output Pin bits

(,,,)1234

Note 1: The SDCx bits are used in Independent Output mode only. When used in Independent Output mode, the

SDCx bits control the PWMxL duty cycle. These bits are ignored in other PWM modes.

2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of: Period + 0x0008.

3: SDC<15:0> < 0x0008 produces a 0% duty cycle. SDC<15:0> > Period + 0x0008 produces a

100% duty cycle.

4: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns to 40 ns, depending on the mode of

operation), PWM duty cycle resolution will reduce from 1 LSb to 3 LSbs.

 2008-2017 Microchip Technology Inc. DS70000323H-page 19

High-Speed PWM Module

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEx<15:8>

( , )1 2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PHASEx<7:0>

( , )1 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 PHASEx<15:0>: PWM Phase-Shift Value or Independent Time Base Period for the PWM Generator bits

(1,2)

Note 1: If PWMCONx<9> = 0 (Master Time Base mode), the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull PWM Output mode (IOCONx<11:10> = 00, 01 or 10);

PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs.

• True Independent PWM Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Phase-shift value for

PWMxH only.

• When the PHASEx/SPHASEx bits provide the phase shift with respect to the master time base, the

valid range of values is 0x0000 – Period.

2: If PWMCONx<9> = 1 (Independent Time Base mode), the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull PWM Output mode (IOCONx<11:10> = 00, 01 or 10);

PHASEx<15:0> = Independent Time Base period value for PWMxH and PWMxL outputs.

• True Independent PWM Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent Time

Base period value for PWMxH only.

• When the PHASEx/SPHASEx bits provide the local period, the valid range of values is

0x0010-0xFFF8.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SPHASEx<15:8>

( , )1 2

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SPHASEx<7:0>

( , )1 2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-0 SPHASEx<15:0>: PWM Secondary Phase Offset for the PWMxL Output Pin bits

( , )1 2

(used in Independent PWM mode only)

Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull PWM Output mode (IOCONx<11:10> = 00, 01 or 10);

SPHASEx<15:0> = Not used.

• True Independent PWM Output mode (IOCONx<11:10> = 11); SPHASEx<15:0> = Phase-shift value

for PWMxL only.

• When the PHASEx/SPHASEx bits provide the phase shift with respect to the master time base, the

valid range of values is 0x0000 – Period.

2: If PWMCONx<9> = 1, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull PWM Output mode (IOCONx<11:10> = 00, 01 or 10);

SPHASEx<15:0> = Not used.

• True Independent PWM Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent Time

Base period value for PWMxL only.

• When the PHASEx/SPHASEx bits provide the local period, the valid range of values is

0x0010-0xFFF8.

 2008-2017 Microchip Technology Inc. DS70000323H-page 21

High-Speed PWM Module

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — DTRx<13:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DTRx<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMxH Dead-Time Unit bits

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — ALTDTRx<13:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALTDTRx<7:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-14 Unimplemented: Read as ‘0’

bit 13-0 ALTDTRx<13:0>: Alternate Unsigned 14-Bit Dead-Time Value for PWMxL Dead-Time Unit bits

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R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

TRGDIV<3:0> — — — —

bit 15 bit 8

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DTM

( )1

— TRGSTRT<5:0>

( )2

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits

1111 = Trigger output for every 16th trigger event

1110 = Trigger output for every 15th trigger event

1101 = Trigger output for every 14th trigger event

1100 = Trigger output for every 13th trigger event

1011 = Trigger output for every 12th trigger event

1010 = Trigger output for every 11th trigger event

1001 = Trigger output for every 10th trigger event

1000 = Trigger output for every 9th trigger event

0111 = Trigger output for every 8th trigger event

0110 = Trigger output for every 7th trigger event

0101 = Trigger output for every 6th trigger event

0100 = Trigger output for every 5th trigger event

0011 = Trigger output for every 4th trigger event

0010 = Trigger output for every 3rd trigger event

0001 = Trigger output for every 2nd trigger event

0000 = Trigger output for every trigger event

bit 11-8 Unimplemented: Read as ‘0’

bit 7 DTM: Dual Trigger Mode bit

( )1

1 = Secondary trigger event is combined with the primary trigger event to create a PWM trigger

0 = Secondary trigger event is not combined with the primary trigger event to create a PWM trigger; two

separate PWM triggers are generated

bit 6 Unimplemented: Read as ‘0’

bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits

( )2

111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled

•

000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled

000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled

000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled

Note 1: The Secondary Trigger Event (STRIGx) cannot generate PWM trigger interrupts.

2: The trigger start event is synchronized with the rollover of the master/secondary master time base.

 2008-2017 Microchip Technology Inc. DS70000323H-page 23

High-Speed PWM Module

R/W-0/1 R/W-0/1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PENH

(,,,)1345

PENL

(,,,)1345

POLH

(,)1 3

POLL

(,)1 3

PMOD<1:0>

(,,)135

OVRENH

( )3

OVRENL

( )3

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OVRDAT<1:0>

(,)2 3

FLTDAT<1:0>

(,)2 3

CLDAT<1:0>

(,)2 3

SWAP

( )3

OSYNC

( )3

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 PENH: PWMxH Output Pin Ownership bit

(,,,)1345

1 = PWM module controls the PWMxH pin

0 = GPIO module controls the PWMxH pin

bit 14 PENL: PWMxL Output Pin Ownership bit

(,,,)1345

1 = PWM module controls the PWMxL pin

0 = GPIO module controls the PWMxL pin

bit 13 POLH: PWMxH Output Pin Polarity bit

(,)1 3

1 = PWMxH pin is active-low

0 = PWMxH pin is active-high

bit 12 POLL: PWMxL Output Pin Polarity bit

(,)1 3

1 = PWMxL pin is active-low

0 = PWMxL pin is active-high

bit 11-10 PMOD<1:0>: PWM # I/O Pin Mode bits

(,,)135

11 = PWM I/O pin pair is in the True Independent PWM Output mode

10 = PWM I/O pin pair is in the Push-Pull PWM Output mode

01 = PWM I/O pin pair is in the Redundant PWM Output mode

00 = PWM I/O pin pair is in the Complementary PWM Output mode

bit 9 OVRENH: Override Enable for PWMxH Pin bit

( )3

1 = OVRDAT1 provides data for output on the PWMxH pin

0 = PWM Generator provides data for the PWMxH pin

bit 8 OVRENL: Override Enable for PWMxL Pin bit

( )3

1 = OVRDAT0 provides data for output on the PWMxL pin

0 = PWM Generator provides data for the PWMxL pin

Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).

2: The state represents the active/inactive state of the PWM depending on the POLH and POLL bits.

3: On devices that support PWM unlock functionality, the IOCONx register bits are writable only after the

proper sequence of bits is written to the PWMKEY register. Refer to the specific device data sheet for the

availability of the PWMKEY register.

4: These bits are set (‘1’) by default on some devices. Refer to the specific device data sheet for more

information on the default status of these bits.

5: In a few devices, the PENH and PENL bits have a default state of ‘1’. In such devices, an unused or

unconfigured PWMxH pin will have a default low state and the PWMxL pin will have a default high state,

since the PMOD<1:0> bits are set to ‘0’ (Complementary mode) by default. In such devices, all PWM pairs

must be appropriately configured before enabling the PWM module (PTEN = ). Refer to the specific 1

device data sheet for the default status of the PENH and PENL bits.

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DS70000323H-page 24  2008-2017 Microchip Technology Inc.

bit 7-6 OVRDAT<1:0>: State for PWMxH and PWMxL Pins if Override is Enabled bits

(,)2 3

If OVRENH = 1, OVRDAT1 provides data for PWMxH.

If OVRENL = 1, OVRDAT0 provides data for PWMxL.

bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD<1:0> are Enabled bits

(,)2 3

FCLCONx<15> = 0: Normal Fault mode:

If Fault is active, then FLTDAT1 provides the state for PWMxH.

If Fault is active, then FLTDAT0 provides the state for PWMxL.

FCLCONx<15> = 1: Independent Fault mode:

If current limit is active, then FLTDAT1 provides the state for PWMxH.

If Fault is active, then FLTDAT0 provides the state for PWMxL.

bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits

(,)2 3

FCLCONx<15> = 0: Normal Fault mode:

If current limit is active, then CLDAT1 provides the state for PWMxH.

If current limit is active, then CLDAT0 provides the state for PWMxL.

FCLCONx<15> = 1: Independent Fault mode:

CLDAT<1:0> bits are ignored.

bit 1 SWAP: Swap PWMxH and PWMxL Pins bit

( )3

1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the

PWMxH pins

0 = PWMxH and PWMxL pins are mapped to their respective pins

bit 0 OSYNC: Output Override Synchronization bit

( )3

1 = Output overrides through the OVRDAT<1:0> bits are synchronized to the PWM time base

0 = Output overrides through the OVRDAT<1:0> bits occur on the next CPU clock boundary

Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).

2: The state represents the active/inactive state of the PWM depending on the POLH and POLL bits.

3: On devices that support PWM unlock functionality, the IOCONx register bits are writable only after the

proper sequence of bits is written to the PWMKEY register. Refer to the specific device data sheet for the

availability of the PWMKEY register.

4: These bits are set (‘1’) by default on some devices. Refer to the specific device data sheet for more

information on the default status of these bits.

5: In a few devices, the PENH and PENL bits have a default state of ‘1’. In such devices, an unused or

unconfigured PWMxH pin will have a default low state and the PWMxL pin will have a default high state,

since the PMOD<1:0> bits are set to ‘0’ (Complementary mode) by default. In such devices, all PWM pairs

must be appropriately configured before enabling the PWM module (PTEN = 1). Refer to the specific

device data sheet for the default status of the PENH and PENL bits.

 2008-2017 Microchip Technology Inc. DS70000323H-page 25

High-Speed PWM Module

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TRGCMP<12:5>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

TRGCMP<4:0> — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 TRGCMP<12:0>: Trigger Control Value bits

When the primary PWM functions in the local time base, this register contains the compare values

that can trigger the ADC module and generate a PWM trigger Interrupt Request (IRQ).

bit 2-0 Unimplemented: Read as ‘0’

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STRGCMP<12:5>

( )1

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

STRGCMP<4:0>

( )1

— — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 STRGCMP<12:0>: Secondary Trigger Control Value bits

( )1

When the secondary PWM functions in the local time base, this register contains the compare values

that can trigger the ADC module.

bit 2-0 Unimplemented: Read as ‘0’

Note 1: The STRIGx register bits cannot generate the PWM trigger interrupts.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IFLTMOD

( )4

CLSRC<4:0>

(,,)234

CLPOL

(,)1 4

CLMOD

( )4

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

FLTSRC<4:0>

(,,,)2345

FLTPOL

(,)1 4

FLTMOD<1:0>

( )4

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 IFLTMOD: Independent Fault Mode Enable bit

( )4

1 = In Independent Fault mode, the current-limit input maps FLTDAT1 to the PWMxH output and the Fault

input maps FLTDAT0 to the PWMxL output; the CLDAT<1:0> bits are not used for override functions

0 = In Normal Fault mode, the Current-Limit mode maps the CLDAT<1:0> bits to the PWMxH and

PWMxL outputs; the PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs

bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWM Generator # bits

(,,)234

These bits also specify the source for the Dead-Time Compensation Input Signal, DTCMPx. For more

information on the CLSRCx bits, refer to the specific device data sheet.

bit 9 CLPOL: Current-Limit Polarity for PWM Generator # bit

(,)1 4

1 = The selected current-limit source is active-low

0 = The selected current-limit source is active-high

bit 8 CLMOD: Current-Limit Mode Enable for PWM Generator # bit

( )4

1 = Current-Limit mode is enabled

0 = Current-Limit mode is disabled

bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits

(,,,)2345

For more information on encoding the FLTSRCx bits, refer to the specific device data sheet.

bit 2 FLTPOL: Fault Polarity for PWM Generator # bit

(,)1 4

1 = The selected Fault source is active-low

0 = The selected Fault source is active-high

Note 1: These bits should be changed only when PTEN = 0.

2: When Independent Fault mode is enabled (IFLTMOD = 1), ensure that the correct current-limit and Fault

sources are selected for PWMxH and PWMxL through the CLSRCx and FLTSRCx bits, respectively. For

example, in some devices, ‘0b0000’ encoding of the CLSRCx or FLTSRCx bits refers to the Fault 1

source. In such devices, if Fault 1 is selected for CLSRCx, then a different (or unused) Fault source must

be used for FLTSRCx in order to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.

Similarly, if Fault 1 is selected for FLTSRCx, then a different (or unused) Fault source must be used for

CLSRCx in order to prevent Fault 1 from disabling both the PWMxL and PWMxH outputs.

3: Refer to the “Pin Diagrams” section in the specific device data sheet for more details on the number of

available Fault pins.

4: On devices that support PWM unlock functionality, the FCLCONx register bits are writable only after the

proper sequence of bits is written to the PWMKEY register. Refer to the specific device data sheet for the

availability of the PWMKEY register.

5: On the dsPIC33EP family of devices, the default state of the FLTSRC<4:0> bits is ‘0b11111’ (R/W-1),

which represents FLT31. The PWMx signals remain latched to the states corresponding to the

FLTDAT<1:0> bits settings in the IOCONx register and the status of the I/O pin corresponding to FLT31 at

start-up. To clear the Fault condition, the Fault pin must first be pulled low externally or the internal

pull-down resistor in the CNPDx register can be enabled.

 2008-2017 Microchip Technology Inc. DS70000323H-page 27

High-Speed PWM Module

bit 1-0 FLTMOD<1:0>: Fault Mode for PWM Generator # bits

( )4

11 = Fault input is disabled

10 = Reserved

01 = The selected Fault source forces the PWMxH and PWMxL pins to the FLTDATx values (cycle)

00 = The selected Fault source forces the PWMxH and PWMxL pins to the FLTDATx values (latched

condition)